Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16611745	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

159518600

1

T1

71087

T2

1586

T3

9176

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	86741178	1			T1	38867		T2	898		T3	4552
values[0x0]	43045857	1			T1	18883		T2	366		T3	2254
values[0x1]	46343310	1			T1	20484		T2	487		T3	2370

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8452277	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

167678068

1

T1

74726

T2

1683

T3

9176

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2801622	1			T1	302		T2	5		T3	45
valid_sources[0x01]	633073	1			T1	361		T2	2		T3	34
valid_sources[0x02]	609450	1			T1	282		T2	19		T3	39
valid_sources[0x03]	641200	1			T1	375		T2	9		T3	56
valid_sources[0x04]	597052	1			T1	304		T2	4		T3	27
valid_sources[0x05]	599339	1			T1	382		T2	2		T3	3
valid_sources[0x06]	629822	1			T1	304		T2	5		T3	44
valid_sources[0x07]	566076	1			T1	301		T2	10		T3	38
valid_sources[0x08]	602998	1			T1	282		T2	5		T3	36
valid_sources[0x09]	644892	1			T1	276		T2	8		T3	62
valid_sources[0x0a]	574404	1			T1	267		T2	7		T3	41
valid_sources[0x0b]	565215	1			T1	352		T2	5		T3	32
valid_sources[0x0c]	594947	1			T1	276		T2	4		T3	14
valid_sources[0x0d]	559670	1			T1	376		T2	8		T3	32
valid_sources[0x0e]	581008	1			T1	272		T2	8		T3	47
valid_sources[0x0f]	571082	1			T1	271		T2	11		T3	35
valid_sources[0x10]	627163	1			T1	346		T2	8		T3	49
valid_sources[0x11]	597470	1			T1	312		T2	5		T3	34
valid_sources[0x12]	599185	1			T1	264		T2	7		T3	38
valid_sources[0x13]	557291	1			T1	262		T2	17		T3	52
valid_sources[0x14]	580776	1			T1	291		T2	10		T3	86
valid_sources[0x15]	584706	1			T1	390		T2	2		T3	97
valid_sources[0x16]	645376	1			T1	308		T3	60		T4	39
valid_sources[0x17]	645283	1			T1	256		T2	5		T3	31
valid_sources[0x18]	797076	1			T1	338		T2	10		T3	18
valid_sources[0x19]	569038	1			T1	365		T2	1		T3	55
valid_sources[0x1a]	595550	1			T1	339		T2	3		T3	63
valid_sources[0x1b]	599159	1			T1	266		T2	11		T3	21
valid_sources[0x1c]	770390	1			T1	336		T2	8		T3	16
valid_sources[0x1d]	595451	1			T1	232		T2	11		T3	55
valid_sources[0x1e]	579855	1			T1	297		T2	8		T3	21
valid_sources[0x1f]	1497131	1			T1	301		T2	3		T3	57
valid_sources[0x20]	596350	1			T1	367		T2	5		T3	43
valid_sources[0x21]	575841	1			T1	283		T2	2		T3	54
valid_sources[0x22]	591381	1			T1	325		T2	5		T3	47
valid_sources[0x23]	567900	1			T1	280		T2	11		T3	24
valid_sources[0x24]	570544	1			T1	302		T2	11		T3	15
valid_sources[0x25]	575177	1			T1	303		T2	8		T3	29
valid_sources[0x26]	571697	1			T1	330		T2	6		T3	44
valid_sources[0x27]	614074	1			T1	288		T2	4		T3	14
valid_sources[0x28]	598809	1			T1	326		T2	6		T3	33
valid_sources[0x29]	568319	1			T1	380		T2	13		T3	19
valid_sources[0x2a]	629909	1			T1	237		T2	8		T3	34
valid_sources[0x2b]	601054	1			T1	253		T2	5		T3	31
valid_sources[0x2c]	695389	1			T1	304		T2	17		T3	29
valid_sources[0x2d]	579880	1			T1	362		T2	4		T3	32
valid_sources[0x2e]	601547	1			T1	271		T2	8		T3	42
valid_sources[0x2f]	565265	1			T1	265		T2	4		T3	38
valid_sources[0x30]	563687	1			T1	361		T2	12		T3	18
valid_sources[0x31]	583032	1			T1	327		T2	10		T3	2
valid_sources[0x32]	595803	1			T1	335		T2	11		T3	37
valid_sources[0x33]	596031	1			T1	357		T2	5		T3	48
valid_sources[0x34]	580380	1			T1	318		T2	8		T3	44
valid_sources[0x35]	582801	1			T1	363		T2	6		T3	61
valid_sources[0x36]	607373	1			T1	288		T2	3		T3	59
valid_sources[0x37]	567669	1			T1	289		T2	26		T3	44
valid_sources[0x38]	583331	1			T1	303		T2	2		T3	47
valid_sources[0x39]	607473	1			T1	353		T2	5		T3	21
valid_sources[0x3a]	572306	1			T1	323		T2	4		T3	27
valid_sources[0x3b]	614340	1			T1	285		T2	8		T3	57
valid_sources[0x3c]	612782	1			T1	381		T2	2		T3	33
valid_sources[0x3d]	603268	1			T1	263		T2	4		T3	10
valid_sources[0x3e]	605902	1			T1	316		T2	9		T3	80
valid_sources[0x3f]	561533	1			T1	316		T2	4		T3	14
valid_sources[0x40]	572714	1			T1	292		T2	3		T3	14
valid_sources[0x41]	569257	1			T1	336		T2	4		T3	22
valid_sources[0x42]	559602	1			T1	293		T2	11		T3	56
valid_sources[0x43]	567738	1			T1	336		T2	8		T3	8
valid_sources[0x44]	625071	1			T1	294		T2	3		T3	56
valid_sources[0x45]	622347	1			T1	256		T2	10		T3	26
valid_sources[0x46]	562074	1			T1	288		T2	9		T3	22
valid_sources[0x47]	581984	1			T1	331		T2	5		T3	5
valid_sources[0x48]	566450	1			T1	291		T2	1		T3	38
valid_sources[0x49]	582810	1			T1	309		T2	12		T3	73
valid_sources[0x4a]	589229	1			T1	280		T2	5		T3	17
valid_sources[0x4b]	597498	1			T1	329		T2	1		T3	85
valid_sources[0x4c]	590472	1			T1	292		T2	7		T3	30
valid_sources[0x4d]	564920	1			T1	238		T2	6		T3	35
valid_sources[0x4e]	614173	1			T1	305		T2	5		T3	51
valid_sources[0x4f]	583176	1			T1	349		T2	8		T3	26
valid_sources[0x50]	583573	1			T1	353		T2	7		T3	42
valid_sources[0x51]	701747	1			T1	347		T2	11		T3	33
valid_sources[0x52]	596138	1			T1	388		T2	6		T3	23
valid_sources[0x53]	2218827	1			T1	397		T2	7		T3	5
valid_sources[0x54]	1508686	1			T1	298		T2	2		T3	8
valid_sources[0x55]	588937	1			T1	245		T2	4		T3	6
valid_sources[0x56]	561129	1			T1	351		T2	24		T3	19
valid_sources[0x57]	590488	1			T1	316		T2	7		T3	3
valid_sources[0x58]	568453	1			T1	330		T2	10		T3	14
valid_sources[0x59]	599237	1			T1	287		T2	6		T3	23
valid_sources[0x5a]	591612	1			T1	327		T2	6		T3	41
valid_sources[0x5b]	566243	1			T1	302		T2	5		T3	29
valid_sources[0x5c]	627312	1			T1	335		T2	5		T3	16
valid_sources[0x5d]	565447	1			T1	235		T2	10		T3	30
valid_sources[0x5e]	600270	1			T1	361		T2	3		T3	30
valid_sources[0x5f]	715882	1			T1	332		T2	7		T3	4
valid_sources[0x60]	582074	1			T1	267		T2	10		T3	11
valid_sources[0x61]	1070277	1			T1	256		T2	4		T3	32
valid_sources[0x62]	560045	1			T1	310		T2	1		T3	33
valid_sources[0x63]	562345	1			T1	285		T2	8		T3	41
valid_sources[0x64]	634995	1			T1	307		T2	7		T3	29
valid_sources[0x65]	1391465	1			T1	296		T2	10		T3	80
valid_sources[0x66]	566706	1			T1	297		T2	8		T3	28
valid_sources[0x67]	672348	1			T1	305		T2	8		T3	52
valid_sources[0x68]	567752	1			T1	398		T2	8		T3	21
valid_sources[0x69]	1573230	1			T1	366		T2	7		T3	52
valid_sources[0x6a]	559352	1			T1	317		T2	11		T3	90
valid_sources[0x6b]	628458	1			T1	213		T2	5		T3	44
valid_sources[0x6c]	563649	1			T1	319		T2	4		T3	77
valid_sources[0x6d]	1039773	1			T1	208		T2	1		T3	19
valid_sources[0x6e]	598284	1			T1	226		T2	4		T3	43
valid_sources[0x6f]	559108	1			T1	355		T2	10		T3	35
valid_sources[0x70]	569006	1			T1	232		T2	3		T3	18
valid_sources[0x71]	564571	1			T1	312		T2	7		T3	25
valid_sources[0x72]	630278	1			T1	279		T2	6		T3	18
valid_sources[0x73]	606145	1			T1	273		T2	8		T3	51
valid_sources[0x74]	783209	1			T1	238		T2	1		T3	26
valid_sources[0x75]	603148	1			T1	325		T2	1		T3	42
valid_sources[0x76]	662126	1			T1	333		T2	5		T3	29
valid_sources[0x77]	571482	1			T1	275		T2	16		T3	74
valid_sources[0x78]	620620	1			T1	253		T2	8		T3	33
valid_sources[0x79]	615887	1			T1	333		T2	8		T3	48
valid_sources[0x7a]	662425	1			T1	293		T2	5		T3	28
valid_sources[0x7b]	613751	1			T1	327		T2	8		T3	31
valid_sources[0x7c]	773831	1			T1	316		T2	7		T3	23
valid_sources[0x7d]	631059	1			T1	295		T2	7		T3	16
valid_sources[0x7e]	615478	1			T1	291		T2	5		T3	32
valid_sources[0x7f]	567623	1			T1	282		T2	1		T3	53
valid_sources[0x80]	571203	1			T1	351		T2	14		T3	20

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

78389046

1

T1

35322

T2

823

T3

4552

values[0x0]

all_enables

biggest_size

40567458

1

T1

17775

T2

347

T3

2254

values[0x1]

all_enables

biggest_size

40562096

1

T1

17990

T2

416

T3

2370

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	43525	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

137993

1

T1

2

T2

14

T6

72

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	49539	1			T2	18		T7	31		T8	24
values[0x0]	63659	1			T1	2		T2	9		T3	1
values[0x1]	68320	1			T1	4		T2	10		T3	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	33986	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

147532

1

T1

3

T2

15

T5

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	725	1			T2	1		T102	1		T24	10
valid_sources[0x01]	705	1			T102	2		T20	2		T21	1
valid_sources[0x02]	733	1			T44	2		T102	1		T104	1
valid_sources[0x03]	645	1			T2	1		T21	1		T24	15
valid_sources[0x04]	606	1			T44	5		T21	1		T24	16
valid_sources[0x05]	678	1			T10	1		T24	26		T131	1
valid_sources[0x06]	703	1			T52	1		T166	5		T24	6
valid_sources[0x07]	615	1			T13	3		T44	1		T104	1
valid_sources[0x08]	600	1			T44	4		T24	9		T26	3
valid_sources[0x09]	557	1			T41	3		T102	1		T24	7
valid_sources[0x0a]	553	1			T44	5		T24	15		T77	1
valid_sources[0x0b]	585	1			T3	1		T13	1		T21	1
valid_sources[0x0c]	935	1			T2	2		T44	1		T102	1
valid_sources[0x0d]	730	1			T2	1		T102	1		T21	1
valid_sources[0x0e]	618	1			T10	1		T104	1		T24	10
valid_sources[0x0f]	647	1			T10	1		T52	1		T44	4
valid_sources[0x10]	658	1			T102	1		T20	10		T24	9
valid_sources[0x11]	609	1			T20	13		T24	11		T167	2
valid_sources[0x12]	610	1			T102	2		T75	6		T21	1
valid_sources[0x13]	702	1			T24	13		T15	1		T26	51
valid_sources[0x14]	667	1			T2	1		T19	1		T24	16
valid_sources[0x15]	697	1			T1	6		T104	1		T21	1
valid_sources[0x16]	695	1			T21	2		T168	1		T24	7
valid_sources[0x17]	748	1			T68	9		T20	5		T21	1
valid_sources[0x18]	649	1			T44	1		T102	1		T24	10
valid_sources[0x19]	512	1			T19	1		T44	1		T102	1
valid_sources[0x1a]	531	1			T41	1		T19	1		T102	1
valid_sources[0x1b]	734	1			T20	1		T24	11		T76	13
valid_sources[0x1c]	883	1			T4	1		T24	13		T25	26
valid_sources[0x1d]	552	1			T44	4		T104	1		T24	23
valid_sources[0x1e]	586	1			T19	1		T104	1		T20	10
valid_sources[0x1f]	702	1			T24	13		T53	13		T162	3
valid_sources[0x20]	533	1			T41	1		T24	11		T51	1
valid_sources[0x21]	633	1			T44	1		T20	6		T24	17
valid_sources[0x22]	748	1			T2	1		T21	1		T24	11
valid_sources[0x23]	667	1			T102	1		T21	2		T24	10
valid_sources[0x24]	691	1			T21	1		T24	6		T76	12
valid_sources[0x25]	921	1			T102	2		T20	2		T21	3
valid_sources[0x26]	1072	1			T20	3		T24	14		T26	39
valid_sources[0x27]	724	1			T44	4		T104	1		T24	20
valid_sources[0x28]	775	1			T5	2		T19	1		T24	9
valid_sources[0x29]	529	1			T2	1		T102	1		T24	12
valid_sources[0x2a]	508	1			T27	1		T8	4		T24	15
valid_sources[0x2b]	891	1			T44	4		T24	15		T51	7
valid_sources[0x2c]	871	1			T104	1		T24	14		T53	1
valid_sources[0x2d]	595	1			T102	1		T21	1		T24	12
valid_sources[0x2e]	608	1			T13	1		T27	1		T104	1
valid_sources[0x2f]	518	1			T21	2		T24	6		T26	15
valid_sources[0x30]	780	1			T41	1		T44	2		T168	1
valid_sources[0x31]	523	1			T2	1		T102	1		T24	10
valid_sources[0x32]	521	1			T13	1		T24	13		T169	1
valid_sources[0x33]	591	1			T27	6		T24	19		T26	9
valid_sources[0x34]	752	1			T27	1		T102	1		T104	1
valid_sources[0x35]	682	1			T102	1		T104	1		T21	1
valid_sources[0x36]	801	1			T6	274		T20	1		T24	15
valid_sources[0x37]	719	1			T2	1		T24	9		T42	3
valid_sources[0x38]	810	1			T21	1		T168	1		T24	13
valid_sources[0x39]	556	1			T102	1		T21	1		T24	10
valid_sources[0x3a]	631	1			T41	5		T44	2		T102	3
valid_sources[0x3b]	691	1			T102	1		T24	12		T25	2
valid_sources[0x3c]	629	1			T20	2		T24	8		T76	2
valid_sources[0x3d]	509	1			T2	1		T24	12		T25	1
valid_sources[0x3e]	594	1			T2	1		T10	2		T24	6
valid_sources[0x3f]	684	1			T102	1		T24	12		T49	58
valid_sources[0x40]	622	1			T44	1		T24	15		T76	2
valid_sources[0x41]	812	1			T44	6		T24	16		T25	1
valid_sources[0x42]	814	1			T10	3		T41	1		T24	15
valid_sources[0x43]	736	1			T24	12		T49	1		T169	1
valid_sources[0x44]	864	1			T24	7		T77	1		T23	1
valid_sources[0x45]	574	1			T20	1		T21	3		T24	14
valid_sources[0x46]	568	1			T44	1		T21	1		T24	6
valid_sources[0x47]	567	1			T20	2		T24	14		T170	5
valid_sources[0x48]	559	1			T24	13		T25	2		T23	1
valid_sources[0x49]	601	1			T13	1		T41	1		T102	2
valid_sources[0x4a]	806	1			T44	3		T112	3		T24	12
valid_sources[0x4b]	696	1			T21	1		T24	7		T26	22
valid_sources[0x4c]	559	1			T24	19		T25	3		T162	1
valid_sources[0x4d]	574	1			T2	1		T10	1		T24	16
valid_sources[0x4e]	701	1			T5	1		T102	1		T24	7
valid_sources[0x4f]	611	1			T2	1		T171	3		T24	13
valid_sources[0x50]	511	1			T2	1		T44	14		T24	10
valid_sources[0x51]	868	1			T10	1		T44	3		T102	3
valid_sources[0x52]	1322	1			T10	1		T21	2		T24	8
valid_sources[0x53]	825	1			T24	10		T25	5		T53	9
valid_sources[0x54]	685	1			T102	2		T8	34		T24	16
valid_sources[0x55]	844	1			T27	3		T171	5		T21	1
valid_sources[0x56]	637	1			T2	1		T41	2		T44	2
valid_sources[0x57]	1070	1			T10	1		T27	2		T24	12
valid_sources[0x58]	729	1			T102	1		T24	15		T77	2
valid_sources[0x59]	766	1			T44	3		T102	1		T104	1
valid_sources[0x5a]	628	1			T44	3		T21	1		T24	5
valid_sources[0x5b]	807	1			T104	1		T24	17		T23	1
valid_sources[0x5c]	877	1			T8	13		T20	11		T21	1
valid_sources[0x5d]	736	1			T172	1		T24	13		T169	2
valid_sources[0x5e]	664	1			T20	2		T24	15		T42	1
valid_sources[0x5f]	672	1			T24	16		T88	2		T25	61
valid_sources[0x60]	766	1			T21	1		T24	12		T23	1
valid_sources[0x61]	498	1			T19	1		T44	2		T102	1
valid_sources[0x62]	521	1			T104	1		T24	9		T23	2
valid_sources[0x63]	502	1			T24	10		T25	3		T23	3
valid_sources[0x64]	531	1			T24	11		T173	7		T60	1
valid_sources[0x65]	843	1			T44	1		T24	12		T54	4
valid_sources[0x66]	1136	1			T2	1		T7	212		T27	1
valid_sources[0x67]	550	1			T44	7		T24	19		T51	1
valid_sources[0x68]	790	1			T44	1		T21	1		T24	15
valid_sources[0x69]	668	1			T44	4		T102	1		T21	1
valid_sources[0x6a]	863	1			T19	1		T168	2		T24	16
valid_sources[0x6b]	604	1			T44	3		T24	7		T25	1
valid_sources[0x6c]	579	1			T102	1		T100	1		T24	10
valid_sources[0x6d]	829	1			T102	1		T21	1		T24	20
valid_sources[0x6e]	847	1			T24	14		T25	1		T51	5
valid_sources[0x6f]	644	1			T24	10		T51	3		T174	1
valid_sources[0x70]	740	1			T21	1		T24	7		T82	2
valid_sources[0x71]	1013	1			T19	1		T21	1		T24	12
valid_sources[0x72]	673	1			T44	4		T102	1		T171	2
valid_sources[0x73]	658	1			T27	3		T44	2		T102	2
valid_sources[0x74]	766	1			T2	1		T20	6		T21	1
valid_sources[0x75]	716	1			T19	1		T20	1		T24	21
valid_sources[0x76]	535	1			T19	1		T175	1		T129	1
valid_sources[0x77]	885	1			T10	1		T102	1		T21	1
valid_sources[0x78]	652	1			T41	2		T102	1		T21	1
valid_sources[0x79]	606	1			T20	5		T24	14		T25	39
valid_sources[0x7a]	655	1			T102	1		T24	10		T60	1
valid_sources[0x7b]	607	1			T102	1		T128	1		T21	2
valid_sources[0x7c]	939	1			T21	1		T24	7		T23	2
valid_sources[0x7d]	943	1			T9	1		T24	12		T25	3
valid_sources[0x7e]	1137	1			T2	1		T104	1		T24	17
valid_sources[0x7f]	489	1			T41	2		T20	3		T24	13
valid_sources[0x80]	755	1			T21	1		T24	8		T176	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

36935

1

T2

8

T7

16

T8

8

values[0x0]

all_enables

biggest_size

51869

1

T1

1

T2

3

T6

44

values[0x1]

all_enables

biggest_size

49189

1

T1

1

T2

3

T6

28