Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16507006

1

T1

7147

T2

49

T4

1807

full_word

156635932

1

T1

71087

T2

481

T3

9176

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	173142628	1			T1	78234		T2	530		T3	9176
auto[TlIntgErrCmd]	92	1			T69	4		T70	3		T71	10
auto[TlIntgErrData]	114	1			T69	4		T70	4		T71	7
auto[TlIntgErrBoth]	104	1			T69	2		T70	3		T71	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

83686579

1

T1

38867

T2

280

T3

4552

auto[1]

89456359

1

T1

39367

T2

250

T3

4624

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	8108577	1			T1	3545		T2	22		T4	921
auto[TlIntgErrNone]	partial	auto[1]	8398147	1			T1	3602		T2	27		T4	886
auto[TlIntgErrNone]	full_word	auto[0]	75577869	1			T1	35322		T2	258		T3	4552
auto[TlIntgErrNone]	full_word	auto[1]	81058035	1			T1	35765		T2	223		T3	4624
auto[TlIntgErrCmd]	partial	auto[0]	33	1			T69	1		T70	2		T71	3
auto[TlIntgErrCmd]	partial	auto[1]	48	1			T69	3		T71	5		T151	2
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T71	1		T151	1		T156	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T70	1		T71	1		T158	1
auto[TlIntgErrData]	partial	auto[0]	43	1			T69	2		T70	1		T71	1
auto[TlIntgErrData]	partial	auto[1]	61	1			T69	1		T70	2		T71	5
auto[TlIntgErrData]	full_word	auto[0]	4	1			T71	1		T157	1		T158	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T69	1		T70	1		T156	1
auto[TlIntgErrBoth]	partial	auto[0]	45	1			T71	2		T151	2		T147	5
auto[TlIntgErrBoth]	partial	auto[1]	52	1			T69	2		T70	3		T71	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T158	1		T150	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T157	2		T149	2		T153	1