Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	984313	1			T1	152		T5	3251		T7	45329
auto[1]	11284014	1			T1	1100		T2	246		T3	4552
auto[2]	761170	1			T1	71		T5	2396		T11	1
auto[3]	10991648	1			T1	1086		T2	213		T3	4623

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14562367	1			T1	1695		T2	364		T3	9175
auto[1]	2288626	1			T1	271		T2	57		T4	1434
auto[2]	2327695	1			T1	390		T2	36		T4	1495
auto[3]	4842457	1			T1	53		T2	2		T4	312

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9643728

1

T1

2409

T2

459

T3

9175

auto[1]

14377417

1

T4

1

T5

24844

T7

4

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	449102	1			T1	121		T7	37347		T27	5512
auto[0]	auto[0]	auto[1]	46853	1			T1	15		T7	3845		T27	522
auto[0]	auto[0]	auto[2]	46581	1			T1	16		T7	3744		T27	521
auto[0]	auto[0]	auto[3]	76596	1			T7	392		T27	36		T20	100
auto[0]	auto[1]	auto[0]	3245901	1			T1	832		T2	193		T3	4552
auto[0]	auto[1]	auto[1]	350428	1			T1	168		T2	36		T4	702
auto[0]	auto[1]	auto[2]	362309	1			T1	77		T2	16		T4	763
auto[0]	auto[1]	auto[3]	439025	1			T1	23		T2	1		T4	158
auto[0]	auto[2]	auto[0]	334689	1			T7	32632		T27	3095		T8	1
auto[0]	auto[2]	auto[1]	38687	1			T7	3277		T27	287		T20	592
auto[0]	auto[2]	auto[2]	33937	1			T1	62		T7	2519		T27	214
auto[0]	auto[2]	auto[3]	53022	1			T1	9		T11	1		T7	234
auto[0]	auto[3]	auto[0]	3071365	1			T1	742		T2	171		T3	4623
auto[0]	auto[3]	auto[1]	340461	1			T1	88		T2	21		T4	732
auto[0]	auto[3]	auto[2]	359064	1			T1	235		T2	20		T4	732
auto[0]	auto[3]	auto[3]	395708	1			T1	21		T2	1		T4	154
auto[1]	auto[0]	auto[0]	12244	1			T5	96		T7	1		T100	125
auto[1]	auto[0]	auto[1]	54137	1			T5	492		T100	537		T128	1598
auto[1]	auto[0]	auto[2]	54210	1			T5	499		T100	513		T128	1639
auto[1]	auto[0]	auto[3]	244590	1			T5	2164		T100	2426		T128	7525
auto[1]	auto[1]	auto[0]	3722012	1			T4	1		T5	231		T68	1
auto[1]	auto[1]	auto[1]	726583	1			T5	1685		T7	1		T100	1666
auto[1]	auto[1]	auto[2]	706923	1			T5	918		T99	1		T100	1049
auto[1]	auto[1]	auto[3]	1730833	1			T5	7200		T100	7558		T128	8587
auto[1]	auto[2]	auto[0]	8673	1			T7	2		T128	183		T164	321
auto[1]	auto[2]	auto[1]	39724	1			T128	965		T164	1395		T165	3848
auto[1]	auto[2]	auto[2]	45583	1			T5	442		T100	470		T128	1695
auto[1]	auto[2]	auto[3]	206855	1			T5	1954		T100	2250		T128	7941
auto[1]	auto[3]	auto[0]	3718381	1			T5	93		T52	1		T41	2
auto[1]	auto[3]	auto[1]	691753	1			T5	369		T100	448		T128	390
auto[1]	auto[3]	auto[2]	719088	1			T5	1637		T41	1		T100	1595
auto[1]	auto[3]	auto[3]	1695828	1			T5	7064		T100	7108		T128	9391