Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1168708241	194924	0	0
ctrl_regwen_rd_A	1168708241	4260	0	0
exec_rd_A	1168708241	4043	0	0
exec_regwen_rd_A	1168708241	4289	0	0
readback_rd_A	1168708241	2578	0	0
readback_regwen_rd_A	1168708241	2231	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1168708241	194924	0	0
T24	72214	4803	0	0
T25	0	4987	0	0
T26	0	7306	0	0
T42	461754	0	0	0
T45	0	4054	0	0
T50	0	6370	0	0
T55	0	6408	0	0
T76	524611	0	0	0
T78	0	1218	0	0
T79	0	1076	0	0
T80	0	1376	0	0
T81	0	2058	0	0
T82	71823	0	0	0
T83	451465	0	0	0
T84	52970	0	0	0
T85	86741	0	0	0
T86	280453	0	0	0
T87	183403	0	0	0
T88	937673	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1168708241	4260	0	0
T45	0	336	0	0
T46	0	619	0	0
T50	150117	0	0	0
T78	39704	95	0	0
T79	19209	51	0	0
T134	0	82	0	0
T135	0	196	0	0
T136	0	170	0	0
T137	0	180	0	0
T138	0	78	0	0
T139	0	72	0	0
T140	655022	0	0	0
T141	71427	0	0	0
T142	116946	0	0	0
T143	152923	0	0	0
T144	105103	0	0	0
T145	421021	0	0	0
T146	400190	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1168708241	4043	0	0
T45	0	252	0	0
T46	0	437	0	0
T50	150117	0	0	0
T78	39704	118	0	0
T79	19209	48	0	0
T134	0	88	0	0
T135	0	150	0	0
T136	0	99	0	0
T137	0	200	0	0
T138	0	91	0	0
T139	0	34	0	0
T140	655022	0	0	0
T141	71427	0	0	0
T142	116946	0	0	0
T143	152923	0	0	0
T144	105103	0	0	0
T145	421021	0	0	0
T146	400190	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1168708241	4289	0	0
T45	0	335	0	0
T46	0	502	0	0
T50	150117	0	0	0
T78	39704	118	0	0
T79	19209	61	0	0
T134	0	80	0	0
T135	0	247	0	0
T136	0	122	0	0
T137	0	213	0	0
T138	0	124	0	0
T139	0	83	0	0
T140	655022	0	0	0
T141	71427	0	0	0
T142	116946	0	0	0
T143	152923	0	0	0
T144	105103	0	0	0
T145	421021	0	0	0
T146	400190	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1168708241	2578	0	0
T45	0	364	0	0
T46	0	477	0	0
T50	150117	0	0	0
T78	39704	60	0	0
T79	19209	52	0	0
T134	0	45	0	0
T135	0	188	0	0
T136	0	95	0	0
T137	0	197	0	0
T138	0	74	0	0
T139	0	54	0	0
T140	655022	0	0	0
T141	71427	0	0	0
T142	116946	0	0	0
T143	152923	0	0	0
T144	105103	0	0	0
T145	421021	0	0	0
T146	400190	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1168708241	2231	0	0
T45	0	309	0	0
T46	0	423	0	0
T50	150117	0	0	0
T78	39704	89	0	0
T79	19209	55	0	0
T134	0	32	0	0
T135	0	150	0	0
T136	0	75	0	0
T137	0	160	0	0
T138	0	46	0	0
T139	0	52	0	0
T140	655022	0	0	0
T141	71427	0	0	0
T142	116946	0	0	0
T143	152923	0	0	0
T144	105103	0	0	0
T145	421021	0	0	0
T146	400190	0	0	0