| T795 |
/workspace/coverage/default/28.sram_ctrl_partial_access_b2b.1403164415 |
|
|
Jul 06 04:42:58 PM PDT 24 |
Jul 06 04:50:04 PM PDT 24 |
18029877429 ps |
| T796 |
/workspace/coverage/default/45.sram_ctrl_ram_cfg.20177288 |
|
|
Jul 06 04:44:25 PM PDT 24 |
Jul 06 04:44:30 PM PDT 24 |
1410793853 ps |
| T797 |
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.1140590042 |
|
|
Jul 06 04:42:11 PM PDT 24 |
Jul 06 04:42:28 PM PDT 24 |
1418462384 ps |
| T798 |
/workspace/coverage/default/13.sram_ctrl_partial_access_b2b.1564196032 |
|
|
Jul 06 04:42:37 PM PDT 24 |
Jul 06 04:46:56 PM PDT 24 |
4541854585 ps |
| T799 |
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.1497322109 |
|
|
Jul 06 04:42:10 PM PDT 24 |
Jul 06 04:42:46 PM PDT 24 |
1072695741 ps |
| T800 |
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.2316364932 |
|
|
Jul 06 04:42:00 PM PDT 24 |
Jul 06 04:43:44 PM PDT 24 |
3272973632 ps |
| T801 |
/workspace/coverage/default/3.sram_ctrl_smoke.1167594956 |
|
|
Jul 06 04:42:09 PM PDT 24 |
Jul 06 04:42:26 PM PDT 24 |
3692004656 ps |
| T802 |
/workspace/coverage/default/18.sram_ctrl_lc_escalation.3502859423 |
|
|
Jul 06 04:42:44 PM PDT 24 |
Jul 06 04:43:40 PM PDT 24 |
10308060686 ps |
| T803 |
/workspace/coverage/default/14.sram_ctrl_partial_access_b2b.3114546217 |
|
|
Jul 06 04:42:36 PM PDT 24 |
Jul 06 04:52:12 PM PDT 24 |
88266973637 ps |
| T804 |
/workspace/coverage/default/46.sram_ctrl_regwen.2427646826 |
|
|
Jul 06 04:44:31 PM PDT 24 |
Jul 06 04:46:29 PM PDT 24 |
23347836290 ps |
| T805 |
/workspace/coverage/default/34.sram_ctrl_ram_cfg.244117256 |
|
|
Jul 06 04:43:31 PM PDT 24 |
Jul 06 04:43:35 PM PDT 24 |
365018861 ps |
| T806 |
/workspace/coverage/default/24.sram_ctrl_partial_access_b2b.1384430572 |
|
|
Jul 06 04:42:59 PM PDT 24 |
Jul 06 04:50:06 PM PDT 24 |
38048461363 ps |
| T807 |
/workspace/coverage/default/40.sram_ctrl_bijection.1893392664 |
|
|
Jul 06 04:43:54 PM PDT 24 |
Jul 06 04:56:58 PM PDT 24 |
69114415786 ps |
| T808 |
/workspace/coverage/default/13.sram_ctrl_stress_all.811856142 |
|
|
Jul 06 04:42:37 PM PDT 24 |
Jul 06 05:17:52 PM PDT 24 |
333238700322 ps |
| T809 |
/workspace/coverage/default/17.sram_ctrl_smoke.4217525389 |
|
|
Jul 06 04:42:46 PM PDT 24 |
Jul 06 04:42:50 PM PDT 24 |
695371341 ps |
| T810 |
/workspace/coverage/default/17.sram_ctrl_stress_pipeline.2237077293 |
|
|
Jul 06 04:42:47 PM PDT 24 |
Jul 06 04:48:19 PM PDT 24 |
36251783240 ps |
| T811 |
/workspace/coverage/default/44.sram_ctrl_multiple_keys.765267396 |
|
|
Jul 06 04:44:19 PM PDT 24 |
Jul 06 05:01:57 PM PDT 24 |
103082529533 ps |
| T812 |
/workspace/coverage/default/39.sram_ctrl_access_during_key_req.3640621265 |
|
|
Jul 06 04:43:56 PM PDT 24 |
Jul 06 04:52:35 PM PDT 24 |
4244341316 ps |
| T813 |
/workspace/coverage/default/2.sram_ctrl_max_throughput.3690881181 |
|
|
Jul 06 04:42:00 PM PDT 24 |
Jul 06 04:43:58 PM PDT 24 |
3119538763 ps |
| T814 |
/workspace/coverage/default/1.sram_ctrl_mem_walk.764010269 |
|
|
Jul 06 04:42:02 PM PDT 24 |
Jul 06 04:46:58 PM PDT 24 |
5475021991 ps |
| T815 |
/workspace/coverage/default/9.sram_ctrl_mem_walk.1119772177 |
|
|
Jul 06 04:42:40 PM PDT 24 |
Jul 06 04:48:46 PM PDT 24 |
69207499785 ps |
| T816 |
/workspace/coverage/default/27.sram_ctrl_mem_partial_access.2416653402 |
|
|
Jul 06 04:42:58 PM PDT 24 |
Jul 06 04:45:36 PM PDT 24 |
10254904449 ps |
| T817 |
/workspace/coverage/default/42.sram_ctrl_ram_cfg.1620045190 |
|
|
Jul 06 04:44:09 PM PDT 24 |
Jul 06 04:44:12 PM PDT 24 |
352024226 ps |
| T818 |
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.493818025 |
|
|
Jul 06 04:44:09 PM PDT 24 |
Jul 06 04:49:50 PM PDT 24 |
30086161033 ps |
| T819 |
/workspace/coverage/default/43.sram_ctrl_access_during_key_req.3152408698 |
|
|
Jul 06 04:44:15 PM PDT 24 |
Jul 06 04:52:26 PM PDT 24 |
11800392271 ps |
| T820 |
/workspace/coverage/default/26.sram_ctrl_partial_access.365035998 |
|
|
Jul 06 04:43:00 PM PDT 24 |
Jul 06 04:45:01 PM PDT 24 |
1281211314 ps |
| T821 |
/workspace/coverage/default/21.sram_ctrl_max_throughput.1571482928 |
|
|
Jul 06 04:42:45 PM PDT 24 |
Jul 06 04:42:53 PM PDT 24 |
686935617 ps |
| T822 |
/workspace/coverage/default/26.sram_ctrl_mem_walk.1768148124 |
|
|
Jul 06 04:43:05 PM PDT 24 |
Jul 06 04:48:12 PM PDT 24 |
5418980176 ps |
| T823 |
/workspace/coverage/default/47.sram_ctrl_max_throughput.3382925492 |
|
|
Jul 06 04:44:37 PM PDT 24 |
Jul 06 04:46:48 PM PDT 24 |
773534250 ps |
| T824 |
/workspace/coverage/default/30.sram_ctrl_access_during_key_req.1672124468 |
|
|
Jul 06 04:43:09 PM PDT 24 |
Jul 06 04:54:10 PM PDT 24 |
35529992071 ps |
| T825 |
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.2067419582 |
|
|
Jul 06 04:42:26 PM PDT 24 |
Jul 06 05:09:45 PM PDT 24 |
60949674896 ps |
| T826 |
/workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.1111041698 |
|
|
Jul 06 04:42:35 PM PDT 24 |
Jul 06 04:42:44 PM PDT 24 |
238557886 ps |
| T827 |
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.2353567322 |
|
|
Jul 06 04:44:26 PM PDT 24 |
Jul 06 04:45:14 PM PDT 24 |
3075829509 ps |
| T828 |
/workspace/coverage/default/24.sram_ctrl_partial_access.611241409 |
|
|
Jul 06 04:42:59 PM PDT 24 |
Jul 06 04:43:28 PM PDT 24 |
1814368802 ps |
| T829 |
/workspace/coverage/default/41.sram_ctrl_partial_access_b2b.1841841436 |
|
|
Jul 06 04:43:57 PM PDT 24 |
Jul 06 04:49:15 PM PDT 24 |
30443634583 ps |
| T830 |
/workspace/coverage/default/6.sram_ctrl_ram_cfg.9130432 |
|
|
Jul 06 04:42:05 PM PDT 24 |
Jul 06 04:42:09 PM PDT 24 |
757297742 ps |
| T831 |
/workspace/coverage/default/10.sram_ctrl_ram_cfg.1927022773 |
|
|
Jul 06 04:42:12 PM PDT 24 |
Jul 06 04:42:16 PM PDT 24 |
1411348499 ps |
| T832 |
/workspace/coverage/default/1.sram_ctrl_executable.2981353891 |
|
|
Jul 06 04:42:02 PM PDT 24 |
Jul 06 05:06:20 PM PDT 24 |
73701973101 ps |
| T833 |
/workspace/coverage/default/47.sram_ctrl_alert_test.1527615212 |
|
|
Jul 06 04:44:37 PM PDT 24 |
Jul 06 04:44:38 PM PDT 24 |
24138352 ps |
| T834 |
/workspace/coverage/default/9.sram_ctrl_max_throughput.79768758 |
|
|
Jul 06 04:42:37 PM PDT 24 |
Jul 06 04:42:50 PM PDT 24 |
2150896085 ps |
| T835 |
/workspace/coverage/default/23.sram_ctrl_partial_access.4242892477 |
|
|
Jul 06 04:42:53 PM PDT 24 |
Jul 06 04:43:10 PM PDT 24 |
1236704848 ps |
| T836 |
/workspace/coverage/default/29.sram_ctrl_mem_partial_access.1368422912 |
|
|
Jul 06 04:43:14 PM PDT 24 |
Jul 06 04:45:58 PM PDT 24 |
24270367195 ps |
| T837 |
/workspace/coverage/default/14.sram_ctrl_ram_cfg.1085216803 |
|
|
Jul 06 04:42:47 PM PDT 24 |
Jul 06 04:42:50 PM PDT 24 |
794835860 ps |
| T838 |
/workspace/coverage/default/10.sram_ctrl_stress_all.2228863596 |
|
|
Jul 06 04:42:30 PM PDT 24 |
Jul 06 06:02:00 PM PDT 24 |
69073387752 ps |
| T839 |
/workspace/coverage/default/2.sram_ctrl_mem_partial_access.550600395 |
|
|
Jul 06 04:42:07 PM PDT 24 |
Jul 06 04:43:13 PM PDT 24 |
4008905970 ps |
| T840 |
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.3890577771 |
|
|
Jul 06 04:43:26 PM PDT 24 |
Jul 06 04:45:56 PM PDT 24 |
3561131345 ps |
| T841 |
/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.4234591970 |
|
|
Jul 06 04:43:24 PM PDT 24 |
Jul 06 04:48:37 PM PDT 24 |
101742869636 ps |
| T842 |
/workspace/coverage/default/4.sram_ctrl_bijection.2197745424 |
|
|
Jul 06 04:42:01 PM PDT 24 |
Jul 06 05:08:02 PM PDT 24 |
359333770740 ps |
| T843 |
/workspace/coverage/default/4.sram_ctrl_stress_pipeline.924511369 |
|
|
Jul 06 04:41:56 PM PDT 24 |
Jul 06 04:47:51 PM PDT 24 |
19494643213 ps |
| T844 |
/workspace/coverage/default/4.sram_ctrl_mem_walk.139248577 |
|
|
Jul 06 04:42:19 PM PDT 24 |
Jul 06 04:45:30 PM PDT 24 |
31406178225 ps |
| T845 |
/workspace/coverage/default/12.sram_ctrl_partial_access.3902099285 |
|
|
Jul 06 04:42:26 PM PDT 24 |
Jul 06 04:42:37 PM PDT 24 |
2797203348 ps |
| T846 |
/workspace/coverage/default/29.sram_ctrl_partial_access.4200946939 |
|
|
Jul 06 04:43:05 PM PDT 24 |
Jul 06 04:43:45 PM PDT 24 |
800885115 ps |
| T847 |
/workspace/coverage/default/13.sram_ctrl_mem_partial_access.1525865384 |
|
|
Jul 06 04:42:37 PM PDT 24 |
Jul 06 04:44:01 PM PDT 24 |
2765951053 ps |
| T848 |
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.2425789200 |
|
|
Jul 06 04:44:32 PM PDT 24 |
Jul 06 04:47:10 PM PDT 24 |
2081062672 ps |
| T849 |
/workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.633009121 |
|
|
Jul 06 04:43:06 PM PDT 24 |
Jul 06 04:43:48 PM PDT 24 |
1052819781 ps |
| T850 |
/workspace/coverage/default/44.sram_ctrl_max_throughput.1946192977 |
|
|
Jul 06 04:44:20 PM PDT 24 |
Jul 06 04:46:12 PM PDT 24 |
761863036 ps |
| T851 |
/workspace/coverage/default/41.sram_ctrl_alert_test.2206356852 |
|
|
Jul 06 04:44:04 PM PDT 24 |
Jul 06 04:44:05 PM PDT 24 |
19536392 ps |
| T852 |
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.631781507 |
|
|
Jul 06 04:42:32 PM PDT 24 |
Jul 06 04:44:35 PM PDT 24 |
821566781 ps |
| T853 |
/workspace/coverage/default/22.sram_ctrl_alert_test.3226480348 |
|
|
Jul 06 04:42:58 PM PDT 24 |
Jul 06 04:43:00 PM PDT 24 |
14690392 ps |
| T854 |
/workspace/coverage/default/22.sram_ctrl_lc_escalation.2972958395 |
|
|
Jul 06 04:42:57 PM PDT 24 |
Jul 06 04:43:49 PM PDT 24 |
24200044536 ps |
| T855 |
/workspace/coverage/default/29.sram_ctrl_multiple_keys.544852683 |
|
|
Jul 06 04:43:09 PM PDT 24 |
Jul 06 05:11:45 PM PDT 24 |
39905809477 ps |
| T856 |
/workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.3454210118 |
|
|
Jul 06 04:42:58 PM PDT 24 |
Jul 06 04:43:58 PM PDT 24 |
9357855963 ps |
| T857 |
/workspace/coverage/default/33.sram_ctrl_access_during_key_req.840984159 |
|
|
Jul 06 04:43:25 PM PDT 24 |
Jul 06 04:56:50 PM PDT 24 |
50572603754 ps |
| T858 |
/workspace/coverage/default/46.sram_ctrl_partial_access.2705952980 |
|
|
Jul 06 04:44:35 PM PDT 24 |
Jul 06 04:45:16 PM PDT 24 |
6007484061 ps |
| T859 |
/workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.166540280 |
|
|
Jul 06 04:42:54 PM PDT 24 |
Jul 06 04:45:33 PM PDT 24 |
9741805583 ps |
| T860 |
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.2804976064 |
|
|
Jul 06 04:44:37 PM PDT 24 |
Jul 06 04:46:04 PM PDT 24 |
16402141928 ps |
| T861 |
/workspace/coverage/default/22.sram_ctrl_regwen.2577400177 |
|
|
Jul 06 04:42:57 PM PDT 24 |
Jul 06 04:45:37 PM PDT 24 |
4222141806 ps |
| T862 |
/workspace/coverage/default/6.sram_ctrl_stress_all.4156273249 |
|
|
Jul 06 04:42:17 PM PDT 24 |
Jul 06 06:01:47 PM PDT 24 |
305433219523 ps |
| T863 |
/workspace/coverage/default/4.sram_ctrl_max_throughput.872475664 |
|
|
Jul 06 04:42:06 PM PDT 24 |
Jul 06 04:42:13 PM PDT 24 |
3329700613 ps |
| T864 |
/workspace/coverage/default/23.sram_ctrl_mem_partial_access.3160197949 |
|
|
Jul 06 04:42:59 PM PDT 24 |
Jul 06 04:45:36 PM PDT 24 |
12788598510 ps |
| T865 |
/workspace/coverage/default/44.sram_ctrl_bijection.757682712 |
|
|
Jul 06 04:44:15 PM PDT 24 |
Jul 06 05:19:30 PM PDT 24 |
116695797727 ps |
| T866 |
/workspace/coverage/default/20.sram_ctrl_executable.3695496772 |
|
|
Jul 06 04:42:46 PM PDT 24 |
Jul 06 04:43:59 PM PDT 24 |
3037304471 ps |
| T867 |
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.499151397 |
|
|
Jul 06 04:44:40 PM PDT 24 |
Jul 06 04:45:04 PM PDT 24 |
3010011624 ps |
| T868 |
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.1130970770 |
|
|
Jul 06 04:44:48 PM PDT 24 |
Jul 06 04:50:22 PM PDT 24 |
22576377191 ps |
| T869 |
/workspace/coverage/default/5.sram_ctrl_smoke.983952359 |
|
|
Jul 06 04:42:23 PM PDT 24 |
Jul 06 04:42:39 PM PDT 24 |
850680446 ps |
| T870 |
/workspace/coverage/default/24.sram_ctrl_lc_escalation.3590274765 |
|
|
Jul 06 04:42:53 PM PDT 24 |
Jul 06 04:43:05 PM PDT 24 |
6042434176 ps |
| T871 |
/workspace/coverage/default/5.sram_ctrl_partial_access.1918549949 |
|
|
Jul 06 04:42:09 PM PDT 24 |
Jul 06 04:42:31 PM PDT 24 |
1880776633 ps |
| T872 |
/workspace/coverage/default/42.sram_ctrl_executable.80783986 |
|
|
Jul 06 04:44:11 PM PDT 24 |
Jul 06 05:11:57 PM PDT 24 |
137462607693 ps |
| T873 |
/workspace/coverage/default/22.sram_ctrl_ram_cfg.3793828017 |
|
|
Jul 06 04:43:02 PM PDT 24 |
Jul 06 04:43:06 PM PDT 24 |
360695747 ps |
| T874 |
/workspace/coverage/default/9.sram_ctrl_ram_cfg.2795330421 |
|
|
Jul 06 04:42:13 PM PDT 24 |
Jul 06 04:42:17 PM PDT 24 |
351647002 ps |
| T875 |
/workspace/coverage/default/32.sram_ctrl_mem_walk.3885663604 |
|
|
Jul 06 04:43:23 PM PDT 24 |
Jul 06 04:46:05 PM PDT 24 |
12127559732 ps |
| T876 |
/workspace/coverage/default/1.sram_ctrl_alert_test.996250648 |
|
|
Jul 06 04:42:05 PM PDT 24 |
Jul 06 04:42:06 PM PDT 24 |
20106866 ps |
| T877 |
/workspace/coverage/default/0.sram_ctrl_alert_test.207158235 |
|
|
Jul 06 04:41:52 PM PDT 24 |
Jul 06 04:41:53 PM PDT 24 |
18874121 ps |
| T878 |
/workspace/coverage/default/35.sram_ctrl_partial_access_b2b.2000646117 |
|
|
Jul 06 04:43:38 PM PDT 24 |
Jul 06 04:52:15 PM PDT 24 |
19611301103 ps |
| T879 |
/workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.4187630266 |
|
|
Jul 06 04:43:41 PM PDT 24 |
Jul 06 04:44:23 PM PDT 24 |
5895291021 ps |
| T880 |
/workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.2942576786 |
|
|
Jul 06 04:43:58 PM PDT 24 |
Jul 06 04:45:07 PM PDT 24 |
1162881644 ps |
| T881 |
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.797862563 |
|
|
Jul 06 04:44:37 PM PDT 24 |
Jul 06 05:04:10 PM PDT 24 |
20268311105 ps |
| T882 |
/workspace/coverage/default/19.sram_ctrl_access_during_key_req.3375938905 |
|
|
Jul 06 04:42:48 PM PDT 24 |
Jul 06 04:51:08 PM PDT 24 |
10739358599 ps |
| T883 |
/workspace/coverage/default/29.sram_ctrl_partial_access_b2b.3323077081 |
|
|
Jul 06 04:43:05 PM PDT 24 |
Jul 06 04:51:26 PM PDT 24 |
7636494779 ps |
| T884 |
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.3841181869 |
|
|
Jul 06 04:44:27 PM PDT 24 |
Jul 06 04:46:43 PM PDT 24 |
1668260244 ps |
| T885 |
/workspace/coverage/default/15.sram_ctrl_alert_test.3831168873 |
|
|
Jul 06 04:42:36 PM PDT 24 |
Jul 06 04:42:37 PM PDT 24 |
14340477 ps |
| T886 |
/workspace/coverage/default/11.sram_ctrl_lc_escalation.1689322906 |
|
|
Jul 06 04:42:39 PM PDT 24 |
Jul 06 04:43:40 PM PDT 24 |
10449129225 ps |
| T887 |
/workspace/coverage/default/12.sram_ctrl_smoke.1938460463 |
|
|
Jul 06 04:42:16 PM PDT 24 |
Jul 06 04:42:37 PM PDT 24 |
1304299321 ps |
| T888 |
/workspace/coverage/default/1.sram_ctrl_regwen.3551234221 |
|
|
Jul 06 04:41:50 PM PDT 24 |
Jul 06 04:50:23 PM PDT 24 |
5536512548 ps |
| T889 |
/workspace/coverage/default/17.sram_ctrl_multiple_keys.3207794158 |
|
|
Jul 06 04:42:33 PM PDT 24 |
Jul 06 04:55:39 PM PDT 24 |
16468691033 ps |
| T890 |
/workspace/coverage/default/44.sram_ctrl_lc_escalation.793561188 |
|
|
Jul 06 04:44:21 PM PDT 24 |
Jul 06 04:44:25 PM PDT 24 |
1506439008 ps |
| T891 |
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.3460276320 |
|
|
Jul 06 04:42:02 PM PDT 24 |
Jul 06 04:47:28 PM PDT 24 |
21094084924 ps |
| T892 |
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.3997069631 |
|
|
Jul 06 04:42:20 PM PDT 24 |
Jul 06 04:42:49 PM PDT 24 |
754040111 ps |
| T893 |
/workspace/coverage/default/13.sram_ctrl_partial_access.3754388717 |
|
|
Jul 06 04:42:42 PM PDT 24 |
Jul 06 04:42:53 PM PDT 24 |
533584808 ps |
| T894 |
/workspace/coverage/default/31.sram_ctrl_executable.65626566 |
|
|
Jul 06 04:43:15 PM PDT 24 |
Jul 06 05:01:12 PM PDT 24 |
18664455670 ps |
| T895 |
/workspace/coverage/default/27.sram_ctrl_smoke.2850305718 |
|
|
Jul 06 04:43:02 PM PDT 24 |
Jul 06 04:43:13 PM PDT 24 |
997940572 ps |
| T896 |
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3211776936 |
|
|
Jul 06 04:42:34 PM PDT 24 |
Jul 06 04:42:52 PM PDT 24 |
2966812526 ps |
| T897 |
/workspace/coverage/default/15.sram_ctrl_executable.3316344250 |
|
|
Jul 06 04:42:39 PM PDT 24 |
Jul 06 05:10:48 PM PDT 24 |
128616603792 ps |
| T898 |
/workspace/coverage/default/37.sram_ctrl_ram_cfg.3795534660 |
|
|
Jul 06 04:43:42 PM PDT 24 |
Jul 06 04:43:46 PM PDT 24 |
655739993 ps |
| T899 |
/workspace/coverage/default/40.sram_ctrl_access_during_key_req.4179535914 |
|
|
Jul 06 04:43:51 PM PDT 24 |
Jul 06 04:55:56 PM PDT 24 |
6433574534 ps |
| T900 |
/workspace/coverage/default/29.sram_ctrl_mem_walk.3346901843 |
|
|
Jul 06 04:43:11 PM PDT 24 |
Jul 06 04:46:09 PM PDT 24 |
11392135964 ps |
| T901 |
/workspace/coverage/default/31.sram_ctrl_bijection.2077726442 |
|
|
Jul 06 04:43:11 PM PDT 24 |
Jul 06 05:07:06 PM PDT 24 |
249960731813 ps |
| T902 |
/workspace/coverage/default/20.sram_ctrl_mem_partial_access.2567106806 |
|
|
Jul 06 04:42:45 PM PDT 24 |
Jul 06 04:46:03 PM PDT 24 |
54427067899 ps |
| T903 |
/workspace/coverage/default/20.sram_ctrl_stress_pipeline.1127265425 |
|
|
Jul 06 04:42:53 PM PDT 24 |
Jul 06 04:48:15 PM PDT 24 |
9361772422 ps |
| T904 |
/workspace/coverage/default/4.sram_ctrl_regwen.3919745749 |
|
|
Jul 06 04:42:06 PM PDT 24 |
Jul 06 04:56:29 PM PDT 24 |
192460337705 ps |
| T905 |
/workspace/coverage/default/10.sram_ctrl_partial_access.2120810643 |
|
|
Jul 06 04:42:34 PM PDT 24 |
Jul 06 04:42:46 PM PDT 24 |
1583232648 ps |
| T906 |
/workspace/coverage/default/43.sram_ctrl_stress_all.1421808981 |
|
|
Jul 06 04:44:14 PM PDT 24 |
Jul 06 06:21:58 PM PDT 24 |
805902376858 ps |
| T907 |
/workspace/coverage/default/26.sram_ctrl_max_throughput.3287699686 |
|
|
Jul 06 04:42:58 PM PDT 24 |
Jul 06 04:43:25 PM PDT 24 |
2955866511 ps |
| T908 |
/workspace/coverage/default/2.sram_ctrl_stress_pipeline.1919296311 |
|
|
Jul 06 04:41:59 PM PDT 24 |
Jul 06 04:46:35 PM PDT 24 |
4101137419 ps |
| T909 |
/workspace/coverage/default/10.sram_ctrl_regwen.141052963 |
|
|
Jul 06 04:42:35 PM PDT 24 |
Jul 06 04:48:08 PM PDT 24 |
7884091555 ps |
| T910 |
/workspace/coverage/default/12.sram_ctrl_regwen.3869852197 |
|
|
Jul 06 04:42:23 PM PDT 24 |
Jul 06 04:59:12 PM PDT 24 |
7190574565 ps |
| T911 |
/workspace/coverage/default/0.sram_ctrl_max_throughput.4136170545 |
|
|
Jul 06 04:42:01 PM PDT 24 |
Jul 06 04:42:27 PM PDT 24 |
1126673400 ps |
| T912 |
/workspace/coverage/default/3.sram_ctrl_multiple_keys.2472430172 |
|
|
Jul 06 04:42:00 PM PDT 24 |
Jul 06 04:56:07 PM PDT 24 |
4876156689 ps |
| T913 |
/workspace/coverage/default/18.sram_ctrl_bijection.3598549390 |
|
|
Jul 06 04:42:43 PM PDT 24 |
Jul 06 05:11:43 PM PDT 24 |
215703849809 ps |
| T914 |
/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.70781481 |
|
|
Jul 06 04:42:50 PM PDT 24 |
Jul 06 04:43:04 PM PDT 24 |
596028520 ps |
| T915 |
/workspace/coverage/default/43.sram_ctrl_smoke.2189217028 |
|
|
Jul 06 04:44:09 PM PDT 24 |
Jul 06 04:44:29 PM PDT 24 |
1263744424 ps |
| T916 |
/workspace/coverage/default/14.sram_ctrl_mem_walk.2666567659 |
|
|
Jul 06 04:42:45 PM PDT 24 |
Jul 06 04:48:15 PM PDT 24 |
14286081199 ps |
| T917 |
/workspace/coverage/default/11.sram_ctrl_regwen.3532571230 |
|
|
Jul 06 04:42:16 PM PDT 24 |
Jul 06 04:55:51 PM PDT 24 |
4786605312 ps |
| T918 |
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.4039828233 |
|
|
Jul 06 04:44:20 PM PDT 24 |
Jul 06 04:50:39 PM PDT 24 |
24643727675 ps |
| T919 |
/workspace/coverage/default/45.sram_ctrl_multiple_keys.1178243549 |
|
|
Jul 06 04:44:26 PM PDT 24 |
Jul 06 05:00:47 PM PDT 24 |
31574291711 ps |
| T920 |
/workspace/coverage/default/22.sram_ctrl_smoke.734476714 |
|
|
Jul 06 04:42:56 PM PDT 24 |
Jul 06 04:43:11 PM PDT 24 |
2098490634 ps |
| T921 |
/workspace/coverage/default/23.sram_ctrl_ram_cfg.2241739370 |
|
|
Jul 06 04:43:00 PM PDT 24 |
Jul 06 04:43:04 PM PDT 24 |
343302965 ps |
| T922 |
/workspace/coverage/default/49.sram_ctrl_bijection.1021137068 |
|
|
Jul 06 04:44:52 PM PDT 24 |
Jul 06 05:09:46 PM PDT 24 |
117645548760 ps |
| T923 |
/workspace/coverage/default/41.sram_ctrl_partial_access.1183594028 |
|
|
Jul 06 04:43:57 PM PDT 24 |
Jul 06 04:44:14 PM PDT 24 |
10309873282 ps |
| T924 |
/workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.2036640242 |
|
|
Jul 06 04:43:01 PM PDT 24 |
Jul 06 04:43:15 PM PDT 24 |
735959574 ps |
| T925 |
/workspace/coverage/default/24.sram_ctrl_max_throughput.394976366 |
|
|
Jul 06 04:42:57 PM PDT 24 |
Jul 06 04:43:11 PM PDT 24 |
2870742321 ps |
| T926 |
/workspace/coverage/default/6.sram_ctrl_mem_walk.3468276449 |
|
|
Jul 06 04:42:00 PM PDT 24 |
Jul 06 04:47:55 PM PDT 24 |
18886229041 ps |
| T927 |
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.2436796084 |
|
|
Jul 06 04:42:28 PM PDT 24 |
Jul 06 04:42:45 PM PDT 24 |
461085306 ps |
| T928 |
/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.3423656915 |
|
|
Jul 06 04:43:37 PM PDT 24 |
Jul 06 04:47:11 PM PDT 24 |
4507771185 ps |
| T929 |
/workspace/coverage/default/3.sram_ctrl_bijection.1146219024 |
|
|
Jul 06 04:42:06 PM PDT 24 |
Jul 06 05:24:25 PM PDT 24 |
110464457492 ps |
| T930 |
/workspace/coverage/default/14.sram_ctrl_access_during_key_req.2020294719 |
|
|
Jul 06 04:42:42 PM PDT 24 |
Jul 06 04:48:25 PM PDT 24 |
9408571713 ps |
| T931 |
/workspace/coverage/default/31.sram_ctrl_access_during_key_req.3829838222 |
|
|
Jul 06 04:43:12 PM PDT 24 |
Jul 06 04:44:33 PM PDT 24 |
3111826697 ps |
| T932 |
/workspace/coverage/default/16.sram_ctrl_smoke.1641792042 |
|
|
Jul 06 04:42:43 PM PDT 24 |
Jul 06 04:43:02 PM PDT 24 |
1998394434 ps |
| T933 |
/workspace/coverage/default/36.sram_ctrl_multiple_keys.3470678742 |
|
|
Jul 06 04:43:37 PM PDT 24 |
Jul 06 05:01:15 PM PDT 24 |
18658127203 ps |
| T934 |
/workspace/coverage/default/34.sram_ctrl_stress_all.2392828321 |
|
|
Jul 06 04:43:31 PM PDT 24 |
Jul 06 06:16:46 PM PDT 24 |
905427361012 ps |
| T935 |
/workspace/coverage/default/11.sram_ctrl_smoke.995529434 |
|
|
Jul 06 04:42:26 PM PDT 24 |
Jul 06 04:42:33 PM PDT 24 |
1344581541 ps |
| T936 |
/workspace/coverage/default/25.sram_ctrl_mem_partial_access.3928236799 |
|
|
Jul 06 04:42:52 PM PDT 24 |
Jul 06 04:45:26 PM PDT 24 |
39793717080 ps |
| T937 |
/workspace/coverage/default/28.sram_ctrl_stress_pipeline.3971830197 |
|
|
Jul 06 04:43:04 PM PDT 24 |
Jul 06 04:47:24 PM PDT 24 |
20230620956 ps |
| T938 |
/workspace/coverage/default/31.sram_ctrl_partial_access.1406384928 |
|
|
Jul 06 04:43:12 PM PDT 24 |
Jul 06 04:43:32 PM PDT 24 |
2581000136 ps |
| T939 |
/workspace/coverage/default/18.sram_ctrl_max_throughput.2981881381 |
|
|
Jul 06 04:42:47 PM PDT 24 |
Jul 06 04:42:55 PM PDT 24 |
679820826 ps |
| T940 |
/workspace/coverage/default/36.sram_ctrl_ram_cfg.3810597755 |
|
|
Jul 06 04:43:41 PM PDT 24 |
Jul 06 04:43:45 PM PDT 24 |
1403739043 ps |
| T941 |
/workspace/coverage/default/38.sram_ctrl_mem_partial_access.3551930788 |
|
|
Jul 06 04:43:49 PM PDT 24 |
Jul 06 04:46:16 PM PDT 24 |
9770779594 ps |
| T942 |
/workspace/coverage/default/25.sram_ctrl_ram_cfg.4265711901 |
|
|
Jul 06 04:43:00 PM PDT 24 |
Jul 06 04:43:04 PM PDT 24 |
345102601 ps |
| T943 |
/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.3055830326 |
|
|
Jul 06 04:42:51 PM PDT 24 |
Jul 06 04:45:02 PM PDT 24 |
3367246316 ps |
| T944 |
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3691091648 |
|
|
Jul 06 04:44:26 PM PDT 24 |
Jul 06 04:48:12 PM PDT 24 |
1697531142 ps |
| T72 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.301288577 |
|
|
Jul 06 04:20:16 PM PDT 24 |
Jul 06 04:20:17 PM PDT 24 |
59574304 ps |
| T73 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2222075758 |
|
|
Jul 06 04:21:46 PM PDT 24 |
Jul 06 04:21:47 PM PDT 24 |
40283441 ps |
| T74 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.60516163 |
|
|
Jul 06 04:23:43 PM PDT 24 |
Jul 06 04:23:45 PM PDT 24 |
20069659 ps |
| T90 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3979065353 |
|
|
Jul 06 04:18:22 PM PDT 24 |
Jul 06 04:18:23 PM PDT 24 |
52498832 ps |
| T91 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3627212673 |
|
|
Jul 06 04:18:35 PM PDT 24 |
Jul 06 04:19:31 PM PDT 24 |
7351656069 ps |
| T945 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1548357669 |
|
|
Jul 06 04:23:00 PM PDT 24 |
Jul 06 04:23:02 PM PDT 24 |
26974215 ps |
| T124 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.302490713 |
|
|
Jul 06 04:18:37 PM PDT 24 |
Jul 06 04:18:40 PM PDT 24 |
16496406 ps |
| T69 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3581438524 |
|
|
Jul 06 04:24:01 PM PDT 24 |
Jul 06 04:24:03 PM PDT 24 |
353253144 ps |
| T946 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2929142557 |
|
|
Jul 06 04:19:28 PM PDT 24 |
Jul 06 04:19:33 PM PDT 24 |
649300256 ps |
| T947 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2866371188 |
|
|
Jul 06 04:23:15 PM PDT 24 |
Jul 06 04:23:20 PM PDT 24 |
442943423 ps |
| T125 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3615758242 |
|
|
Jul 06 04:20:16 PM PDT 24 |
Jul 06 04:20:49 PM PDT 24 |
15419517338 ps |
| T92 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2955390903 |
|
|
Jul 06 04:18:36 PM PDT 24 |
Jul 06 04:18:38 PM PDT 24 |
24031543 ps |
| T132 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3715478798 |
|
|
Jul 06 04:18:37 PM PDT 24 |
Jul 06 04:18:40 PM PDT 24 |
29364572 ps |
| T948 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.234684087 |
|
|
Jul 06 04:23:21 PM PDT 24 |
Jul 06 04:23:27 PM PDT 24 |
158286228 ps |
| T93 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.198848066 |
|
|
Jul 06 04:20:41 PM PDT 24 |
Jul 06 04:20:42 PM PDT 24 |
17582466 ps |
| T949 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.343333777 |
|
|
Jul 06 04:18:37 PM PDT 24 |
Jul 06 04:18:40 PM PDT 24 |
505162759 ps |
| T94 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.4207428644 |
|
|
Jul 06 04:18:36 PM PDT 24 |
Jul 06 04:18:38 PM PDT 24 |
26025618 ps |
| T126 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3846674716 |
|
|
Jul 06 04:23:15 PM PDT 24 |
Jul 06 04:23:16 PM PDT 24 |
15036956 ps |
| T127 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2373663465 |
|
|
Jul 06 04:19:52 PM PDT 24 |
Jul 06 04:19:53 PM PDT 24 |
38286143 ps |
| T950 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1892718253 |
|
|
Jul 06 04:19:22 PM PDT 24 |
Jul 06 04:19:28 PM PDT 24 |
4394414366 ps |
| T95 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3729950478 |
|
|
Jul 06 04:18:21 PM PDT 24 |
Jul 06 04:18:22 PM PDT 24 |
39633657 ps |
| T70 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2754668566 |
|
|
Jul 06 04:20:52 PM PDT 24 |
Jul 06 04:20:54 PM PDT 24 |
125628813 ps |
| T71 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2818342502 |
|
|
Jul 06 04:18:38 PM PDT 24 |
Jul 06 04:18:42 PM PDT 24 |
258963168 ps |
| T951 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.875884483 |
|
|
Jul 06 04:23:15 PM PDT 24 |
Jul 06 04:23:18 PM PDT 24 |
58928079 ps |
| T952 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3446416280 |
|
|
Jul 06 04:24:01 PM PDT 24 |
Jul 06 04:24:54 PM PDT 24 |
7354927678 ps |
| T96 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1764383437 |
|
|
Jul 06 04:18:36 PM PDT 24 |
Jul 06 04:19:32 PM PDT 24 |
7096205834 ps |
| T97 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2491390365 |
|
|
Jul 06 04:20:52 PM PDT 24 |
Jul 06 04:20:53 PM PDT 24 |
41327845 ps |
| T953 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3163251123 |
|
|
Jul 06 04:18:37 PM PDT 24 |
Jul 06 04:18:41 PM PDT 24 |
34246611 ps |
| T954 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2881105142 |
|
|
Jul 06 04:18:37 PM PDT 24 |
Jul 06 04:18:40 PM PDT 24 |
21115499 ps |
| T105 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1780143521 |
|
|
Jul 06 04:20:29 PM PDT 24 |
Jul 06 04:21:18 PM PDT 24 |
7375093900 ps |
| T151 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.4070747912 |
|
|
Jul 06 04:18:26 PM PDT 24 |
Jul 06 04:18:29 PM PDT 24 |
490604546 ps |
| T955 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.234969784 |
|
|
Jul 06 04:23:29 PM PDT 24 |
Jul 06 04:23:33 PM PDT 24 |
500344927 ps |
| T106 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3470936323 |
|
|
Jul 06 04:24:00 PM PDT 24 |
Jul 06 04:24:52 PM PDT 24 |
7079742028 ps |
| T956 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3762504866 |
|
|
Jul 06 04:19:23 PM PDT 24 |
Jul 06 04:19:27 PM PDT 24 |
703440855 ps |
| T957 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1809909280 |
|
|
Jul 06 04:18:23 PM PDT 24 |
Jul 06 04:18:25 PM PDT 24 |
67970901 ps |
| T147 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1640754975 |
|
|
Jul 06 04:23:44 PM PDT 24 |
Jul 06 04:23:48 PM PDT 24 |
1032264025 ps |
| T958 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1901150419 |
|
|
Jul 06 04:18:37 PM PDT 24 |
Jul 06 04:18:42 PM PDT 24 |
1501250777 ps |
| T959 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1436224929 |
|
|
Jul 06 04:20:57 PM PDT 24 |
Jul 06 04:20:58 PM PDT 24 |
15636776 ps |
| T107 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2974394209 |
|
|
Jul 06 04:23:21 PM PDT 24 |
Jul 06 04:23:49 PM PDT 24 |
6302329495 ps |
| T156 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2181585970 |
|
|
Jul 06 04:23:44 PM PDT 24 |
Jul 06 04:23:47 PM PDT 24 |
674206136 ps |
| T960 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.814150855 |
|
|
Jul 06 04:21:04 PM PDT 24 |
Jul 06 04:21:09 PM PDT 24 |
533341309 ps |
| T961 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.4185710707 |
|
|
Jul 06 04:23:44 PM PDT 24 |
Jul 06 04:23:49 PM PDT 24 |
352519360 ps |
| T108 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1678415683 |
|
|
Jul 06 04:18:36 PM PDT 24 |
Jul 06 04:19:10 PM PDT 24 |
15351677230 ps |
| T962 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3438217819 |
|
|
Jul 06 04:23:14 PM PDT 24 |
Jul 06 04:23:18 PM PDT 24 |
702277351 ps |
| T963 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.4047716266 |
|
|
Jul 06 04:18:36 PM PDT 24 |
Jul 06 04:18:39 PM PDT 24 |
40194450 ps |
| T109 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1166768891 |
|
|
Jul 06 04:18:26 PM PDT 24 |
Jul 06 04:18:27 PM PDT 24 |
131550477 ps |
| T964 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.510712651 |
|
|
Jul 06 04:23:37 PM PDT 24 |
Jul 06 04:23:41 PM PDT 24 |
354449183 ps |
| T965 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3120912904 |
|
|
Jul 06 04:23:28 PM PDT 24 |
Jul 06 04:23:29 PM PDT 24 |
47370638 ps |
| T966 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1019074568 |
|
|
Jul 06 04:20:27 PM PDT 24 |
Jul 06 04:20:28 PM PDT 24 |
11922144 ps |
| T967 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2568096695 |
|
|
Jul 06 04:23:07 PM PDT 24 |
Jul 06 04:23:08 PM PDT 24 |
21367054 ps |
| T968 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3426515549 |
|
|
Jul 06 04:18:35 PM PDT 24 |
Jul 06 04:18:40 PM PDT 24 |
33405970 ps |
| T154 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2825041442 |
|
|
Jul 06 04:23:27 PM PDT 24 |
Jul 06 04:23:29 PM PDT 24 |
187681935 ps |
| T969 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.370601218 |
|
|
Jul 06 04:18:36 PM PDT 24 |
Jul 06 04:18:42 PM PDT 24 |
218679579 ps |
| T970 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2880960532 |
|
|
Jul 06 04:18:36 PM PDT 24 |
Jul 06 04:18:41 PM PDT 24 |
363043074 ps |
| T971 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2644738615 |
|
|
Jul 06 04:21:27 PM PDT 24 |
Jul 06 04:21:57 PM PDT 24 |
16103821005 ps |
| T972 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.850110702 |
|
|
Jul 06 04:18:36 PM PDT 24 |
Jul 06 04:18:38 PM PDT 24 |
19288252 ps |
| T152 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1313576934 |
|
|
Jul 06 04:23:15 PM PDT 24 |
Jul 06 04:23:17 PM PDT 24 |
330926952 ps |
| T973 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3719456648 |
|
|
Jul 06 04:20:32 PM PDT 24 |
Jul 06 04:20:36 PM PDT 24 |
371107868 ps |
| T974 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1260572403 |
|
|
Jul 06 04:23:36 PM PDT 24 |
Jul 06 04:23:37 PM PDT 24 |
20264972 ps |
| T975 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2434949220 |
|
|
Jul 06 04:23:40 PM PDT 24 |
Jul 06 04:23:41 PM PDT 24 |
29510899 ps |
| T976 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.458671695 |
|
|
Jul 06 04:20:11 PM PDT 24 |
Jul 06 04:21:03 PM PDT 24 |
7236999229 ps |
| T977 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3102309629 |
|
|
Jul 06 04:23:43 PM PDT 24 |
Jul 06 04:23:47 PM PDT 24 |
508029752 ps |
| T978 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.592337163 |
|
|
Jul 06 04:23:42 PM PDT 24 |
Jul 06 04:23:45 PM PDT 24 |
77897743 ps |
| T979 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.263909359 |
|
|
Jul 06 04:23:13 PM PDT 24 |
Jul 06 04:23:17 PM PDT 24 |
138144235 ps |
| T980 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.4045018606 |
|
|
Jul 06 04:23:21 PM PDT 24 |
Jul 06 04:23:23 PM PDT 24 |
25982179 ps |
| T981 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.727900338 |
|
|
Jul 06 04:18:24 PM PDT 24 |
Jul 06 04:18:28 PM PDT 24 |
1382203105 ps |
| T982 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3623454588 |
|
|
Jul 06 04:23:44 PM PDT 24 |
Jul 06 04:23:46 PM PDT 24 |
29125886 ps |
| T983 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2347112356 |
|
|
Jul 06 04:23:07 PM PDT 24 |
Jul 06 04:23:11 PM PDT 24 |
351882150 ps |
| T110 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3869591189 |
|
|
Jul 06 04:18:22 PM PDT 24 |
Jul 06 04:18:25 PM PDT 24 |
183043221 ps |
| T984 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1223650182 |
|
|
Jul 06 04:18:35 PM PDT 24 |
Jul 06 04:18:38 PM PDT 24 |
726974883 ps |
| T985 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3438409501 |
|
|
Jul 06 04:22:57 PM PDT 24 |
Jul 06 04:23:00 PM PDT 24 |
75027205 ps |
| T155 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.627322956 |
|
|
Jul 06 04:21:20 PM PDT 24 |
Jul 06 04:21:23 PM PDT 24 |
592726357 ps |
| T986 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.403407864 |
|
|
Jul 06 04:23:44 PM PDT 24 |
Jul 06 04:23:49 PM PDT 24 |
346226171 ps |
| T987 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.4001630823 |
|
|
Jul 06 04:22:05 PM PDT 24 |
Jul 06 04:22:06 PM PDT 24 |
11345842 ps |
| T988 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2106026728 |
|
|
Jul 06 04:19:10 PM PDT 24 |
Jul 06 04:19:14 PM PDT 24 |
2903224041 ps |
| T111 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2288679288 |
|
|
Jul 06 04:20:27 PM PDT 24 |
Jul 06 04:21:25 PM PDT 24 |
117426774400 ps |
| T157 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3587029117 |
|
|
Jul 06 04:23:24 PM PDT 24 |
Jul 06 04:23:26 PM PDT 24 |
188887298 ps |
| T118 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3734679152 |
|
|
Jul 06 04:23:58 PM PDT 24 |
Jul 06 04:24:55 PM PDT 24 |
70572019741 ps |
| T989 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.225006492 |
|
|
Jul 06 04:20:34 PM PDT 24 |
Jul 06 04:20:39 PM PDT 24 |
482183438 ps |
| T990 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2908804324 |
|
|
Jul 06 04:19:23 PM PDT 24 |
Jul 06 04:19:24 PM PDT 24 |
27032357 ps |
| T991 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2497458541 |
|
|
Jul 06 04:24:00 PM PDT 24 |
Jul 06 04:24:53 PM PDT 24 |
14432930029 ps |
| T992 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3782300632 |
|
|
Jul 06 04:24:01 PM PDT 24 |
Jul 06 04:24:05 PM PDT 24 |
1412500296 ps |
| T119 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.657007498 |
|
|
Jul 06 04:18:37 PM PDT 24 |
Jul 06 04:18:40 PM PDT 24 |
71125119 ps |
| T993 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2337040908 |
|
|
Jul 06 04:18:35 PM PDT 24 |
Jul 06 04:18:39 PM PDT 24 |
1442671034 ps |
| T994 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3966642831 |
|
|
Jul 06 04:23:15 PM PDT 24 |
Jul 06 04:23:16 PM PDT 24 |
78441301 ps |
| T120 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3082411459 |
|
|
Jul 06 04:20:49 PM PDT 24 |
Jul 06 04:21:17 PM PDT 24 |
13166009841 ps |
| T995 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.436026556 |
|
|
Jul 06 04:23:18 PM PDT 24 |
Jul 06 04:23:20 PM PDT 24 |
29156844 ps |
| T996 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.4235472976 |
|
|
Jul 06 04:21:49 PM PDT 24 |
Jul 06 04:21:53 PM PDT 24 |
372578882 ps |
| T997 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1855329182 |
|
|
Jul 06 04:19:35 PM PDT 24 |
Jul 06 04:19:36 PM PDT 24 |
21475811 ps |
| T998 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3391964637 |
|
|
Jul 06 04:18:37 PM PDT 24 |
Jul 06 04:18:39 PM PDT 24 |
12807423 ps |
| T999 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1516562679 |
|
|
Jul 06 04:18:37 PM PDT 24 |
Jul 06 04:18:40 PM PDT 24 |
14371671 ps |
| T1000 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3805761615 |
|
|
Jul 06 04:20:09 PM PDT 24 |
Jul 06 04:20:13 PM PDT 24 |
701101422 ps |
| T158 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2938842335 |
|
|
Jul 06 04:23:15 PM PDT 24 |
Jul 06 04:23:18 PM PDT 24 |
562056305 ps |
| T1001 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2271163790 |
|
|
Jul 06 04:23:14 PM PDT 24 |
Jul 06 04:23:18 PM PDT 24 |
358732441 ps |
| T148 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.4082609474 |
|
|
Jul 06 04:23:09 PM PDT 24 |
Jul 06 04:23:12 PM PDT 24 |
321457387 ps |
| T1002 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1617214592 |
|
|
Jul 06 04:23:21 PM PDT 24 |
Jul 06 04:23:23 PM PDT 24 |
61432927 ps |
| T1003 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.351099815 |
|
|
Jul 06 04:23:43 PM PDT 24 |
Jul 06 04:23:48 PM PDT 24 |
3196539229 ps |
| T121 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1889025408 |
|
|
Jul 06 04:20:19 PM PDT 24 |
Jul 06 04:20:20 PM PDT 24 |
46545011 ps |
| T1004 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2233576963 |
|
|
Jul 06 04:23:15 PM PDT 24 |
Jul 06 04:23:18 PM PDT 24 |
153909831 ps |
| T1005 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2766737999 |
|
|
Jul 06 04:23:28 PM PDT 24 |
Jul 06 04:23:32 PM PDT 24 |
1217227309 ps |