Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	331118252	1			T1	127860		T2	383400		T3	69722
instr_valid_dis	295853226	1			T1	127860		T2	383400		T3	30586
instr_en	26976464	1			T3	39136		T6	141294		T24	268680

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	17610399	1			T6	36794		T24	109032		T39	31414
sram_ifetch_valid_disable	292933725	1			T1	127860		T2	383400		T3	30586
sram_ifetch_enable	20574128	1			T3	39136		T6	129028		T24	148418

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	331118252	1			T1	127860		T2	383400		T3	69722
hw_debug_en_valid_off	291940403	1			T1	127860		T2	383400		T3	69722
hw_debug_en_on	26128427	1			T6	36794		T24	166170		T39	154930

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	292933725	1			T1	127860		T2	383400		T3	30586
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	278133983	1			T1	127860		T2	383400		T3	30586
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	11843304	1			T6	17442		T24	103278		T43	67102
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	6119586	1			T24	44844		T39	4684		T43	15736
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	3446408	1			T24	44844		T39	4684		T43	15736
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1862066	1			T19	37474		T63	28570		T152	65012
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	7392281	1			T6	36794		T24	39002		T39	26730
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	5191503	1			T39	26730		T18	72744		T20	162780
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1577810	1			T6	36794		T24	24348		T43	76140
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	11067536	1			T24	95628		T39	53984		T18	2264
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3521562	1			T24	14962		T39	53984		T18	2264
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	6265270	1			T24	80666		T43	51216		T19	102164

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	8407712	1			T3	39136		T6	87058		T24	141054
lc_exec_en	7668610	1			T24	31540		T39	74216		T18	69098
valid_exec_dis	286094875	1			T1	127860		T2	383400		T3	30586
invalid_exec_dis	38184527	1			T3	39136		T6	165822		T24	257450