Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	137576686	1			T1	3115		T2	174305		T3	9531
triple_byte_access	2680893	1			T1	7245		T2	3455		T3	165
halfword_access	4112403	1			T1	13110		T2	5177		T3	289
byte_access	5754278	1			T1	25490		T2	6995		T3	385
zero_access	1751215	1			T1	14970		T2	1768		T3	93

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

75747254

1

T1

32132

T2

95841

T3

7006

auto[1]

76128221

1

T1

31798

T2

95859

T3

3457

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	68465973	1			T1	248		T2	87116		T3	6368
auto[0]	triple_byte_access	1276761	1			T1	1365		T2	1744		T3	124
auto[0]	halfword_access	2007619	1			T1	4580		T2	2571		T3	195
auto[0]	byte_access	2948540	1			T1	13845		T2	3497		T3	255
auto[0]	zero_access	1048361	1			T1	12094		T2	913		T3	64
auto[1]	word_access	69110713	1			T1	2867		T2	87189		T3	3163
auto[1]	triple_byte_access	1404132	1			T1	5880		T2	1711		T3	41
auto[1]	halfword_access	2104784	1			T1	8530		T2	2606		T3	94
auto[1]	byte_access	2805738	1			T1	11645		T2	3498		T3	130
auto[1]	zero_access	702854	1			T1	2876		T2	855		T3	29