Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg
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Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv



Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 16 0 16 100.00


Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
csr_exec_cp 3 0 3 100.00 100 1 1 0
en_sram_ifetch_cp 3 0 3 100.00 100 1 1 0
lc_hw_debug_en_cp 3 0 3 100.00 100 1 1 0


Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
executable_cross 16 0 16 100.00 100 1 1 0


Summary for Variable csr_exec_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for csr_exec_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
instr_invalid_dis 364114894 1 T1 16820 T2 240196 T3 13840
instr_valid_dis 316646645 1 T1 16820 T2 61580 T3 13840
instr_en 36615158 1 T2 144532 T12 136028 T6 246652



Summary for Variable en_sram_ifetch_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for en_sram_ifetch_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sram_ifetch_invalid_disable 12767108 1 T2 97342 T12 48164 T6 115874
sram_ifetch_valid_disable 317516634 1 T1 16820 T2 93088 T3 13840
sram_ifetch_enable 33831152 1 T2 49766 T12 357020 T6 99358



Summary for Variable lc_hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for lc_hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
hw_debug_en_invalid_off 364114894 1 T1 16820 T2 240196 T3 13840
hw_debug_en_valid_off 312375818 1 T1 16820 T2 99682 T3 13840
hw_debug_en_on 30465660 1 T2 59510 T12 258550 T6 143700



Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 16 0 16 100.00
Automatically Generated Cross Bins 12 0 12 100.00
User Defined Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for executable_cross

Bins
lc_hw_debug_en_cpen_sram_ifetch_cpcsr_exec_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
hw_debug_en_invalid_off sram_ifetch_valid_disable instr_invalid_dis 317516634 1 T1 16820 T2 93088 T3 13840
hw_debug_en_invalid_off sram_ifetch_valid_disable instr_valid_dis 299623691 1 T1 16820 T2 61580 T3 13840
hw_debug_en_invalid_off sram_ifetch_valid_disable instr_en 15111546 1 T2 13762 T12 60782 T6 46896
hw_debug_en_valid_off sram_ifetch_invalid_disable instr_invalid_dis 3990614 1 T2 20000 T12 1298 T6 38376
hw_debug_en_valid_off sram_ifetch_invalid_disable instr_valid_dis 1771572 1 T12 1298 T47 2422 T24 64830
hw_debug_en_valid_off sram_ifetch_invalid_disable instr_en 1609442 1 T2 20000 T6 38376 T43 50096
hw_debug_en_on sram_ifetch_invalid_disable instr_invalid_dis 6744090 1 T2 16338 T12 43240 T6 38450
hw_debug_en_on sram_ifetch_invalid_disable instr_valid_dis 1757842 1 T12 43240 T48 38622 T20 3234
hw_debug_en_on sram_ifetch_invalid_disable instr_en 1721628 1 T6 38450 T43 18990 T24 1812
hw_debug_en_on sram_ifetch_valid_disable instr_invalid_dis 10599080 1 T2 41644 T12 79868 T6 39652
hw_debug_en_on sram_ifetch_valid_disable instr_valid_dis 3343342 1 T2 41580 T12 38812 T24 14846
hw_debug_en_on sram_ifetch_valid_disable instr_en 6316360 1 T2 64 T12 12998 T6 39652


User Defined Cross Bins for executable_cross

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
csr_exec_en 17211896 1 T2 49766 T12 71620 T6 83882
lc_exec_en 13122490 1 T2 1528 T12 135442 T6 65598
valid_exec_dis 311096572 1 T1 16820 T2 31444 T3 13840
invalid_exec_dis 46598260 1 T2 147108 T12 405184 T6 215232

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