Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	152653179	1			T1	1578		T2	53482		T4	9129
triple_byte_access	2879362	1			T1	1427		T2	1054		T4	181
halfword_access	4417243	1			T1	2049		T2	1586		T4	264
byte_access	6172882	1			T1	2708		T2	2112		T4	371
zero_access	1874283	1			T1	648		T2	532		T4	83

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

83703618

1

T1

4181

T2

34690

T4

4981

auto[1]

84293331

1

T1

4229

T2

24076

T4

5047

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	75896036	1			T1	818		T2	31509		T4	4525
auto[0]	triple_byte_access	1370286	1			T1	733		T2	634		T4	102
auto[0]	halfword_access	2155025	1			T1	993		T2	942		T4	123
auto[0]	byte_access	3161825	1			T1	1318		T2	1286		T4	184
auto[0]	zero_access	1120446	1			T1	319		T2	319		T4	47
auto[1]	word_access	76757143	1			T1	760		T2	21973		T4	4604
auto[1]	triple_byte_access	1509076	1			T1	694		T2	420		T4	79
auto[1]	halfword_access	2262218	1			T1	1056		T2	644		T4	141
auto[1]	byte_access	3011057	1			T1	1390		T2	826		T4	187
auto[1]	zero_access	753837	1			T1	329		T2	213		T4	36