| T795 |
/workspace/coverage/default/38.sram_ctrl_bijection.4164828201 |
|
|
Jul 09 06:49:40 PM PDT 24 |
Jul 09 07:38:13 PM PDT 24 |
344856979792 ps |
| T796 |
/workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.743455110 |
|
|
Jul 09 06:45:11 PM PDT 24 |
Jul 09 06:50:33 PM PDT 24 |
3341491467 ps |
| T797 |
/workspace/coverage/default/39.sram_ctrl_mem_walk.876400538 |
|
|
Jul 09 06:50:01 PM PDT 24 |
Jul 09 06:55:24 PM PDT 24 |
72707900242 ps |
| T798 |
/workspace/coverage/default/29.sram_ctrl_smoke.638230574 |
|
|
Jul 09 06:47:47 PM PDT 24 |
Jul 09 06:47:57 PM PDT 24 |
3529773103 ps |
| T799 |
/workspace/coverage/default/34.sram_ctrl_stress_pipeline.1901753739 |
|
|
Jul 09 06:48:45 PM PDT 24 |
Jul 09 06:52:27 PM PDT 24 |
14923507918 ps |
| T800 |
/workspace/coverage/default/21.sram_ctrl_bijection.298417538 |
|
|
Jul 09 06:46:18 PM PDT 24 |
Jul 09 07:04:11 PM PDT 24 |
270908726688 ps |
| T801 |
/workspace/coverage/default/26.sram_ctrl_partial_access.3590689841 |
|
|
Jul 09 06:47:15 PM PDT 24 |
Jul 09 06:47:44 PM PDT 24 |
1662222760 ps |
| T802 |
/workspace/coverage/default/41.sram_ctrl_stress_pipeline.1215824611 |
|
|
Jul 09 06:50:18 PM PDT 24 |
Jul 09 06:54:39 PM PDT 24 |
5827881126 ps |
| T803 |
/workspace/coverage/default/4.sram_ctrl_lc_escalation.3108277585 |
|
|
Jul 09 06:44:16 PM PDT 24 |
Jul 09 06:45:32 PM PDT 24 |
12072322912 ps |
| T804 |
/workspace/coverage/default/4.sram_ctrl_regwen.3047479 |
|
|
Jul 09 06:44:17 PM PDT 24 |
Jul 09 07:00:08 PM PDT 24 |
3801203595 ps |
| T805 |
/workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.1030185960 |
|
|
Jul 09 06:49:55 PM PDT 24 |
Jul 09 06:50:15 PM PDT 24 |
702753406 ps |
| T806 |
/workspace/coverage/default/35.sram_ctrl_partial_access_b2b.2783575259 |
|
|
Jul 09 06:49:01 PM PDT 24 |
Jul 09 06:55:07 PM PDT 24 |
66432753391 ps |
| T807 |
/workspace/coverage/default/38.sram_ctrl_stress_all.29956406 |
|
|
Jul 09 06:49:50 PM PDT 24 |
Jul 09 07:34:50 PM PDT 24 |
271466697896 ps |
| T808 |
/workspace/coverage/default/49.sram_ctrl_max_throughput.1709154315 |
|
|
Jul 09 06:52:11 PM PDT 24 |
Jul 09 06:52:44 PM PDT 24 |
723085194 ps |
| T809 |
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.2860979131 |
|
|
Jul 09 06:44:19 PM PDT 24 |
Jul 09 06:49:18 PM PDT 24 |
4362898598 ps |
| T810 |
/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.414708648 |
|
|
Jul 09 06:45:43 PM PDT 24 |
Jul 09 06:53:16 PM PDT 24 |
67740462219 ps |
| T811 |
/workspace/coverage/default/33.sram_ctrl_smoke.1562657352 |
|
|
Jul 09 06:48:34 PM PDT 24 |
Jul 09 06:48:54 PM PDT 24 |
2271385946 ps |
| T32 |
/workspace/coverage/default/4.sram_ctrl_sec_cm.1874171686 |
|
|
Jul 09 06:44:15 PM PDT 24 |
Jul 09 06:44:19 PM PDT 24 |
631638618 ps |
| T812 |
/workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.13248180 |
|
|
Jul 09 06:48:12 PM PDT 24 |
Jul 09 06:48:20 PM PDT 24 |
2792093957 ps |
| T813 |
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.3411147962 |
|
|
Jul 09 06:44:58 PM PDT 24 |
Jul 09 06:47:27 PM PDT 24 |
4577037026 ps |
| T814 |
/workspace/coverage/default/35.sram_ctrl_max_throughput.2142108983 |
|
|
Jul 09 06:49:01 PM PDT 24 |
Jul 09 06:49:58 PM PDT 24 |
3018576148 ps |
| T815 |
/workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.137478281 |
|
|
Jul 09 06:45:24 PM PDT 24 |
Jul 09 06:45:32 PM PDT 24 |
1395532898 ps |
| T816 |
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.4206418988 |
|
|
Jul 09 06:44:38 PM PDT 24 |
Jul 09 06:52:56 PM PDT 24 |
31189571873 ps |
| T817 |
/workspace/coverage/default/37.sram_ctrl_mem_walk.1959985650 |
|
|
Jul 09 06:49:39 PM PDT 24 |
Jul 09 06:55:25 PM PDT 24 |
35887525402 ps |
| T818 |
/workspace/coverage/default/30.sram_ctrl_mem_walk.2996224667 |
|
|
Jul 09 06:48:07 PM PDT 24 |
Jul 09 06:53:56 PM PDT 24 |
43119867069 ps |
| T819 |
/workspace/coverage/default/20.sram_ctrl_partial_access.155617308 |
|
|
Jul 09 06:46:06 PM PDT 24 |
Jul 09 06:46:31 PM PDT 24 |
2362735588 ps |
| T820 |
/workspace/coverage/default/49.sram_ctrl_executable.2905775177 |
|
|
Jul 09 06:52:17 PM PDT 24 |
Jul 09 07:29:36 PM PDT 24 |
132000807092 ps |
| T821 |
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.4277293925 |
|
|
Jul 09 06:50:34 PM PDT 24 |
Jul 09 06:52:03 PM PDT 24 |
6320297756 ps |
| T822 |
/workspace/coverage/default/29.sram_ctrl_max_throughput.728700872 |
|
|
Jul 09 06:47:50 PM PDT 24 |
Jul 09 06:49:16 PM PDT 24 |
3118625677 ps |
| T823 |
/workspace/coverage/default/41.sram_ctrl_max_throughput.530661874 |
|
|
Jul 09 06:50:17 PM PDT 24 |
Jul 09 06:50:26 PM PDT 24 |
705145118 ps |
| T824 |
/workspace/coverage/default/22.sram_ctrl_smoke.2911299420 |
|
|
Jul 09 06:46:23 PM PDT 24 |
Jul 09 06:46:39 PM PDT 24 |
969398249 ps |
| T825 |
/workspace/coverage/default/25.sram_ctrl_stress_pipeline.2663775705 |
|
|
Jul 09 06:47:01 PM PDT 24 |
Jul 09 06:51:06 PM PDT 24 |
26878896770 ps |
| T826 |
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.3702261370 |
|
|
Jul 09 06:44:35 PM PDT 24 |
Jul 09 06:46:02 PM PDT 24 |
2676886044 ps |
| T827 |
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.1884960047 |
|
|
Jul 09 06:44:32 PM PDT 24 |
Jul 09 06:52:30 PM PDT 24 |
25479300462 ps |
| T828 |
/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.2303117192 |
|
|
Jul 09 06:48:27 PM PDT 24 |
Jul 09 06:58:31 PM PDT 24 |
24371094955 ps |
| T829 |
/workspace/coverage/default/45.sram_ctrl_mem_walk.4169178545 |
|
|
Jul 09 06:51:15 PM PDT 24 |
Jul 09 06:53:50 PM PDT 24 |
10974878660 ps |
| T830 |
/workspace/coverage/default/42.sram_ctrl_max_throughput.1644306614 |
|
|
Jul 09 06:50:34 PM PDT 24 |
Jul 09 06:51:04 PM PDT 24 |
4196827830 ps |
| T831 |
/workspace/coverage/default/18.sram_ctrl_multiple_keys.2881758752 |
|
|
Jul 09 06:45:45 PM PDT 24 |
Jul 09 06:57:00 PM PDT 24 |
34508250671 ps |
| T832 |
/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.1139933332 |
|
|
Jul 09 06:45:32 PM PDT 24 |
Jul 09 06:45:43 PM PDT 24 |
2732155640 ps |
| T833 |
/workspace/coverage/default/34.sram_ctrl_stress_all.3111501430 |
|
|
Jul 09 06:48:55 PM PDT 24 |
Jul 09 07:00:50 PM PDT 24 |
21728843475 ps |
| T834 |
/workspace/coverage/default/2.sram_ctrl_alert_test.3700673703 |
|
|
Jul 09 06:44:08 PM PDT 24 |
Jul 09 06:44:10 PM PDT 24 |
33643579 ps |
| T835 |
/workspace/coverage/default/25.sram_ctrl_alert_test.3074026337 |
|
|
Jul 09 06:47:08 PM PDT 24 |
Jul 09 06:47:14 PM PDT 24 |
16871123 ps |
| T836 |
/workspace/coverage/default/33.sram_ctrl_alert_test.3139728493 |
|
|
Jul 09 06:48:45 PM PDT 24 |
Jul 09 06:48:47 PM PDT 24 |
15711089 ps |
| T837 |
/workspace/coverage/default/25.sram_ctrl_stress_all.2295254823 |
|
|
Jul 09 06:47:08 PM PDT 24 |
Jul 09 07:26:31 PM PDT 24 |
55734423844 ps |
| T838 |
/workspace/coverage/default/48.sram_ctrl_max_throughput.3875161137 |
|
|
Jul 09 06:51:56 PM PDT 24 |
Jul 09 06:52:10 PM PDT 24 |
1448158365 ps |
| T839 |
/workspace/coverage/default/37.sram_ctrl_stress_all.253431250 |
|
|
Jul 09 06:49:41 PM PDT 24 |
Jul 09 08:39:40 PM PDT 24 |
239752046248 ps |
| T840 |
/workspace/coverage/default/28.sram_ctrl_max_throughput.2987898893 |
|
|
Jul 09 06:47:40 PM PDT 24 |
Jul 09 06:49:41 PM PDT 24 |
1525327389 ps |
| T841 |
/workspace/coverage/default/11.sram_ctrl_ram_cfg.1831825380 |
|
|
Jul 09 06:44:48 PM PDT 24 |
Jul 09 06:44:52 PM PDT 24 |
347021078 ps |
| T842 |
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.1390969710 |
|
|
Jul 09 06:50:50 PM PDT 24 |
Jul 09 06:53:33 PM PDT 24 |
17461843724 ps |
| T843 |
/workspace/coverage/default/7.sram_ctrl_executable.17841922 |
|
|
Jul 09 06:44:26 PM PDT 24 |
Jul 09 06:50:08 PM PDT 24 |
34377999245 ps |
| T844 |
/workspace/coverage/default/14.sram_ctrl_bijection.2448049350 |
|
|
Jul 09 06:45:15 PM PDT 24 |
Jul 09 07:25:41 PM PDT 24 |
508111229947 ps |
| T845 |
/workspace/coverage/default/17.sram_ctrl_multiple_keys.921086723 |
|
|
Jul 09 06:45:41 PM PDT 24 |
Jul 09 07:00:32 PM PDT 24 |
233683212453 ps |
| T846 |
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.2796666391 |
|
|
Jul 09 06:50:59 PM PDT 24 |
Jul 09 06:52:18 PM PDT 24 |
3393262366 ps |
| T847 |
/workspace/coverage/default/28.sram_ctrl_alert_test.1501318581 |
|
|
Jul 09 06:47:48 PM PDT 24 |
Jul 09 06:47:49 PM PDT 24 |
27414018 ps |
| T848 |
/workspace/coverage/default/43.sram_ctrl_ram_cfg.3488511430 |
|
|
Jul 09 06:50:49 PM PDT 24 |
Jul 09 06:50:53 PM PDT 24 |
713622252 ps |
| T849 |
/workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.275070460 |
|
|
Jul 09 06:48:33 PM PDT 24 |
Jul 09 06:51:01 PM PDT 24 |
950600132 ps |
| T850 |
/workspace/coverage/default/18.sram_ctrl_lc_escalation.3062649930 |
|
|
Jul 09 06:45:51 PM PDT 24 |
Jul 09 06:47:25 PM PDT 24 |
65395685530 ps |
| T851 |
/workspace/coverage/default/7.sram_ctrl_mem_walk.2643604503 |
|
|
Jul 09 06:44:27 PM PDT 24 |
Jul 09 06:47:42 PM PDT 24 |
114973998052 ps |
| T852 |
/workspace/coverage/default/34.sram_ctrl_max_throughput.1156764633 |
|
|
Jul 09 06:48:50 PM PDT 24 |
Jul 09 06:49:24 PM PDT 24 |
1424465491 ps |
| T853 |
/workspace/coverage/default/9.sram_ctrl_lc_escalation.1605739683 |
|
|
Jul 09 06:44:30 PM PDT 24 |
Jul 09 06:45:40 PM PDT 24 |
69137047394 ps |
| T854 |
/workspace/coverage/default/11.sram_ctrl_partial_access.390839921 |
|
|
Jul 09 06:44:47 PM PDT 24 |
Jul 09 06:44:56 PM PDT 24 |
720678436 ps |
| T855 |
/workspace/coverage/default/14.sram_ctrl_regwen.4285769446 |
|
|
Jul 09 06:45:19 PM PDT 24 |
Jul 09 06:46:20 PM PDT 24 |
3099138991 ps |
| T856 |
/workspace/coverage/default/3.sram_ctrl_access_during_key_req.1479870146 |
|
|
Jul 09 06:44:09 PM PDT 24 |
Jul 09 06:45:27 PM PDT 24 |
2523724556 ps |
| T857 |
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.3158556399 |
|
|
Jul 09 06:51:13 PM PDT 24 |
Jul 09 07:16:14 PM PDT 24 |
16343428535 ps |
| T858 |
/workspace/coverage/default/34.sram_ctrl_alert_test.857451166 |
|
|
Jul 09 06:48:58 PM PDT 24 |
Jul 09 06:48:59 PM PDT 24 |
12789824 ps |
| T859 |
/workspace/coverage/default/8.sram_ctrl_regwen.2593965355 |
|
|
Jul 09 06:44:29 PM PDT 24 |
Jul 09 07:11:57 PM PDT 24 |
131174571005 ps |
| T860 |
/workspace/coverage/default/26.sram_ctrl_partial_access_b2b.1906151884 |
|
|
Jul 09 06:47:13 PM PDT 24 |
Jul 09 06:55:50 PM PDT 24 |
34877509440 ps |
| T861 |
/workspace/coverage/default/1.sram_ctrl_max_throughput.4108813408 |
|
|
Jul 09 06:43:56 PM PDT 24 |
Jul 09 06:46:03 PM PDT 24 |
805988894 ps |
| T862 |
/workspace/coverage/default/13.sram_ctrl_multiple_keys.4130240954 |
|
|
Jul 09 06:44:58 PM PDT 24 |
Jul 09 07:03:49 PM PDT 24 |
19684902168 ps |
| T863 |
/workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.3887091349 |
|
|
Jul 09 06:50:00 PM PDT 24 |
Jul 09 06:50:13 PM PDT 24 |
350831048 ps |
| T864 |
/workspace/coverage/default/15.sram_ctrl_stress_pipeline.2448971329 |
|
|
Jul 09 06:45:25 PM PDT 24 |
Jul 09 06:48:54 PM PDT 24 |
4418886777 ps |
| T865 |
/workspace/coverage/default/5.sram_ctrl_mem_walk.3841835857 |
|
|
Jul 09 06:44:21 PM PDT 24 |
Jul 09 06:46:34 PM PDT 24 |
8978994473 ps |
| T866 |
/workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.4133704854 |
|
|
Jul 09 06:44:12 PM PDT 24 |
Jul 09 06:45:01 PM PDT 24 |
3963469475 ps |
| T867 |
/workspace/coverage/default/24.sram_ctrl_smoke.2117758091 |
|
|
Jul 09 06:46:54 PM PDT 24 |
Jul 09 06:47:13 PM PDT 24 |
3210580896 ps |
| T868 |
/workspace/coverage/default/47.sram_ctrl_max_throughput.190010770 |
|
|
Jul 09 06:51:41 PM PDT 24 |
Jul 09 06:52:30 PM PDT 24 |
723195285 ps |
| T869 |
/workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.285352702 |
|
|
Jul 09 06:45:23 PM PDT 24 |
Jul 09 06:45:52 PM PDT 24 |
1182549905 ps |
| T870 |
/workspace/coverage/default/8.sram_ctrl_lc_escalation.3546775676 |
|
|
Jul 09 06:44:29 PM PDT 24 |
Jul 09 06:44:50 PM PDT 24 |
4210311228 ps |
| T871 |
/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.564890999 |
|
|
Jul 09 06:49:17 PM PDT 24 |
Jul 09 06:56:59 PM PDT 24 |
8177317517 ps |
| T872 |
/workspace/coverage/default/31.sram_ctrl_alert_test.985654556 |
|
|
Jul 09 06:48:22 PM PDT 24 |
Jul 09 06:48:23 PM PDT 24 |
26931365 ps |
| T873 |
/workspace/coverage/default/13.sram_ctrl_stress_pipeline.2023646774 |
|
|
Jul 09 06:44:58 PM PDT 24 |
Jul 09 06:49:30 PM PDT 24 |
16454641560 ps |
| T874 |
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.3794885177 |
|
|
Jul 09 06:44:26 PM PDT 24 |
Jul 09 06:47:07 PM PDT 24 |
5568271294 ps |
| T875 |
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.4032714407 |
|
|
Jul 09 06:52:02 PM PDT 24 |
Jul 09 06:54:16 PM PDT 24 |
6358226796 ps |
| T876 |
/workspace/coverage/default/42.sram_ctrl_regwen.1150089763 |
|
|
Jul 09 06:50:33 PM PDT 24 |
Jul 09 07:04:56 PM PDT 24 |
9696913686 ps |
| T877 |
/workspace/coverage/default/41.sram_ctrl_ram_cfg.1987717467 |
|
|
Jul 09 06:50:28 PM PDT 24 |
Jul 09 06:50:32 PM PDT 24 |
1397100501 ps |
| T878 |
/workspace/coverage/default/15.sram_ctrl_multiple_keys.2294927908 |
|
|
Jul 09 06:45:18 PM PDT 24 |
Jul 09 06:57:51 PM PDT 24 |
15760380727 ps |
| T879 |
/workspace/coverage/default/33.sram_ctrl_partial_access_b2b.630864454 |
|
|
Jul 09 06:48:34 PM PDT 24 |
Jul 09 06:54:39 PM PDT 24 |
6956021786 ps |
| T880 |
/workspace/coverage/default/38.sram_ctrl_partial_access_b2b.3862981449 |
|
|
Jul 09 06:49:39 PM PDT 24 |
Jul 09 06:55:14 PM PDT 24 |
127698507037 ps |
| T881 |
/workspace/coverage/default/37.sram_ctrl_multiple_keys.2686013012 |
|
|
Jul 09 06:49:28 PM PDT 24 |
Jul 09 06:52:41 PM PDT 24 |
4386966068 ps |
| T882 |
/workspace/coverage/default/8.sram_ctrl_executable.1225373784 |
|
|
Jul 09 06:44:29 PM PDT 24 |
Jul 09 06:51:58 PM PDT 24 |
14104335960 ps |
| T883 |
/workspace/coverage/default/25.sram_ctrl_ram_cfg.1039218845 |
|
|
Jul 09 06:47:08 PM PDT 24 |
Jul 09 06:47:16 PM PDT 24 |
433035836 ps |
| T884 |
/workspace/coverage/default/39.sram_ctrl_access_during_key_req.3813318472 |
|
|
Jul 09 06:49:56 PM PDT 24 |
Jul 09 06:53:26 PM PDT 24 |
5721630990 ps |
| T885 |
/workspace/coverage/default/18.sram_ctrl_bijection.3698247403 |
|
|
Jul 09 06:45:51 PM PDT 24 |
Jul 09 07:04:38 PM PDT 24 |
192562189810 ps |
| T886 |
/workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.2304604089 |
|
|
Jul 09 06:48:11 PM PDT 24 |
Jul 09 06:50:15 PM PDT 24 |
1681193806 ps |
| T887 |
/workspace/coverage/default/4.sram_ctrl_stress_all.3036157897 |
|
|
Jul 09 06:44:13 PM PDT 24 |
Jul 09 08:46:00 PM PDT 24 |
266464875090 ps |
| T888 |
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.4143176888 |
|
|
Jul 09 06:44:49 PM PDT 24 |
Jul 09 06:44:59 PM PDT 24 |
2216107319 ps |
| T889 |
/workspace/coverage/default/5.sram_ctrl_stress_all.2654345697 |
|
|
Jul 09 06:44:19 PM PDT 24 |
Jul 09 07:20:22 PM PDT 24 |
413580226433 ps |
| T890 |
/workspace/coverage/default/38.sram_ctrl_stress_pipeline.3700918439 |
|
|
Jul 09 06:49:40 PM PDT 24 |
Jul 09 06:53:20 PM PDT 24 |
4749545413 ps |
| T891 |
/workspace/coverage/default/34.sram_ctrl_bijection.351880488 |
|
|
Jul 09 06:48:44 PM PDT 24 |
Jul 09 07:11:57 PM PDT 24 |
19520305128 ps |
| T892 |
/workspace/coverage/default/40.sram_ctrl_alert_test.3576233991 |
|
|
Jul 09 06:50:16 PM PDT 24 |
Jul 09 06:50:18 PM PDT 24 |
11216388 ps |
| T893 |
/workspace/coverage/default/32.sram_ctrl_multiple_keys.991925687 |
|
|
Jul 09 06:48:23 PM PDT 24 |
Jul 09 06:57:47 PM PDT 24 |
23037277081 ps |
| T894 |
/workspace/coverage/default/41.sram_ctrl_mem_partial_access.451294111 |
|
|
Jul 09 06:50:23 PM PDT 24 |
Jul 09 06:53:11 PM PDT 24 |
26372859575 ps |
| T895 |
/workspace/coverage/default/48.sram_ctrl_ram_cfg.4143805151 |
|
|
Jul 09 06:52:02 PM PDT 24 |
Jul 09 06:52:06 PM PDT 24 |
462958855 ps |
| T896 |
/workspace/coverage/default/36.sram_ctrl_mem_partial_access.990568125 |
|
|
Jul 09 06:49:24 PM PDT 24 |
Jul 09 06:52:11 PM PDT 24 |
38495010434 ps |
| T897 |
/workspace/coverage/default/16.sram_ctrl_access_during_key_req.1778912224 |
|
|
Jul 09 06:45:37 PM PDT 24 |
Jul 09 07:11:26 PM PDT 24 |
30056106390 ps |
| T898 |
/workspace/coverage/default/6.sram_ctrl_partial_access.4006502327 |
|
|
Jul 09 06:44:17 PM PDT 24 |
Jul 09 06:44:35 PM PDT 24 |
2243607967 ps |
| T899 |
/workspace/coverage/default/1.sram_ctrl_regwen.3675595778 |
|
|
Jul 09 06:44:02 PM PDT 24 |
Jul 09 06:54:44 PM PDT 24 |
2516491485 ps |
| T900 |
/workspace/coverage/default/14.sram_ctrl_access_during_key_req.1486417997 |
|
|
Jul 09 06:45:12 PM PDT 24 |
Jul 09 07:00:33 PM PDT 24 |
51081025206 ps |
| T901 |
/workspace/coverage/default/13.sram_ctrl_lc_escalation.3420717051 |
|
|
Jul 09 06:45:05 PM PDT 24 |
Jul 09 06:46:05 PM PDT 24 |
9709437257 ps |
| T902 |
/workspace/coverage/default/40.sram_ctrl_executable.2969395593 |
|
|
Jul 09 06:50:11 PM PDT 24 |
Jul 09 07:17:29 PM PDT 24 |
65781362518 ps |
| T903 |
/workspace/coverage/default/8.sram_ctrl_stress_all.1006447456 |
|
|
Jul 09 06:44:29 PM PDT 24 |
Jul 09 08:54:31 PM PDT 24 |
243227535736 ps |
| T904 |
/workspace/coverage/default/11.sram_ctrl_bijection.53804016 |
|
|
Jul 09 06:44:43 PM PDT 24 |
Jul 09 07:02:01 PM PDT 24 |
248566390640 ps |
| T905 |
/workspace/coverage/default/32.sram_ctrl_executable.1436855163 |
|
|
Jul 09 06:48:28 PM PDT 24 |
Jul 09 06:54:46 PM PDT 24 |
41086280320 ps |
| T906 |
/workspace/coverage/default/0.sram_ctrl_max_throughput.491045527 |
|
|
Jul 09 06:43:56 PM PDT 24 |
Jul 09 06:44:25 PM PDT 24 |
1427205669 ps |
| T907 |
/workspace/coverage/default/46.sram_ctrl_mem_walk.3793793257 |
|
|
Jul 09 06:51:27 PM PDT 24 |
Jul 09 06:53:56 PM PDT 24 |
2634200629 ps |
| T908 |
/workspace/coverage/default/21.sram_ctrl_max_throughput.1109371899 |
|
|
Jul 09 06:46:17 PM PDT 24 |
Jul 09 06:47:06 PM PDT 24 |
1528937418 ps |
| T909 |
/workspace/coverage/default/13.sram_ctrl_max_throughput.1011195703 |
|
|
Jul 09 06:45:01 PM PDT 24 |
Jul 09 06:46:15 PM PDT 24 |
788633625 ps |
| T910 |
/workspace/coverage/default/46.sram_ctrl_stress_all.3677711775 |
|
|
Jul 09 06:51:29 PM PDT 24 |
Jul 09 07:50:54 PM PDT 24 |
65296218994 ps |
| T911 |
/workspace/coverage/default/30.sram_ctrl_stress_pipeline.3128899369 |
|
|
Jul 09 06:48:05 PM PDT 24 |
Jul 09 06:52:41 PM PDT 24 |
5352405495 ps |
| T912 |
/workspace/coverage/default/28.sram_ctrl_partial_access_b2b.2808642135 |
|
|
Jul 09 06:47:39 PM PDT 24 |
Jul 09 06:53:34 PM PDT 24 |
15315316319 ps |
| T913 |
/workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.249391470 |
|
|
Jul 09 06:47:30 PM PDT 24 |
Jul 09 06:49:06 PM PDT 24 |
3336585624 ps |
| T914 |
/workspace/coverage/default/29.sram_ctrl_mem_walk.719612196 |
|
|
Jul 09 06:47:56 PM PDT 24 |
Jul 09 06:53:13 PM PDT 24 |
13855784155 ps |
| T915 |
/workspace/coverage/default/32.sram_ctrl_mem_partial_access.3122846957 |
|
|
Jul 09 06:48:34 PM PDT 24 |
Jul 09 06:49:40 PM PDT 24 |
3419106586 ps |
| T916 |
/workspace/coverage/default/44.sram_ctrl_lc_escalation.988041426 |
|
|
Jul 09 06:50:58 PM PDT 24 |
Jul 09 06:51:49 PM PDT 24 |
8111060782 ps |
| T917 |
/workspace/coverage/default/34.sram_ctrl_ram_cfg.1084346983 |
|
|
Jul 09 06:48:58 PM PDT 24 |
Jul 09 06:49:03 PM PDT 24 |
1243099577 ps |
| T918 |
/workspace/coverage/default/37.sram_ctrl_max_throughput.457022744 |
|
|
Jul 09 06:49:28 PM PDT 24 |
Jul 09 06:50:39 PM PDT 24 |
781992705 ps |
| T919 |
/workspace/coverage/default/19.sram_ctrl_executable.866189831 |
|
|
Jul 09 06:46:04 PM PDT 24 |
Jul 09 07:13:52 PM PDT 24 |
88438684121 ps |
| T920 |
/workspace/coverage/default/20.sram_ctrl_lc_escalation.3016116244 |
|
|
Jul 09 06:46:15 PM PDT 24 |
Jul 09 06:47:17 PM PDT 24 |
9432152253 ps |
| T921 |
/workspace/coverage/default/12.sram_ctrl_lc_escalation.1994626712 |
|
|
Jul 09 06:44:54 PM PDT 24 |
Jul 09 06:46:32 PM PDT 24 |
29164704785 ps |
| T922 |
/workspace/coverage/default/35.sram_ctrl_mem_partial_access.2142455607 |
|
|
Jul 09 06:49:12 PM PDT 24 |
Jul 09 06:51:42 PM PDT 24 |
4945351880 ps |
| T923 |
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2482491594 |
|
|
Jul 09 06:44:29 PM PDT 24 |
Jul 09 06:44:42 PM PDT 24 |
329496353 ps |
| T924 |
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.744678435 |
|
|
Jul 09 06:51:10 PM PDT 24 |
Jul 09 06:57:51 PM PDT 24 |
29320767415 ps |
| T925 |
/workspace/coverage/default/29.sram_ctrl_executable.135524776 |
|
|
Jul 09 06:47:50 PM PDT 24 |
Jul 09 06:58:02 PM PDT 24 |
7510890296 ps |
| T926 |
/workspace/coverage/default/35.sram_ctrl_alert_test.3957120432 |
|
|
Jul 09 06:49:14 PM PDT 24 |
Jul 09 06:49:15 PM PDT 24 |
17697894 ps |
| T927 |
/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.3316559359 |
|
|
Jul 09 06:44:58 PM PDT 24 |
Jul 09 06:45:04 PM PDT 24 |
1612071021 ps |
| T928 |
/workspace/coverage/default/43.sram_ctrl_stress_all.2196308263 |
|
|
Jul 09 06:50:48 PM PDT 24 |
Jul 09 07:00:14 PM PDT 24 |
109247633549 ps |
| T929 |
/workspace/coverage/default/35.sram_ctrl_partial_access.147074786 |
|
|
Jul 09 06:49:03 PM PDT 24 |
Jul 09 06:50:22 PM PDT 24 |
1879343835 ps |
| T930 |
/workspace/coverage/default/4.sram_ctrl_mem_partial_access.2133110888 |
|
|
Jul 09 06:44:12 PM PDT 24 |
Jul 09 06:46:53 PM PDT 24 |
11658355027 ps |
| T931 |
/workspace/coverage/default/36.sram_ctrl_mem_walk.2016739940 |
|
|
Jul 09 06:49:23 PM PDT 24 |
Jul 09 06:54:29 PM PDT 24 |
21878401587 ps |
| T932 |
/workspace/coverage/default/32.sram_ctrl_smoke.2744200756 |
|
|
Jul 09 06:48:21 PM PDT 24 |
Jul 09 06:48:40 PM PDT 24 |
547004691 ps |
| T933 |
/workspace/coverage/default/38.sram_ctrl_max_throughput.102622142 |
|
|
Jul 09 06:49:44 PM PDT 24 |
Jul 09 06:51:35 PM PDT 24 |
8491820418 ps |
| T934 |
/workspace/coverage/default/6.sram_ctrl_multiple_keys.2423655655 |
|
|
Jul 09 06:44:18 PM PDT 24 |
Jul 09 06:44:47 PM PDT 24 |
5971330124 ps |
| T935 |
/workspace/coverage/default/10.sram_ctrl_smoke.172382961 |
|
|
Jul 09 06:44:36 PM PDT 24 |
Jul 09 06:46:57 PM PDT 24 |
1332677029 ps |
| T936 |
/workspace/coverage/default/22.sram_ctrl_regwen.718660272 |
|
|
Jul 09 06:46:29 PM PDT 24 |
Jul 09 07:01:58 PM PDT 24 |
12877520246 ps |
| T937 |
/workspace/coverage/default/23.sram_ctrl_mem_walk.1052628113 |
|
|
Jul 09 06:46:45 PM PDT 24 |
Jul 09 06:51:05 PM PDT 24 |
3986411786 ps |
| T938 |
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.207451464 |
|
|
Jul 09 06:44:18 PM PDT 24 |
Jul 09 06:46:31 PM PDT 24 |
792104475 ps |
| T939 |
/workspace/coverage/default/3.sram_ctrl_regwen.2850259340 |
|
|
Jul 09 06:44:08 PM PDT 24 |
Jul 09 06:46:43 PM PDT 24 |
1526262782 ps |
| T940 |
/workspace/coverage/default/42.sram_ctrl_smoke.3814792749 |
|
|
Jul 09 06:50:22 PM PDT 24 |
Jul 09 06:50:42 PM PDT 24 |
2525907579 ps |
| T941 |
/workspace/coverage/default/13.sram_ctrl_partial_access.3225225153 |
|
|
Jul 09 06:44:58 PM PDT 24 |
Jul 09 06:45:37 PM PDT 24 |
786744884 ps |
| T942 |
/workspace/coverage/default/40.sram_ctrl_partial_access.1940744332 |
|
|
Jul 09 06:50:10 PM PDT 24 |
Jul 09 06:50:21 PM PDT 24 |
1252737122 ps |
| T943 |
/workspace/coverage/default/26.sram_ctrl_stress_pipeline.1006253108 |
|
|
Jul 09 06:47:14 PM PDT 24 |
Jul 09 06:50:00 PM PDT 24 |
15236925566 ps |
| T944 |
/workspace/coverage/default/4.sram_ctrl_bijection.3549163173 |
|
|
Jul 09 06:44:11 PM PDT 24 |
Jul 09 07:18:58 PM PDT 24 |
29515438947 ps |
| T62 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3642243272 |
|
|
Jul 09 06:32:08 PM PDT 24 |
Jul 09 06:32:39 PM PDT 24 |
130357425 ps |
| T63 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.846486471 |
|
|
Jul 09 06:32:11 PM PDT 24 |
Jul 09 06:32:43 PM PDT 24 |
124984131 ps |
| T65 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3582137567 |
|
|
Jul 09 06:31:58 PM PDT 24 |
Jul 09 06:33:14 PM PDT 24 |
27345221036 ps |
| T945 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3561641199 |
|
|
Jul 09 06:32:23 PM PDT 24 |
Jul 09 06:32:55 PM PDT 24 |
3889174947 ps |
| T72 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1812369528 |
|
|
Jul 09 06:32:28 PM PDT 24 |
Jul 09 06:32:55 PM PDT 24 |
14965198 ps |
| T64 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.719641963 |
|
|
Jul 09 06:31:56 PM PDT 24 |
Jul 09 06:32:18 PM PDT 24 |
331518962 ps |
| T946 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1368529918 |
|
|
Jul 09 06:32:32 PM PDT 24 |
Jul 09 06:33:00 PM PDT 24 |
138351814 ps |
| T103 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2129218479 |
|
|
Jul 09 06:32:05 PM PDT 24 |
Jul 09 06:32:34 PM PDT 24 |
86565282 ps |
| T128 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2284706553 |
|
|
Jul 09 06:32:29 PM PDT 24 |
Jul 09 06:32:56 PM PDT 24 |
145439885 ps |
| T947 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2797153246 |
|
|
Jul 09 06:31:59 PM PDT 24 |
Jul 09 06:32:27 PM PDT 24 |
375377681 ps |
| T73 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3329553851 |
|
|
Jul 09 06:32:21 PM PDT 24 |
Jul 09 06:32:50 PM PDT 24 |
29563264 ps |
| T948 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1603973553 |
|
|
Jul 09 06:32:02 PM PDT 24 |
Jul 09 06:32:32 PM PDT 24 |
360408374 ps |
| T74 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3390971013 |
|
|
Jul 09 06:32:20 PM PDT 24 |
Jul 09 06:33:56 PM PDT 24 |
117384164797 ps |
| T949 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3052481071 |
|
|
Jul 09 06:32:07 PM PDT 24 |
Jul 09 06:32:41 PM PDT 24 |
514847552 ps |
| T112 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2532194692 |
|
|
Jul 09 06:32:06 PM PDT 24 |
Jul 09 06:32:37 PM PDT 24 |
110540417 ps |
| T950 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.48108052 |
|
|
Jul 09 06:31:59 PM PDT 24 |
Jul 09 06:32:27 PM PDT 24 |
707251732 ps |
| T104 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1340644572 |
|
|
Jul 09 06:32:32 PM PDT 24 |
Jul 09 06:32:57 PM PDT 24 |
129043484 ps |
| T75 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.418904344 |
|
|
Jul 09 06:32:17 PM PDT 24 |
Jul 09 06:32:46 PM PDT 24 |
117301879 ps |
| T122 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.969128733 |
|
|
Jul 09 06:32:32 PM PDT 24 |
Jul 09 06:32:58 PM PDT 24 |
655603947 ps |
| T113 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1740188458 |
|
|
Jul 09 06:31:56 PM PDT 24 |
Jul 09 06:32:18 PM PDT 24 |
38831804 ps |
| T76 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1984192102 |
|
|
Jul 09 06:32:17 PM PDT 24 |
Jul 09 06:33:35 PM PDT 24 |
7270065625 ps |
| T951 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1448023084 |
|
|
Jul 09 06:32:04 PM PDT 24 |
Jul 09 06:32:32 PM PDT 24 |
14758084 ps |
| T952 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3532150005 |
|
|
Jul 09 06:32:24 PM PDT 24 |
Jul 09 06:32:54 PM PDT 24 |
518910276 ps |
| T953 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1423114256 |
|
|
Jul 09 06:32:12 PM PDT 24 |
Jul 09 06:32:42 PM PDT 24 |
24485658 ps |
| T954 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.998187843 |
|
|
Jul 09 06:32:00 PM PDT 24 |
Jul 09 06:32:24 PM PDT 24 |
14922884 ps |
| T955 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1960995295 |
|
|
Jul 09 06:32:16 PM PDT 24 |
Jul 09 06:32:50 PM PDT 24 |
371262061 ps |
| T956 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3219567324 |
|
|
Jul 09 06:31:59 PM PDT 24 |
Jul 09 06:32:25 PM PDT 24 |
55481657 ps |
| T105 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1829010180 |
|
|
Jul 09 06:32:14 PM PDT 24 |
Jul 09 06:32:44 PM PDT 24 |
27334332 ps |
| T957 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3325505149 |
|
|
Jul 09 06:32:20 PM PDT 24 |
Jul 09 06:32:52 PM PDT 24 |
361622632 ps |
| T77 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2822148693 |
|
|
Jul 09 06:31:53 PM PDT 24 |
Jul 09 06:32:14 PM PDT 24 |
98795260 ps |
| T78 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.26749198 |
|
|
Jul 09 06:32:14 PM PDT 24 |
Jul 09 06:32:44 PM PDT 24 |
185149543 ps |
| T79 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.852294631 |
|
|
Jul 09 06:32:08 PM PDT 24 |
Jul 09 06:32:38 PM PDT 24 |
150047627 ps |
| T106 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.130628413 |
|
|
Jul 09 06:32:29 PM PDT 24 |
Jul 09 06:32:55 PM PDT 24 |
76846544 ps |
| T80 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2304025519 |
|
|
Jul 09 06:31:56 PM PDT 24 |
Jul 09 06:32:18 PM PDT 24 |
20035676 ps |
| T958 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1510577437 |
|
|
Jul 09 06:32:36 PM PDT 24 |
Jul 09 06:33:02 PM PDT 24 |
30815386 ps |
| T82 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2734340057 |
|
|
Jul 09 06:32:24 PM PDT 24 |
Jul 09 06:33:53 PM PDT 24 |
26159315371 ps |
| T83 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.4055091700 |
|
|
Jul 09 06:31:56 PM PDT 24 |
Jul 09 06:33:05 PM PDT 24 |
7333740875 ps |
| T959 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1144904662 |
|
|
Jul 09 06:32:38 PM PDT 24 |
Jul 09 06:33:01 PM PDT 24 |
32809620 ps |
| T960 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.233228357 |
|
|
Jul 09 06:32:29 PM PDT 24 |
Jul 09 06:32:59 PM PDT 24 |
420870374 ps |
| T961 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.85747617 |
|
|
Jul 09 06:32:00 PM PDT 24 |
Jul 09 06:32:24 PM PDT 24 |
38020232 ps |
| T962 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3224752307 |
|
|
Jul 09 06:32:12 PM PDT 24 |
Jul 09 06:32:44 PM PDT 24 |
119259657 ps |
| T84 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.345683013 |
|
|
Jul 09 06:32:16 PM PDT 24 |
Jul 09 06:33:16 PM PDT 24 |
15375858162 ps |
| T963 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.4284350818 |
|
|
Jul 09 06:32:21 PM PDT 24 |
Jul 09 06:32:53 PM PDT 24 |
209058763 ps |
| T85 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.4183333248 |
|
|
Jul 09 06:32:20 PM PDT 24 |
Jul 09 06:32:50 PM PDT 24 |
115460782 ps |
| T964 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1833890966 |
|
|
Jul 09 06:32:10 PM PDT 24 |
Jul 09 06:32:43 PM PDT 24 |
365345051 ps |
| T965 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.934094901 |
|
|
Jul 09 06:32:18 PM PDT 24 |
Jul 09 06:32:47 PM PDT 24 |
34382529 ps |
| T86 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3275166672 |
|
|
Jul 09 06:32:32 PM PDT 24 |
Jul 09 06:32:57 PM PDT 24 |
49121442 ps |
| T966 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.4201322496 |
|
|
Jul 09 06:32:16 PM PDT 24 |
Jul 09 06:32:48 PM PDT 24 |
80551630 ps |
| T125 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3049406524 |
|
|
Jul 09 06:32:18 PM PDT 24 |
Jul 09 06:32:49 PM PDT 24 |
178086955 ps |
| T967 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2571127866 |
|
|
Jul 09 06:32:06 PM PDT 24 |
Jul 09 06:32:36 PM PDT 24 |
25828003 ps |
| T968 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1021505890 |
|
|
Jul 09 06:32:09 PM PDT 24 |
Jul 09 06:32:38 PM PDT 24 |
15916842 ps |
| T969 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3304177192 |
|
|
Jul 09 06:31:56 PM PDT 24 |
Jul 09 06:32:18 PM PDT 24 |
23030847 ps |
| T970 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.983749909 |
|
|
Jul 09 06:32:37 PM PDT 24 |
Jul 09 06:33:03 PM PDT 24 |
367625767 ps |
| T132 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.4185356627 |
|
|
Jul 09 06:32:37 PM PDT 24 |
Jul 09 06:33:01 PM PDT 24 |
247898420 ps |
| T971 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3761613645 |
|
|
Jul 09 06:31:56 PM PDT 24 |
Jul 09 06:32:17 PM PDT 24 |
15088423 ps |
| T87 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.861992990 |
|
|
Jul 09 06:32:19 PM PDT 24 |
Jul 09 06:32:48 PM PDT 24 |
31696904 ps |
| T972 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1939311936 |
|
|
Jul 09 06:32:31 PM PDT 24 |
Jul 09 06:32:55 PM PDT 24 |
11736318 ps |
| T973 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1183309780 |
|
|
Jul 09 06:31:56 PM PDT 24 |
Jul 09 06:32:20 PM PDT 24 |
264185920 ps |
| T123 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1255430611 |
|
|
Jul 09 06:32:17 PM PDT 24 |
Jul 09 06:32:47 PM PDT 24 |
449016025 ps |
| T974 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3410955271 |
|
|
Jul 09 06:32:24 PM PDT 24 |
Jul 09 06:32:52 PM PDT 24 |
155129119 ps |
| T88 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.642838939 |
|
|
Jul 09 06:32:02 PM PDT 24 |
Jul 09 06:32:30 PM PDT 24 |
45558887 ps |
| T975 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2568427403 |
|
|
Jul 09 06:32:10 PM PDT 24 |
Jul 09 06:32:43 PM PDT 24 |
124386886 ps |
| T976 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1326845637 |
|
|
Jul 09 06:32:09 PM PDT 24 |
Jul 09 06:32:40 PM PDT 24 |
81784594 ps |
| T977 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1224065718 |
|
|
Jul 09 06:31:54 PM PDT 24 |
Jul 09 06:32:14 PM PDT 24 |
38631867 ps |
| T978 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.340065449 |
|
|
Jul 09 06:32:27 PM PDT 24 |
Jul 09 06:32:55 PM PDT 24 |
45105723 ps |
| T95 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3239976618 |
|
|
Jul 09 06:32:24 PM PDT 24 |
Jul 09 06:33:20 PM PDT 24 |
46085308755 ps |
| T129 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3025795232 |
|
|
Jul 09 06:32:04 PM PDT 24 |
Jul 09 06:32:33 PM PDT 24 |
397451873 ps |
| T979 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2261744191 |
|
|
Jul 09 06:32:30 PM PDT 24 |
Jul 09 06:32:59 PM PDT 24 |
1442256782 ps |
| T980 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1739688805 |
|
|
Jul 09 06:32:20 PM PDT 24 |
Jul 09 06:32:50 PM PDT 24 |
15703874 ps |
| T981 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3635525392 |
|
|
Jul 09 06:32:27 PM PDT 24 |
Jul 09 06:32:56 PM PDT 24 |
720377658 ps |
| T94 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3830047382 |
|
|
Jul 09 06:32:01 PM PDT 24 |
Jul 09 06:32:27 PM PDT 24 |
14726635 ps |
| T982 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.132261255 |
|
|
Jul 09 06:32:38 PM PDT 24 |
Jul 09 06:33:03 PM PDT 24 |
811045643 ps |
| T983 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.316846963 |
|
|
Jul 09 06:32:03 PM PDT 24 |
Jul 09 06:32:32 PM PDT 24 |
21835191 ps |
| T984 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.592775504 |
|
|
Jul 09 06:32:07 PM PDT 24 |
Jul 09 06:32:41 PM PDT 24 |
166513222 ps |
| T126 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.254456711 |
|
|
Jul 09 06:32:31 PM PDT 24 |
Jul 09 06:32:57 PM PDT 24 |
226265915 ps |
| T97 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2051328464 |
|
|
Jul 09 06:32:37 PM PDT 24 |
Jul 09 06:33:24 PM PDT 24 |
3905254939 ps |
| T96 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3825130769 |
|
|
Jul 09 06:31:54 PM PDT 24 |
Jul 09 06:32:43 PM PDT 24 |
15399919713 ps |
| T985 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2826272418 |
|
|
Jul 09 06:32:29 PM PDT 24 |
Jul 09 06:32:55 PM PDT 24 |
34771327 ps |
| T986 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1024450155 |
|
|
Jul 09 06:32:16 PM PDT 24 |
Jul 09 06:32:46 PM PDT 24 |
205310021 ps |
| T987 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3834279293 |
|
|
Jul 09 06:32:32 PM PDT 24 |
Jul 09 06:32:58 PM PDT 24 |
798203626 ps |
| T98 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.921130153 |
|
|
Jul 09 06:31:56 PM PDT 24 |
Jul 09 06:32:17 PM PDT 24 |
50308167 ps |
| T99 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3261785357 |
|
|
Jul 09 06:32:33 PM PDT 24 |
Jul 09 06:32:58 PM PDT 24 |
24501277 ps |
| T988 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.4030652120 |
|
|
Jul 09 06:32:22 PM PDT 24 |
Jul 09 06:32:50 PM PDT 24 |
66323246 ps |
| T989 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1536082760 |
|
|
Jul 09 06:31:56 PM PDT 24 |
Jul 09 06:32:21 PM PDT 24 |
370855304 ps |
| T990 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.608864285 |
|
|
Jul 09 06:32:34 PM PDT 24 |
Jul 09 06:33:02 PM PDT 24 |
5737015326 ps |
| T991 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.4116033884 |
|
|
Jul 09 06:32:33 PM PDT 24 |
Jul 09 06:33:01 PM PDT 24 |
141617825 ps |
| T130 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1764454424 |
|
|
Jul 09 06:31:54 PM PDT 24 |
Jul 09 06:32:15 PM PDT 24 |
80976962 ps |
| T992 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.824996768 |
|
|
Jul 09 06:32:33 PM PDT 24 |
Jul 09 06:32:58 PM PDT 24 |
25869995 ps |
| T993 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1572541259 |
|
|
Jul 09 06:32:20 PM PDT 24 |
Jul 09 06:33:19 PM PDT 24 |
7248554680 ps |
| T994 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2984839973 |
|
|
Jul 09 06:32:27 PM PDT 24 |
Jul 09 06:33:26 PM PDT 24 |
26313882736 ps |
| T995 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2499211598 |
|
|
Jul 09 06:31:55 PM PDT 24 |
Jul 09 06:32:18 PM PDT 24 |
1535824198 ps |
| T996 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.4177974011 |
|
|
Jul 09 06:32:03 PM PDT 24 |
Jul 09 06:32:32 PM PDT 24 |
12628134 ps |
| T997 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.14435981 |
|
|
Jul 09 06:32:14 PM PDT 24 |
Jul 09 06:32:47 PM PDT 24 |
689848085 ps |
| T998 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1531685574 |
|
|
Jul 09 06:32:09 PM PDT 24 |
Jul 09 06:33:29 PM PDT 24 |
14357478745 ps |
| T999 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3756890749 |
|
|
Jul 09 06:31:59 PM PDT 24 |
Jul 09 06:32:24 PM PDT 24 |
18908527 ps |
| T1000 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.142927823 |
|
|
Jul 09 06:32:21 PM PDT 24 |
Jul 09 06:32:50 PM PDT 24 |
47313250 ps |
| T1001 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.860768472 |
|
|
Jul 09 06:32:02 PM PDT 24 |
Jul 09 06:32:55 PM PDT 24 |
3806154019 ps |
| T1002 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.892350335 |
|
|
Jul 09 06:32:24 PM PDT 24 |
Jul 09 06:32:51 PM PDT 24 |
136564198 ps |
| T1003 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1189720885 |
|
|
Jul 09 06:31:55 PM PDT 24 |
Jul 09 06:32:20 PM PDT 24 |
426349485 ps |