Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	367840964	1			T1	346138		T3	432534		T4	130604
instr_valid_dis	319952092	1			T1	346138		T3	432534		T4	130604
instr_en	29347535	1			T10	233654		T6	244864		T7	297878

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	15975516	1			T10	55990		T6	157368		T7	48542
sram_ifetch_valid_disable	325913039	1			T1	346138		T3	432534		T4	130604
sram_ifetch_enable	25952409	1			T10	333196		T6	339698		T7	163864

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	367840964	1			T1	346138		T3	432534		T4	130604
hw_debug_en_valid_off	324155814	1			T1	346138		T3	432534		T4	130604
hw_debug_en_on	26618396	1			T10	275634		T6	402014		T7	87428

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	325913039	1			T1	346138		T3	432534		T4	130604
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	305410401	1			T1	346138		T3	432534		T4	130604
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	15001755	1			T10	65870		T6	50846		T7	148370
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	3487948	1			T10	32818		T6	56508		T7	15266
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1470682	1			T10	19152		T131	18160		T135	35076
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1316922	1			T10	13666		T6	1424		T7	15266
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	9610982	1			T10	7090		T6	49078		T17	18014
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1680482	1			T6	16922		T129	57766		T136	32816
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1582116	1			T10	7090		T6	10356		T17	18014
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	9024600	1			T10	76638		T6	143768		T7	24530
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	2959758	1			T10	29074		T20	9336		T129	15946
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	4175706	1			T10	47564		T6	12646		T7	24530

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	10761944	1			T10	147028		T6	182238		T7	100966
lc_exec_en	7982814	1			T10	191906		T6	209168		T7	62898
valid_exec_dis	320502752	1			T1	346138		T3	432534		T4	130604
invalid_exec_dis	41927925	1			T10	389186		T6	497066		T7	212406