Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	155322896	1			T1	157199		T3	39332		T4	3252
triple_byte_access	2873718	1			T1	3167		T3	35500		T4	7422
halfword_access	4418962	1			T1	4824		T3	53075		T4	13582
byte_access	6188006	1			T1	6305		T3	70849		T4	25978
zero_access	1888279	1			T1	1574		T3	17511		T4	15068

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

85107148

1

T1

86478

T3

107802

T4

32619

auto[1]

85584713

1

T1

86591

T3

108465

T4

32683

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	77284297	1			T1	78586		T3	19631		T4	249
auto[0]	triple_byte_access	1366831	1			T1	1532		T3	17740		T4	1436
auto[0]	halfword_access	2153106	1			T1	2349		T3	26506		T4	4751
auto[0]	byte_access	3168363	1			T1	3237		T3	35278		T4	14016
auto[0]	zero_access	1134551	1			T1	774		T3	8647		T4	12167
auto[1]	word_access	78038599	1			T1	78613		T3	19701		T4	3003
auto[1]	triple_byte_access	1506887	1			T1	1635		T3	17760		T4	5986
auto[1]	halfword_access	2265856	1			T1	2475		T3	26569		T4	8831
auto[1]	byte_access	3019643	1			T1	3068		T3	35571		T4	11962
auto[1]	zero_access	753728	1			T1	800		T3	8864		T4	2901