| T789 |
/workspace/coverage/default/27.sram_ctrl_multiple_keys.3880206228 |
|
|
Jul 10 06:32:29 PM PDT 24 |
Jul 10 06:45:43 PM PDT 24 |
10685103673 ps |
| T790 |
/workspace/coverage/default/13.sram_ctrl_mem_walk.354546251 |
|
|
Jul 10 06:31:03 PM PDT 24 |
Jul 10 06:36:53 PM PDT 24 |
66496216748 ps |
| T791 |
/workspace/coverage/default/45.sram_ctrl_ram_cfg.2246606982 |
|
|
Jul 10 06:35:29 PM PDT 24 |
Jul 10 06:35:34 PM PDT 24 |
2123521394 ps |
| T792 |
/workspace/coverage/default/17.sram_ctrl_mem_walk.3867515572 |
|
|
Jul 10 06:31:18 PM PDT 24 |
Jul 10 06:34:01 PM PDT 24 |
14146254909 ps |
| T793 |
/workspace/coverage/default/16.sram_ctrl_alert_test.3045323666 |
|
|
Jul 10 06:31:07 PM PDT 24 |
Jul 10 06:31:09 PM PDT 24 |
42484333 ps |
| T794 |
/workspace/coverage/default/40.sram_ctrl_multiple_keys.3994533557 |
|
|
Jul 10 06:34:35 PM PDT 24 |
Jul 10 06:47:38 PM PDT 24 |
15585380898 ps |
| T795 |
/workspace/coverage/default/17.sram_ctrl_smoke.2649634806 |
|
|
Jul 10 06:31:14 PM PDT 24 |
Jul 10 06:31:51 PM PDT 24 |
550274422 ps |
| T796 |
/workspace/coverage/default/4.sram_ctrl_executable.1141815469 |
|
|
Jul 10 06:30:26 PM PDT 24 |
Jul 10 06:36:34 PM PDT 24 |
11316447326 ps |
| T797 |
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.2408808108 |
|
|
Jul 10 06:35:51 PM PDT 24 |
Jul 10 06:42:12 PM PDT 24 |
13424171394 ps |
| T798 |
/workspace/coverage/default/31.sram_ctrl_stress_pipeline.4289779639 |
|
|
Jul 10 06:33:02 PM PDT 24 |
Jul 10 06:36:39 PM PDT 24 |
4071498171 ps |
| T799 |
/workspace/coverage/default/12.sram_ctrl_mem_walk.1177914731 |
|
|
Jul 10 06:30:53 PM PDT 24 |
Jul 10 06:36:12 PM PDT 24 |
53169985229 ps |
| T800 |
/workspace/coverage/default/36.sram_ctrl_stress_all.1326951615 |
|
|
Jul 10 06:34:00 PM PDT 24 |
Jul 10 07:14:41 PM PDT 24 |
114195063866 ps |
| T801 |
/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.1980848409 |
|
|
Jul 10 06:31:39 PM PDT 24 |
Jul 10 06:32:14 PM PDT 24 |
2693294409 ps |
| T802 |
/workspace/coverage/default/34.sram_ctrl_lc_escalation.845242244 |
|
|
Jul 10 06:33:41 PM PDT 24 |
Jul 10 06:35:47 PM PDT 24 |
280649072483 ps |
| T803 |
/workspace/coverage/default/24.sram_ctrl_bijection.2546154859 |
|
|
Jul 10 06:31:57 PM PDT 24 |
Jul 10 06:48:17 PM PDT 24 |
192089034495 ps |
| T804 |
/workspace/coverage/default/15.sram_ctrl_executable.2693517423 |
|
|
Jul 10 06:31:00 PM PDT 24 |
Jul 10 06:39:16 PM PDT 24 |
3921871422 ps |
| T805 |
/workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.3138213934 |
|
|
Jul 10 06:34:19 PM PDT 24 |
Jul 10 06:34:35 PM PDT 24 |
3188577190 ps |
| T806 |
/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.1192676334 |
|
|
Jul 10 06:33:54 PM PDT 24 |
Jul 10 06:43:31 PM PDT 24 |
45229183980 ps |
| T807 |
/workspace/coverage/default/14.sram_ctrl_mem_partial_access.534975256 |
|
|
Jul 10 06:30:59 PM PDT 24 |
Jul 10 06:33:25 PM PDT 24 |
17326914516 ps |
| T808 |
/workspace/coverage/default/37.sram_ctrl_mem_walk.3444926290 |
|
|
Jul 10 06:34:05 PM PDT 24 |
Jul 10 06:36:20 PM PDT 24 |
4202223508 ps |
| T809 |
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.3710538896 |
|
|
Jul 10 06:35:49 PM PDT 24 |
Jul 10 06:38:13 PM PDT 24 |
3127320901 ps |
| T810 |
/workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.3752174368 |
|
|
Jul 10 06:32:33 PM PDT 24 |
Jul 10 06:34:06 PM PDT 24 |
12909697994 ps |
| T811 |
/workspace/coverage/default/15.sram_ctrl_alert_test.2727767691 |
|
|
Jul 10 06:31:01 PM PDT 24 |
Jul 10 06:31:06 PM PDT 24 |
19069060 ps |
| T812 |
/workspace/coverage/default/41.sram_ctrl_smoke.1788404741 |
|
|
Jul 10 06:34:42 PM PDT 24 |
Jul 10 06:35:22 PM PDT 24 |
735428016 ps |
| T48 |
/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.4244104591 |
|
|
Jul 10 06:33:32 PM PDT 24 |
Jul 10 06:35:25 PM PDT 24 |
2633519448 ps |
| T813 |
/workspace/coverage/default/18.sram_ctrl_max_throughput.604806703 |
|
|
Jul 10 06:31:22 PM PDT 24 |
Jul 10 06:32:08 PM PDT 24 |
2949833089 ps |
| T814 |
/workspace/coverage/default/16.sram_ctrl_stress_all.3948257749 |
|
|
Jul 10 06:31:09 PM PDT 24 |
Jul 10 07:27:37 PM PDT 24 |
35454320896 ps |
| T815 |
/workspace/coverage/default/11.sram_ctrl_alert_test.3083027272 |
|
|
Jul 10 06:30:51 PM PDT 24 |
Jul 10 06:30:56 PM PDT 24 |
45798479 ps |
| T816 |
/workspace/coverage/default/28.sram_ctrl_stress_pipeline.3094003685 |
|
|
Jul 10 06:32:32 PM PDT 24 |
Jul 10 06:36:41 PM PDT 24 |
3745014010 ps |
| T817 |
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.3300950682 |
|
|
Jul 10 06:35:10 PM PDT 24 |
Jul 10 06:38:36 PM PDT 24 |
6446187237 ps |
| T818 |
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.2294107622 |
|
|
Jul 10 06:30:33 PM PDT 24 |
Jul 10 06:34:14 PM PDT 24 |
13429245412 ps |
| T819 |
/workspace/coverage/default/10.sram_ctrl_multiple_keys.3223301392 |
|
|
Jul 10 06:30:45 PM PDT 24 |
Jul 10 06:46:30 PM PDT 24 |
91134853725 ps |
| T820 |
/workspace/coverage/default/23.sram_ctrl_partial_access.3499597699 |
|
|
Jul 10 06:31:50 PM PDT 24 |
Jul 10 06:32:01 PM PDT 24 |
4080425383 ps |
| T821 |
/workspace/coverage/default/9.sram_ctrl_partial_access.798924870 |
|
|
Jul 10 06:30:39 PM PDT 24 |
Jul 10 06:32:06 PM PDT 24 |
4440776795 ps |
| T822 |
/workspace/coverage/default/25.sram_ctrl_mem_partial_access.3385252847 |
|
|
Jul 10 06:32:14 PM PDT 24 |
Jul 10 06:33:40 PM PDT 24 |
10926744007 ps |
| T823 |
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.1267374880 |
|
|
Jul 10 06:30:40 PM PDT 24 |
Jul 10 06:32:09 PM PDT 24 |
2788341002 ps |
| T824 |
/workspace/coverage/default/11.sram_ctrl_stress_all.1728349047 |
|
|
Jul 10 06:30:51 PM PDT 24 |
Jul 10 07:11:31 PM PDT 24 |
119466381171 ps |
| T825 |
/workspace/coverage/default/9.sram_ctrl_lc_escalation.2816745769 |
|
|
Jul 10 06:30:43 PM PDT 24 |
Jul 10 06:33:06 PM PDT 24 |
78265957327 ps |
| T826 |
/workspace/coverage/default/45.sram_ctrl_executable.2848235833 |
|
|
Jul 10 06:35:31 PM PDT 24 |
Jul 10 06:38:50 PM PDT 24 |
20685384649 ps |
| T827 |
/workspace/coverage/default/28.sram_ctrl_partial_access.3793938937 |
|
|
Jul 10 06:32:33 PM PDT 24 |
Jul 10 06:32:53 PM PDT 24 |
2698498300 ps |
| T828 |
/workspace/coverage/default/31.sram_ctrl_multiple_keys.1451932371 |
|
|
Jul 10 06:33:02 PM PDT 24 |
Jul 10 06:42:30 PM PDT 24 |
24331570475 ps |
| T829 |
/workspace/coverage/default/29.sram_ctrl_multiple_keys.1480007427 |
|
|
Jul 10 06:32:44 PM PDT 24 |
Jul 10 06:45:17 PM PDT 24 |
12803953825 ps |
| T830 |
/workspace/coverage/default/37.sram_ctrl_lc_escalation.3315681293 |
|
|
Jul 10 06:34:04 PM PDT 24 |
Jul 10 06:34:48 PM PDT 24 |
28452357993 ps |
| T831 |
/workspace/coverage/default/22.sram_ctrl_ram_cfg.358785382 |
|
|
Jul 10 06:31:45 PM PDT 24 |
Jul 10 06:31:49 PM PDT 24 |
681681161 ps |
| T832 |
/workspace/coverage/default/19.sram_ctrl_regwen.1973737135 |
|
|
Jul 10 06:31:29 PM PDT 24 |
Jul 10 06:37:54 PM PDT 24 |
10833892258 ps |
| T833 |
/workspace/coverage/default/41.sram_ctrl_mem_walk.2250145900 |
|
|
Jul 10 06:34:49 PM PDT 24 |
Jul 10 06:39:58 PM PDT 24 |
14393017371 ps |
| T834 |
/workspace/coverage/default/27.sram_ctrl_alert_test.1730098222 |
|
|
Jul 10 06:32:34 PM PDT 24 |
Jul 10 06:32:35 PM PDT 24 |
40907776 ps |
| T835 |
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.669475789 |
|
|
Jul 10 06:35:10 PM PDT 24 |
Jul 10 06:37:39 PM PDT 24 |
5309997262 ps |
| T836 |
/workspace/coverage/default/32.sram_ctrl_stress_all.391482117 |
|
|
Jul 10 06:33:20 PM PDT 24 |
Jul 10 07:36:57 PM PDT 24 |
33217634164 ps |
| T837 |
/workspace/coverage/default/33.sram_ctrl_multiple_keys.1967199061 |
|
|
Jul 10 06:33:28 PM PDT 24 |
Jul 10 06:37:41 PM PDT 24 |
26775944733 ps |
| T838 |
/workspace/coverage/default/23.sram_ctrl_ram_cfg.3168887382 |
|
|
Jul 10 06:31:51 PM PDT 24 |
Jul 10 06:31:56 PM PDT 24 |
702832587 ps |
| T839 |
/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.3906778442 |
|
|
Jul 10 06:32:50 PM PDT 24 |
Jul 10 06:33:55 PM PDT 24 |
3149304124 ps |
| T840 |
/workspace/coverage/default/23.sram_ctrl_executable.1955812645 |
|
|
Jul 10 06:31:55 PM PDT 24 |
Jul 10 06:45:25 PM PDT 24 |
32357646887 ps |
| T841 |
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.1862349665 |
|
|
Jul 10 06:31:03 PM PDT 24 |
Jul 10 06:54:13 PM PDT 24 |
52817479564 ps |
| T842 |
/workspace/coverage/default/20.sram_ctrl_alert_test.3603053834 |
|
|
Jul 10 06:31:38 PM PDT 24 |
Jul 10 06:31:40 PM PDT 24 |
64482454 ps |
| T843 |
/workspace/coverage/default/16.sram_ctrl_partial_access.3991997402 |
|
|
Jul 10 06:31:08 PM PDT 24 |
Jul 10 06:31:18 PM PDT 24 |
898251681 ps |
| T844 |
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2180347004 |
|
|
Jul 10 06:30:31 PM PDT 24 |
Jul 10 06:30:44 PM PDT 24 |
779751659 ps |
| T845 |
/workspace/coverage/default/13.sram_ctrl_executable.1528940578 |
|
|
Jul 10 06:30:56 PM PDT 24 |
Jul 10 06:51:28 PM PDT 24 |
61388106708 ps |
| T846 |
/workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.3800460379 |
|
|
Jul 10 06:31:15 PM PDT 24 |
Jul 10 06:31:43 PM PDT 24 |
4026276244 ps |
| T847 |
/workspace/coverage/default/5.sram_ctrl_multiple_keys.1200920983 |
|
|
Jul 10 06:30:27 PM PDT 24 |
Jul 10 06:42:38 PM PDT 24 |
40072325946 ps |
| T848 |
/workspace/coverage/default/28.sram_ctrl_executable.4022575048 |
|
|
Jul 10 06:32:40 PM PDT 24 |
Jul 10 06:33:27 PM PDT 24 |
3510969680 ps |
| T849 |
/workspace/coverage/default/25.sram_ctrl_smoke.2207676030 |
|
|
Jul 10 06:32:13 PM PDT 24 |
Jul 10 06:32:52 PM PDT 24 |
8550988528 ps |
| T850 |
/workspace/coverage/default/10.sram_ctrl_regwen.1068190424 |
|
|
Jul 10 06:30:47 PM PDT 24 |
Jul 10 06:37:55 PM PDT 24 |
6076495112 ps |
| T851 |
/workspace/coverage/default/17.sram_ctrl_alert_test.2642247747 |
|
|
Jul 10 06:31:15 PM PDT 24 |
Jul 10 06:31:17 PM PDT 24 |
55044473 ps |
| T852 |
/workspace/coverage/default/4.sram_ctrl_multiple_keys.1164047395 |
|
|
Jul 10 06:30:27 PM PDT 24 |
Jul 10 06:49:48 PM PDT 24 |
27944149363 ps |
| T853 |
/workspace/coverage/default/48.sram_ctrl_multiple_keys.2065735733 |
|
|
Jul 10 06:36:07 PM PDT 24 |
Jul 10 07:01:11 PM PDT 24 |
26648484028 ps |
| T854 |
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.3090033473 |
|
|
Jul 10 06:31:03 PM PDT 24 |
Jul 10 06:38:13 PM PDT 24 |
36525904018 ps |
| T855 |
/workspace/coverage/default/13.sram_ctrl_partial_access.2633692450 |
|
|
Jul 10 06:31:02 PM PDT 24 |
Jul 10 06:33:19 PM PDT 24 |
1081620608 ps |
| T856 |
/workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.2550376550 |
|
|
Jul 10 06:32:39 PM PDT 24 |
Jul 10 06:33:31 PM PDT 24 |
8572455993 ps |
| T857 |
/workspace/coverage/default/18.sram_ctrl_regwen.1932942387 |
|
|
Jul 10 06:31:20 PM PDT 24 |
Jul 10 06:31:57 PM PDT 24 |
539520286 ps |
| T858 |
/workspace/coverage/default/1.sram_ctrl_regwen.567806840 |
|
|
Jul 10 06:30:21 PM PDT 24 |
Jul 10 06:53:12 PM PDT 24 |
6705827328 ps |
| T859 |
/workspace/coverage/default/24.sram_ctrl_partial_access.2594904317 |
|
|
Jul 10 06:31:58 PM PDT 24 |
Jul 10 06:32:11 PM PDT 24 |
3880187203 ps |
| T860 |
/workspace/coverage/default/40.sram_ctrl_mem_partial_access.3401427075 |
|
|
Jul 10 06:34:44 PM PDT 24 |
Jul 10 06:37:15 PM PDT 24 |
7140349035 ps |
| T861 |
/workspace/coverage/default/43.sram_ctrl_ram_cfg.2403466715 |
|
|
Jul 10 06:35:11 PM PDT 24 |
Jul 10 06:35:16 PM PDT 24 |
353800665 ps |
| T862 |
/workspace/coverage/default/21.sram_ctrl_multiple_keys.515895246 |
|
|
Jul 10 06:31:40 PM PDT 24 |
Jul 10 06:56:54 PM PDT 24 |
43740337478 ps |
| T863 |
/workspace/coverage/default/10.sram_ctrl_mem_walk.3165148278 |
|
|
Jul 10 06:30:45 PM PDT 24 |
Jul 10 06:33:00 PM PDT 24 |
8229291615 ps |
| T864 |
/workspace/coverage/default/30.sram_ctrl_mem_walk.2082792258 |
|
|
Jul 10 06:33:00 PM PDT 24 |
Jul 10 06:35:20 PM PDT 24 |
17533537426 ps |
| T865 |
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.1300121936 |
|
|
Jul 10 06:36:13 PM PDT 24 |
Jul 10 06:37:18 PM PDT 24 |
3983786489 ps |
| T866 |
/workspace/coverage/default/3.sram_ctrl_executable.1315726451 |
|
|
Jul 10 06:30:22 PM PDT 24 |
Jul 10 06:45:11 PM PDT 24 |
16329722963 ps |
| T867 |
/workspace/coverage/default/19.sram_ctrl_mem_partial_access.550877131 |
|
|
Jul 10 06:31:28 PM PDT 24 |
Jul 10 06:34:18 PM PDT 24 |
24142198072 ps |
| T868 |
/workspace/coverage/default/8.sram_ctrl_partial_access.671229931 |
|
|
Jul 10 06:30:41 PM PDT 24 |
Jul 10 06:32:37 PM PDT 24 |
2744539987 ps |
| T869 |
/workspace/coverage/default/47.sram_ctrl_max_throughput.4233406209 |
|
|
Jul 10 06:35:50 PM PDT 24 |
Jul 10 06:35:57 PM PDT 24 |
4139175716 ps |
| T870 |
/workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.2006627795 |
|
|
Jul 10 06:30:58 PM PDT 24 |
Jul 10 06:31:08 PM PDT 24 |
211682080 ps |
| T871 |
/workspace/coverage/default/47.sram_ctrl_partial_access.3314381784 |
|
|
Jul 10 06:35:51 PM PDT 24 |
Jul 10 06:36:06 PM PDT 24 |
2695819869 ps |
| T872 |
/workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.1563604894 |
|
|
Jul 10 06:31:46 PM PDT 24 |
Jul 10 06:32:26 PM PDT 24 |
5233228158 ps |
| T873 |
/workspace/coverage/default/8.sram_ctrl_stress_all.3550173840 |
|
|
Jul 10 06:30:41 PM PDT 24 |
Jul 10 07:53:31 PM PDT 24 |
78184345641 ps |
| T874 |
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.504854248 |
|
|
Jul 10 06:36:08 PM PDT 24 |
Jul 10 06:39:21 PM PDT 24 |
6422405182 ps |
| T875 |
/workspace/coverage/default/36.sram_ctrl_max_throughput.4005387685 |
|
|
Jul 10 06:33:54 PM PDT 24 |
Jul 10 06:35:25 PM PDT 24 |
3192594442 ps |
| T876 |
/workspace/coverage/default/31.sram_ctrl_lc_escalation.792165992 |
|
|
Jul 10 06:33:10 PM PDT 24 |
Jul 10 06:33:39 PM PDT 24 |
19795062245 ps |
| T877 |
/workspace/coverage/default/16.sram_ctrl_mem_partial_access.3747438104 |
|
|
Jul 10 06:31:07 PM PDT 24 |
Jul 10 06:33:17 PM PDT 24 |
3311325719 ps |
| T878 |
/workspace/coverage/default/30.sram_ctrl_multiple_keys.4154956178 |
|
|
Jul 10 06:32:57 PM PDT 24 |
Jul 10 06:46:44 PM PDT 24 |
33803264065 ps |
| T879 |
/workspace/coverage/default/46.sram_ctrl_stress_all.3827618606 |
|
|
Jul 10 06:35:48 PM PDT 24 |
Jul 10 07:13:39 PM PDT 24 |
52678464240 ps |
| T880 |
/workspace/coverage/default/39.sram_ctrl_smoke.1175868247 |
|
|
Jul 10 06:34:17 PM PDT 24 |
Jul 10 06:34:28 PM PDT 24 |
3053548663 ps |
| T881 |
/workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.904438728 |
|
|
Jul 10 06:30:28 PM PDT 24 |
Jul 10 06:30:37 PM PDT 24 |
699703478 ps |
| T882 |
/workspace/coverage/default/4.sram_ctrl_mem_walk.1786372864 |
|
|
Jul 10 06:30:26 PM PDT 24 |
Jul 10 06:32:56 PM PDT 24 |
9358045055 ps |
| T883 |
/workspace/coverage/default/43.sram_ctrl_regwen.414370827 |
|
|
Jul 10 06:35:13 PM PDT 24 |
Jul 10 06:51:01 PM PDT 24 |
9770571454 ps |
| T884 |
/workspace/coverage/default/33.sram_ctrl_lc_escalation.1832415344 |
|
|
Jul 10 06:33:28 PM PDT 24 |
Jul 10 06:34:14 PM PDT 24 |
28975560956 ps |
| T885 |
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.2702264100 |
|
|
Jul 10 06:35:52 PM PDT 24 |
Jul 10 06:40:47 PM PDT 24 |
22705343554 ps |
| T886 |
/workspace/coverage/default/41.sram_ctrl_max_throughput.886383622 |
|
|
Jul 10 06:34:49 PM PDT 24 |
Jul 10 06:34:56 PM PDT 24 |
686384132 ps |
| T887 |
/workspace/coverage/default/35.sram_ctrl_multiple_keys.3712749202 |
|
|
Jul 10 06:33:50 PM PDT 24 |
Jul 10 06:45:12 PM PDT 24 |
10404420979 ps |
| T888 |
/workspace/coverage/default/30.sram_ctrl_smoke.764104007 |
|
|
Jul 10 06:32:55 PM PDT 24 |
Jul 10 06:35:22 PM PDT 24 |
947543316 ps |
| T889 |
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.3596460369 |
|
|
Jul 10 06:30:45 PM PDT 24 |
Jul 10 06:35:14 PM PDT 24 |
4549605017 ps |
| T890 |
/workspace/coverage/default/8.sram_ctrl_multiple_keys.1279124946 |
|
|
Jul 10 06:30:40 PM PDT 24 |
Jul 10 06:34:59 PM PDT 24 |
9330835220 ps |
| T891 |
/workspace/coverage/default/39.sram_ctrl_regwen.3275820258 |
|
|
Jul 10 06:34:24 PM PDT 24 |
Jul 10 07:03:15 PM PDT 24 |
164500933148 ps |
| T892 |
/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.2928410331 |
|
|
Jul 10 06:34:52 PM PDT 24 |
Jul 10 06:41:11 PM PDT 24 |
20752432582 ps |
| T893 |
/workspace/coverage/default/6.sram_ctrl_bijection.2310719252 |
|
|
Jul 10 06:30:33 PM PDT 24 |
Jul 10 06:47:15 PM PDT 24 |
15759418235 ps |
| T894 |
/workspace/coverage/default/43.sram_ctrl_max_throughput.1325564684 |
|
|
Jul 10 06:35:03 PM PDT 24 |
Jul 10 06:35:12 PM PDT 24 |
2703290297 ps |
| T895 |
/workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.645478439 |
|
|
Jul 10 06:34:23 PM PDT 24 |
Jul 10 06:37:12 PM PDT 24 |
1213572998 ps |
| T896 |
/workspace/coverage/default/13.sram_ctrl_mem_partial_access.2335599505 |
|
|
Jul 10 06:30:51 PM PDT 24 |
Jul 10 06:33:56 PM PDT 24 |
27854976928 ps |
| T897 |
/workspace/coverage/default/39.sram_ctrl_ram_cfg.3300448515 |
|
|
Jul 10 06:34:35 PM PDT 24 |
Jul 10 06:34:47 PM PDT 24 |
707797854 ps |
| T898 |
/workspace/coverage/default/8.sram_ctrl_ram_cfg.334145475 |
|
|
Jul 10 06:30:40 PM PDT 24 |
Jul 10 06:30:45 PM PDT 24 |
1348751359 ps |
| T899 |
/workspace/coverage/default/40.sram_ctrl_access_during_key_req.3794865259 |
|
|
Jul 10 06:34:45 PM PDT 24 |
Jul 10 06:44:40 PM PDT 24 |
45508366022 ps |
| T900 |
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.1614886693 |
|
|
Jul 10 06:30:45 PM PDT 24 |
Jul 10 06:44:03 PM PDT 24 |
52766245090 ps |
| T901 |
/workspace/coverage/default/37.sram_ctrl_executable.4145909367 |
|
|
Jul 10 06:34:05 PM PDT 24 |
Jul 10 06:48:12 PM PDT 24 |
14719955173 ps |
| T902 |
/workspace/coverage/default/18.sram_ctrl_stress_pipeline.1227434732 |
|
|
Jul 10 06:31:16 PM PDT 24 |
Jul 10 06:34:30 PM PDT 24 |
3010740994 ps |
| T903 |
/workspace/coverage/default/18.sram_ctrl_mem_walk.2884272875 |
|
|
Jul 10 06:31:21 PM PDT 24 |
Jul 10 06:36:58 PM PDT 24 |
38473095040 ps |
| T904 |
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.825268846 |
|
|
Jul 10 06:30:17 PM PDT 24 |
Jul 10 06:31:32 PM PDT 24 |
2822800648 ps |
| T905 |
/workspace/coverage/default/27.sram_ctrl_access_during_key_req.2604679332 |
|
|
Jul 10 06:32:35 PM PDT 24 |
Jul 10 06:57:23 PM PDT 24 |
150518536650 ps |
| T906 |
/workspace/coverage/default/14.sram_ctrl_stress_pipeline.475593887 |
|
|
Jul 10 06:31:02 PM PDT 24 |
Jul 10 06:34:54 PM PDT 24 |
3361377208 ps |
| T907 |
/workspace/coverage/default/43.sram_ctrl_multiple_keys.2864281995 |
|
|
Jul 10 06:35:01 PM PDT 24 |
Jul 10 06:53:47 PM PDT 24 |
119969033801 ps |
| T908 |
/workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.3956405946 |
|
|
Jul 10 06:33:07 PM PDT 24 |
Jul 10 06:34:01 PM PDT 24 |
3054527269 ps |
| T909 |
/workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.733773100 |
|
|
Jul 10 06:32:51 PM PDT 24 |
Jul 10 06:33:22 PM PDT 24 |
1266670061 ps |
| T910 |
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.1536099231 |
|
|
Jul 10 06:35:43 PM PDT 24 |
Jul 10 06:35:57 PM PDT 24 |
1581362624 ps |
| T911 |
/workspace/coverage/default/38.sram_ctrl_multiple_keys.370125307 |
|
|
Jul 10 06:34:12 PM PDT 24 |
Jul 10 06:55:18 PM PDT 24 |
68369805605 ps |
| T912 |
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.1430287521 |
|
|
Jul 10 06:30:47 PM PDT 24 |
Jul 10 06:34:10 PM PDT 24 |
28735600575 ps |
| T913 |
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.2438961450 |
|
|
Jul 10 06:30:21 PM PDT 24 |
Jul 10 06:45:03 PM PDT 24 |
41853015020 ps |
| T914 |
/workspace/coverage/default/16.sram_ctrl_mem_walk.4113800129 |
|
|
Jul 10 06:31:07 PM PDT 24 |
Jul 10 06:36:32 PM PDT 24 |
13821446516 ps |
| T915 |
/workspace/coverage/default/16.sram_ctrl_stress_pipeline.383342044 |
|
|
Jul 10 06:31:09 PM PDT 24 |
Jul 10 06:34:46 PM PDT 24 |
3122102787 ps |
| T916 |
/workspace/coverage/default/47.sram_ctrl_mem_walk.1518065259 |
|
|
Jul 10 06:35:51 PM PDT 24 |
Jul 10 06:41:06 PM PDT 24 |
14554543020 ps |
| T917 |
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.476154992 |
|
|
Jul 10 06:30:43 PM PDT 24 |
Jul 10 06:33:16 PM PDT 24 |
2534567265 ps |
| T918 |
/workspace/coverage/default/36.sram_ctrl_regwen.3323803643 |
|
|
Jul 10 06:33:59 PM PDT 24 |
Jul 10 06:55:55 PM PDT 24 |
10493864225 ps |
| T919 |
/workspace/coverage/default/18.sram_ctrl_access_during_key_req.2463741976 |
|
|
Jul 10 06:31:21 PM PDT 24 |
Jul 10 06:42:10 PM PDT 24 |
43622118104 ps |
| T920 |
/workspace/coverage/default/6.sram_ctrl_lc_escalation.74376451 |
|
|
Jul 10 06:30:32 PM PDT 24 |
Jul 10 06:31:54 PM PDT 24 |
26741161431 ps |
| T921 |
/workspace/coverage/default/42.sram_ctrl_multiple_keys.1146165052 |
|
|
Jul 10 06:34:53 PM PDT 24 |
Jul 10 06:51:40 PM PDT 24 |
153731862370 ps |
| T922 |
/workspace/coverage/default/34.sram_ctrl_alert_test.1457369129 |
|
|
Jul 10 06:33:50 PM PDT 24 |
Jul 10 06:33:53 PM PDT 24 |
35655033 ps |
| T923 |
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.3634971691 |
|
|
Jul 10 06:35:29 PM PDT 24 |
Jul 10 06:36:42 PM PDT 24 |
13615915213 ps |
| T924 |
/workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.3914232485 |
|
|
Jul 10 06:30:56 PM PDT 24 |
Jul 10 06:31:34 PM PDT 24 |
2170116335 ps |
| T925 |
/workspace/coverage/default/42.sram_ctrl_regwen.3905076755 |
|
|
Jul 10 06:34:56 PM PDT 24 |
Jul 10 06:39:59 PM PDT 24 |
14217867018 ps |
| T926 |
/workspace/coverage/default/37.sram_ctrl_partial_access.3373344862 |
|
|
Jul 10 06:33:58 PM PDT 24 |
Jul 10 06:34:13 PM PDT 24 |
796758284 ps |
| T927 |
/workspace/coverage/default/10.sram_ctrl_bijection.3222889673 |
|
|
Jul 10 06:30:48 PM PDT 24 |
Jul 10 06:45:21 PM PDT 24 |
12143394722 ps |
| T928 |
/workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.3964578123 |
|
|
Jul 10 06:31:28 PM PDT 24 |
Jul 10 06:32:32 PM PDT 24 |
2101232400 ps |
| T929 |
/workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.205506747 |
|
|
Jul 10 06:31:08 PM PDT 24 |
Jul 10 06:31:19 PM PDT 24 |
299166219 ps |
| T930 |
/workspace/coverage/default/46.sram_ctrl_mem_walk.944370943 |
|
|
Jul 10 06:35:44 PM PDT 24 |
Jul 10 06:38:18 PM PDT 24 |
10517636597 ps |
| T931 |
/workspace/coverage/default/15.sram_ctrl_lc_escalation.2813776238 |
|
|
Jul 10 06:31:00 PM PDT 24 |
Jul 10 06:32:37 PM PDT 24 |
138969464448 ps |
| T932 |
/workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.1870139783 |
|
|
Jul 10 06:34:13 PM PDT 24 |
Jul 10 06:35:11 PM PDT 24 |
5560727427 ps |
| T933 |
/workspace/coverage/default/3.sram_ctrl_bijection.4030727167 |
|
|
Jul 10 06:30:24 PM PDT 24 |
Jul 10 06:50:24 PM PDT 24 |
138328442619 ps |
| T934 |
/workspace/coverage/default/6.sram_ctrl_partial_access.4092833619 |
|
|
Jul 10 06:30:36 PM PDT 24 |
Jul 10 06:30:42 PM PDT 24 |
4238429474 ps |
| T935 |
/workspace/coverage/default/15.sram_ctrl_stress_all.2712990145 |
|
|
Jul 10 06:31:00 PM PDT 24 |
Jul 10 07:18:42 PM PDT 24 |
154982143105 ps |
| T936 |
/workspace/coverage/default/47.sram_ctrl_stress_all.2715018758 |
|
|
Jul 10 06:36:05 PM PDT 24 |
Jul 10 06:40:54 PM PDT 24 |
28543128933 ps |
| T937 |
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.2858602662 |
|
|
Jul 10 06:34:59 PM PDT 24 |
Jul 10 06:35:10 PM PDT 24 |
273713508 ps |
| T938 |
/workspace/coverage/default/48.sram_ctrl_bijection.3187696674 |
|
|
Jul 10 06:36:06 PM PDT 24 |
Jul 10 07:05:35 PM PDT 24 |
179707518711 ps |
| T939 |
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.2402588342 |
|
|
Jul 10 06:30:28 PM PDT 24 |
Jul 10 06:35:36 PM PDT 24 |
9377812433 ps |
| T68 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2581749101 |
|
|
Jul 10 06:28:35 PM PDT 24 |
Jul 10 06:28:38 PM PDT 24 |
22647544 ps |
| T69 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3361271540 |
|
|
Jul 10 06:28:35 PM PDT 24 |
Jul 10 06:28:37 PM PDT 24 |
104549448 ps |
| T70 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3638230501 |
|
|
Jul 10 06:28:17 PM PDT 24 |
Jul 10 06:28:47 PM PDT 24 |
7127167324 ps |
| T79 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.25241445 |
|
|
Jul 10 06:28:29 PM PDT 24 |
Jul 10 06:28:30 PM PDT 24 |
49276080 ps |
| T80 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.975569586 |
|
|
Jul 10 06:27:47 PM PDT 24 |
Jul 10 06:28:36 PM PDT 24 |
29346325865 ps |
| T81 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.713215510 |
|
|
Jul 10 06:28:35 PM PDT 24 |
Jul 10 06:29:24 PM PDT 24 |
19354769780 ps |
| T65 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.631693074 |
|
|
Jul 10 06:27:58 PM PDT 24 |
Jul 10 06:28:03 PM PDT 24 |
752975009 ps |
| T82 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1842336137 |
|
|
Jul 10 06:28:18 PM PDT 24 |
Jul 10 06:29:05 PM PDT 24 |
7328829467 ps |
| T83 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2917610867 |
|
|
Jul 10 06:28:28 PM PDT 24 |
Jul 10 06:28:29 PM PDT 24 |
18965026 ps |
| T66 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2602419896 |
|
|
Jul 10 06:27:41 PM PDT 24 |
Jul 10 06:27:43 PM PDT 24 |
743301594 ps |
| T84 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.759213207 |
|
|
Jul 10 06:28:27 PM PDT 24 |
Jul 10 06:28:54 PM PDT 24 |
3699474811 ps |
| T85 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2688896559 |
|
|
Jul 10 06:28:04 PM PDT 24 |
Jul 10 06:28:06 PM PDT 24 |
15194471 ps |
| T86 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.347345764 |
|
|
Jul 10 06:28:14 PM PDT 24 |
Jul 10 06:28:15 PM PDT 24 |
37284852 ps |
| T940 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1232040860 |
|
|
Jul 10 06:27:53 PM PDT 24 |
Jul 10 06:27:57 PM PDT 24 |
697658105 ps |
| T941 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.436691082 |
|
|
Jul 10 06:28:30 PM PDT 24 |
Jul 10 06:28:32 PM PDT 24 |
24426970 ps |
| T942 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.588660189 |
|
|
Jul 10 06:28:17 PM PDT 24 |
Jul 10 06:28:18 PM PDT 24 |
41376900 ps |
| T108 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3010282505 |
|
|
Jul 10 06:28:06 PM PDT 24 |
Jul 10 06:28:07 PM PDT 24 |
47894525 ps |
| T88 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2650873424 |
|
|
Jul 10 06:28:11 PM PDT 24 |
Jul 10 06:28:40 PM PDT 24 |
3792017410 ps |
| T89 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2819116201 |
|
|
Jul 10 06:28:05 PM PDT 24 |
Jul 10 06:28:53 PM PDT 24 |
7047393499 ps |
| T943 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.877438506 |
|
|
Jul 10 06:28:28 PM PDT 24 |
Jul 10 06:28:33 PM PDT 24 |
1391420959 ps |
| T944 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2564150296 |
|
|
Jul 10 06:28:16 PM PDT 24 |
Jul 10 06:28:17 PM PDT 24 |
36268867 ps |
| T945 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.486885625 |
|
|
Jul 10 06:28:11 PM PDT 24 |
Jul 10 06:28:15 PM PDT 24 |
345198739 ps |
| T946 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2668783667 |
|
|
Jul 10 06:28:10 PM PDT 24 |
Jul 10 06:28:11 PM PDT 24 |
35624559 ps |
| T947 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.4157259987 |
|
|
Jul 10 06:28:18 PM PDT 24 |
Jul 10 06:28:23 PM PDT 24 |
1384073935 ps |
| T948 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.4148221822 |
|
|
Jul 10 06:27:57 PM PDT 24 |
Jul 10 06:27:59 PM PDT 24 |
141864498 ps |
| T949 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1344747245 |
|
|
Jul 10 06:28:12 PM PDT 24 |
Jul 10 06:28:14 PM PDT 24 |
26382736 ps |
| T67 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3552605403 |
|
|
Jul 10 06:28:10 PM PDT 24 |
Jul 10 06:28:14 PM PDT 24 |
722375353 ps |
| T950 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3311380687 |
|
|
Jul 10 06:27:41 PM PDT 24 |
Jul 10 06:27:45 PM PDT 24 |
101400683 ps |
| T951 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.46562691 |
|
|
Jul 10 06:28:30 PM PDT 24 |
Jul 10 06:28:32 PM PDT 24 |
15420318 ps |
| T952 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2656768295 |
|
|
Jul 10 06:27:52 PM PDT 24 |
Jul 10 06:27:53 PM PDT 24 |
35007283 ps |
| T118 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2653461085 |
|
|
Jul 10 06:28:10 PM PDT 24 |
Jul 10 06:28:14 PM PDT 24 |
252958391 ps |
| T90 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2365977275 |
|
|
Jul 10 06:28:06 PM PDT 24 |
Jul 10 06:28:32 PM PDT 24 |
3770822265 ps |
| T953 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3659590413 |
|
|
Jul 10 06:28:17 PM PDT 24 |
Jul 10 06:28:19 PM PDT 24 |
16287801 ps |
| T954 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3594387773 |
|
|
Jul 10 06:28:34 PM PDT 24 |
Jul 10 06:28:36 PM PDT 24 |
79435177 ps |
| T955 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.648638710 |
|
|
Jul 10 06:28:04 PM PDT 24 |
Jul 10 06:28:07 PM PDT 24 |
128082387 ps |
| T956 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.4111222256 |
|
|
Jul 10 06:28:31 PM PDT 24 |
Jul 10 06:28:34 PM PDT 24 |
77554078 ps |
| T957 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1169673043 |
|
|
Jul 10 06:28:29 PM PDT 24 |
Jul 10 06:28:32 PM PDT 24 |
155841134 ps |
| T958 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.34592727 |
|
|
Jul 10 06:28:17 PM PDT 24 |
Jul 10 06:28:19 PM PDT 24 |
13982407 ps |
| T959 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3951641291 |
|
|
Jul 10 06:27:59 PM PDT 24 |
Jul 10 06:28:04 PM PDT 24 |
369276287 ps |
| T91 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1306433518 |
|
|
Jul 10 06:28:18 PM PDT 24 |
Jul 10 06:28:47 PM PDT 24 |
6501348872 ps |
| T960 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.127584907 |
|
|
Jul 10 06:28:31 PM PDT 24 |
Jul 10 06:28:34 PM PDT 24 |
18313433 ps |
| T961 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2576185176 |
|
|
Jul 10 06:28:28 PM PDT 24 |
Jul 10 06:28:32 PM PDT 24 |
1455804561 ps |
| T962 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3356397973 |
|
|
Jul 10 06:28:20 PM PDT 24 |
Jul 10 06:28:21 PM PDT 24 |
17809675 ps |
| T98 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.4143061019 |
|
|
Jul 10 06:27:42 PM PDT 24 |
Jul 10 06:27:43 PM PDT 24 |
42978758 ps |
| T963 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2564025125 |
|
|
Jul 10 06:28:36 PM PDT 24 |
Jul 10 06:28:40 PM PDT 24 |
389120916 ps |
| T964 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1540369964 |
|
|
Jul 10 06:27:43 PM PDT 24 |
Jul 10 06:27:45 PM PDT 24 |
346235502 ps |
| T121 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3527913461 |
|
|
Jul 10 06:28:16 PM PDT 24 |
Jul 10 06:28:19 PM PDT 24 |
315723785 ps |
| T965 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3236833930 |
|
|
Jul 10 06:27:36 PM PDT 24 |
Jul 10 06:27:38 PM PDT 24 |
17761945 ps |
| T119 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1049281164 |
|
|
Jul 10 06:28:16 PM PDT 24 |
Jul 10 06:28:19 PM PDT 24 |
250726038 ps |
| T966 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2841907107 |
|
|
Jul 10 06:28:30 PM PDT 24 |
Jul 10 06:28:35 PM PDT 24 |
1365958900 ps |
| T99 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3674433884 |
|
|
Jul 10 06:27:47 PM PDT 24 |
Jul 10 06:28:43 PM PDT 24 |
7058074245 ps |
| T967 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3315900040 |
|
|
Jul 10 06:28:35 PM PDT 24 |
Jul 10 06:28:41 PM PDT 24 |
849653368 ps |
| T968 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3244932426 |
|
|
Jul 10 06:28:11 PM PDT 24 |
Jul 10 06:28:16 PM PDT 24 |
134203157 ps |
| T969 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3050403082 |
|
|
Jul 10 06:28:17 PM PDT 24 |
Jul 10 06:28:22 PM PDT 24 |
744836095 ps |
| T970 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3397883506 |
|
|
Jul 10 06:27:57 PM PDT 24 |
Jul 10 06:28:02 PM PDT 24 |
363782645 ps |
| T120 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.4188655981 |
|
|
Jul 10 06:28:36 PM PDT 24 |
Jul 10 06:28:40 PM PDT 24 |
483125992 ps |
| T971 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.473699674 |
|
|
Jul 10 06:28:05 PM PDT 24 |
Jul 10 06:28:07 PM PDT 24 |
77554664 ps |
| T972 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3186995340 |
|
|
Jul 10 06:28:30 PM PDT 24 |
Jul 10 06:28:34 PM PDT 24 |
65400628 ps |
| T973 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1244634194 |
|
|
Jul 10 06:28:29 PM PDT 24 |
Jul 10 06:29:02 PM PDT 24 |
17568720499 ps |
| T974 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1908743490 |
|
|
Jul 10 06:27:42 PM PDT 24 |
Jul 10 06:28:12 PM PDT 24 |
7554377104 ps |
| T975 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2251566827 |
|
|
Jul 10 06:28:17 PM PDT 24 |
Jul 10 06:28:22 PM PDT 24 |
2307434039 ps |
| T976 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3543198248 |
|
|
Jul 10 06:28:29 PM PDT 24 |
Jul 10 06:28:33 PM PDT 24 |
705730077 ps |
| T977 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.929151835 |
|
|
Jul 10 06:28:35 PM PDT 24 |
Jul 10 06:28:36 PM PDT 24 |
12415497 ps |
| T100 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1072054147 |
|
|
Jul 10 06:28:36 PM PDT 24 |
Jul 10 06:29:05 PM PDT 24 |
3738479312 ps |
| T978 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.231080842 |
|
|
Jul 10 06:28:04 PM PDT 24 |
Jul 10 06:28:05 PM PDT 24 |
21680901 ps |
| T979 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2081682109 |
|
|
Jul 10 06:28:12 PM PDT 24 |
Jul 10 06:28:17 PM PDT 24 |
3888178308 ps |
| T980 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1539865947 |
|
|
Jul 10 06:28:29 PM PDT 24 |
Jul 10 06:28:31 PM PDT 24 |
65071841 ps |
| T126 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.4152864254 |
|
|
Jul 10 06:28:29 PM PDT 24 |
Jul 10 06:28:31 PM PDT 24 |
188219327 ps |
| T981 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2529401052 |
|
|
Jul 10 06:28:37 PM PDT 24 |
Jul 10 06:28:42 PM PDT 24 |
373675261 ps |
| T101 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2451179008 |
|
|
Jul 10 06:27:59 PM PDT 24 |
Jul 10 06:28:27 PM PDT 24 |
3735429033 ps |
| T982 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1298135813 |
|
|
Jul 10 06:27:30 PM PDT 24 |
Jul 10 06:27:33 PM PDT 24 |
305443062 ps |
| T983 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1906538012 |
|
|
Jul 10 06:28:10 PM PDT 24 |
Jul 10 06:28:39 PM PDT 24 |
14223537787 ps |
| T984 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1446664500 |
|
|
Jul 10 06:28:03 PM PDT 24 |
Jul 10 06:28:06 PM PDT 24 |
121013440 ps |
| T102 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2926737208 |
|
|
Jul 10 06:27:39 PM PDT 24 |
Jul 10 06:27:41 PM PDT 24 |
25222829 ps |
| T103 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1322159011 |
|
|
Jul 10 06:27:59 PM PDT 24 |
Jul 10 06:28:01 PM PDT 24 |
22073843 ps |
| T985 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3883771988 |
|
|
Jul 10 06:28:28 PM PDT 24 |
Jul 10 06:28:30 PM PDT 24 |
33778180 ps |
| T986 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1880139881 |
|
|
Jul 10 06:27:48 PM PDT 24 |
Jul 10 06:27:53 PM PDT 24 |
117287266 ps |
| T987 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.716339557 |
|
|
Jul 10 06:28:36 PM PDT 24 |
Jul 10 06:28:39 PM PDT 24 |
22131502 ps |
| T988 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.4179637280 |
|
|
Jul 10 06:28:29 PM PDT 24 |
Jul 10 06:28:34 PM PDT 24 |
2874024175 ps |
| T989 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2364703012 |
|
|
Jul 10 06:28:16 PM PDT 24 |
Jul 10 06:28:20 PM PDT 24 |
43131910 ps |
| T990 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1818510010 |
|
|
Jul 10 06:27:47 PM PDT 24 |
Jul 10 06:27:51 PM PDT 24 |
360112998 ps |
| T991 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.951279249 |
|
|
Jul 10 06:27:47 PM PDT 24 |
Jul 10 06:27:48 PM PDT 24 |
34520422 ps |
| T992 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.290122466 |
|
|
Jul 10 06:27:59 PM PDT 24 |
Jul 10 06:28:01 PM PDT 24 |
21077703 ps |
| T127 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.4130589622 |
|
|
Jul 10 06:28:03 PM PDT 24 |
Jul 10 06:28:06 PM PDT 24 |
691109313 ps |
| T993 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2762887252 |
|
|
Jul 10 06:28:18 PM PDT 24 |
Jul 10 06:28:23 PM PDT 24 |
52755424 ps |
| T994 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1177733264 |
|
|
Jul 10 06:28:05 PM PDT 24 |
Jul 10 06:28:06 PM PDT 24 |
35951186 ps |
| T995 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.4123656579 |
|
|
Jul 10 06:28:37 PM PDT 24 |
Jul 10 06:28:43 PM PDT 24 |
373476887 ps |
| T996 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.847778854 |
|
|
Jul 10 06:28:30 PM PDT 24 |
Jul 10 06:28:36 PM PDT 24 |
130267364 ps |
| T997 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3355648288 |
|
|
Jul 10 06:28:31 PM PDT 24 |
Jul 10 06:28:38 PM PDT 24 |
141210857 ps |
| T122 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1468272696 |
|
|
Jul 10 06:27:45 PM PDT 24 |
Jul 10 06:27:48 PM PDT 24 |
684320869 ps |
| T998 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.956328380 |
|
|
Jul 10 06:28:28 PM PDT 24 |
Jul 10 06:28:33 PM PDT 24 |
1336395581 ps |
| T999 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.351518582 |
|
|
Jul 10 06:27:47 PM PDT 24 |
Jul 10 06:27:49 PM PDT 24 |
36010758 ps |
| T104 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1369956016 |
|
|
Jul 10 06:27:47 PM PDT 24 |
Jul 10 06:27:49 PM PDT 24 |
39296737 ps |
| T1000 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.267934339 |
|
|
Jul 10 06:28:12 PM PDT 24 |
Jul 10 06:28:14 PM PDT 24 |
103123018 ps |
| T1001 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.4152140776 |
|
|
Jul 10 06:27:48 PM PDT 24 |
Jul 10 06:27:50 PM PDT 24 |
17803818 ps |
| T124 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3788964027 |
|
|
Jul 10 06:28:15 PM PDT 24 |
Jul 10 06:28:17 PM PDT 24 |
275403521 ps |
| T105 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1884744663 |
|
|
Jul 10 06:27:32 PM PDT 24 |
Jul 10 06:28:26 PM PDT 24 |
14649911730 ps |
| T1002 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1682664355 |
|
|
Jul 10 06:28:35 PM PDT 24 |
Jul 10 06:28:41 PM PDT 24 |
150232616 ps |