SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[sram_ctrl_prim_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[sram_ctrl_regs_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[0]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[1] | 166440483 | 0 | T1 | 26654 | T2 | 215382 | T3 | 60772 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 166440279 | 1 | T1 | 26654 | T2 | 215382 | T3 | 60772 | ||||
values[1] | 21 | 1 | T61 | 3 | T63 | 1 | T146 | 1 | ||||
values[2] | 5 | 1 | T62 | 1 | T63 | 1 | T147 | 1 | ||||
values[3] | 100 | 1 | T61 | 3 | T62 | 5 | T63 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 166440282 | 1 | T1 | 26654 | T2 | 215382 | T3 | 60772 | ||||
values[1] | 20 | 1 | T61 | 1 | T62 | 1 | T63 | 1 | ||||
values[2] | 4 | 1 | T63 | 1 | T148 | 1 | T149 | 1 | ||||
values[3] | 107 | 1 | T61 | 5 | T62 | 1 | T63 | 10 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 166440173 | 1 | T1 | 26654 | T2 | 215382 | T3 | 60772 | ||||
auto[TlIntgErrCmd] | 109 | 1 | T61 | 10 | T62 | 2 | T63 | 4 | ||||
auto[TlIntgErrData] | 106 | 1 | T61 | 7 | T62 | 3 | T63 | 8 | ||||
auto[TlIntgErrBoth] | 95 | 1 | T61 | 3 | T62 | 5 | T63 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[0] | 504011 | 0 | T1 | 8 | T2 | 108 | T3 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 503808 | 1 | T1 | 8 | T2 | 108 | T3 | 3 | ||||
values[1] | 14 | 1 | T61 | 1 | T150 | 2 | T151 | 1 | ||||
values[2] | 6 | 1 | T61 | 1 | T63 | 1 | T150 | 1 | ||||
values[3] | 112 | 1 | T61 | 6 | T62 | 5 | T63 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 503811 | 1 | T1 | 8 | T2 | 108 | T3 | 3 | ||||
values[1] | 16 | 1 | T63 | 2 | T148 | 1 | T146 | 1 | ||||
values[2] | 10 | 1 | T63 | 1 | T148 | 1 | T146 | 1 | ||||
values[3] | 90 | 1 | T61 | 5 | T62 | 3 | T63 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 503701 | 1 | T1 | 8 | T2 | 108 | T3 | 3 | ||||
auto[TlIntgErrCmd] | 110 | 1 | T61 | 10 | T62 | 5 | T63 | 8 | ||||
auto[TlIntgErrData] | 107 | 1 | T61 | 6 | T62 | 2 | T63 | 8 | ||||
auto[TlIntgErrBoth] | 93 | 1 | T61 | 4 | T62 | 3 | T63 | 4 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |