Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16119228	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

153276425

1

T1

28213

T2

209450

T3

3048

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	83250104	1			T1	15536		T2	114683		T3	30208
values[0x0]	41466046	1			T1	7520		T2	55772		T3	9778
values[0x1]	44679503	1			T1	7975		T2	59763		T3	20786

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8198724	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

161196929

1

T1

29645

T2

219932

T3

27471

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	556687	1			T1	172		T2	896		T3	231
valid_sources[0x01]	582004	1			T1	96		T2	880		T3	222
valid_sources[0x02]	548218	1			T1	108		T2	860		T3	234
valid_sources[0x03]	637192	1			T1	94		T2	980		T3	222
valid_sources[0x04]	580014	1			T1	87		T2	927		T3	216
valid_sources[0x05]	577822	1			T1	128		T2	913		T3	236
valid_sources[0x06]	540830	1			T1	109		T2	826		T3	235
valid_sources[0x07]	597287	1			T1	105		T2	1012		T3	222
valid_sources[0x08]	540075	1			T1	102		T2	971		T3	257
valid_sources[0x09]	552827	1			T1	84		T2	824		T3	283
valid_sources[0x0a]	613027	1			T1	127		T2	965		T3	281
valid_sources[0x0b]	571340	1			T1	150		T2	938		T3	245
valid_sources[0x0c]	564869	1			T1	166		T2	851		T3	246
valid_sources[0x0d]	534657	1			T1	107		T2	836		T3	231
valid_sources[0x0e]	1389894	1			T1	113		T2	919		T3	270
valid_sources[0x0f]	554339	1			T1	114		T2	876		T3	214
valid_sources[0x10]	573939	1			T1	120		T2	902		T3	265
valid_sources[0x11]	589556	1			T1	133		T2	931		T3	265
valid_sources[0x12]	546973	1			T1	99		T2	871		T3	240
valid_sources[0x13]	562961	1			T1	146		T2	843		T3	230
valid_sources[0x14]	588668	1			T1	118		T2	865		T3	258
valid_sources[0x15]	571210	1			T1	146		T2	919		T3	235
valid_sources[0x16]	538649	1			T1	174		T2	890		T3	259
valid_sources[0x17]	543528	1			T1	131		T2	927		T3	259
valid_sources[0x18]	562773	1			T1	136		T2	840		T3	238
valid_sources[0x19]	596570	1			T1	96		T2	971		T3	243
valid_sources[0x1a]	552513	1			T1	118		T2	966		T3	257
valid_sources[0x1b]	540897	1			T1	155		T2	945		T3	271
valid_sources[0x1c]	560324	1			T1	129		T2	917		T3	208
valid_sources[0x1d]	580695	1			T1	132		T2	812		T3	228
valid_sources[0x1e]	535707	1			T1	114		T2	880		T3	198
valid_sources[0x1f]	558741	1			T1	110		T2	925		T3	245
valid_sources[0x20]	554254	1			T1	121		T2	805		T3	244
valid_sources[0x21]	566149	1			T1	80		T2	882		T3	261
valid_sources[0x22]	554033	1			T1	141		T2	906		T3	247
valid_sources[0x23]	770072	1			T1	88		T2	970		T3	181
valid_sources[0x24]	591245	1			T1	117		T2	859		T3	177
valid_sources[0x25]	584595	1			T1	126		T2	900		T3	233
valid_sources[0x26]	550385	1			T1	161		T2	857		T3	232
valid_sources[0x27]	589225	1			T1	142		T2	935		T3	188
valid_sources[0x28]	563455	1			T1	127		T2	951		T3	239
valid_sources[0x29]	570089	1			T1	79		T2	912		T3	237
valid_sources[0x2a]	565203	1			T1	107		T2	972		T3	212
valid_sources[0x2b]	3342356	1			T1	162		T2	987		T3	271
valid_sources[0x2c]	616939	1			T1	57		T2	1009		T3	220
valid_sources[0x2d]	555771	1			T1	115		T2	1029		T3	206
valid_sources[0x2e]	1653090	1			T1	153		T2	892		T3	204
valid_sources[0x2f]	586729	1			T1	106		T2	941		T3	182
valid_sources[0x30]	617247	1			T1	125		T2	876		T3	268
valid_sources[0x31]	541571	1			T1	135		T2	892		T3	250
valid_sources[0x32]	560371	1			T1	164		T2	917		T3	267
valid_sources[0x33]	568659	1			T1	113		T2	895		T3	224
valid_sources[0x34]	559482	1			T1	141		T2	933		T3	224
valid_sources[0x35]	1665564	1			T1	124		T2	926		T3	271
valid_sources[0x36]	535363	1			T1	118		T2	973		T3	215
valid_sources[0x37]	591172	1			T1	79		T2	905		T3	207
valid_sources[0x38]	564596	1			T1	112		T2	907		T3	227
valid_sources[0x39]	540691	1			T1	112		T2	783		T3	249
valid_sources[0x3a]	545332	1			T1	133		T2	848		T3	258
valid_sources[0x3b]	558628	1			T1	134		T2	916		T3	226
valid_sources[0x3c]	556242	1			T1	116		T2	941		T3	228
valid_sources[0x3d]	552297	1			T1	93		T2	812		T3	219
valid_sources[0x3e]	543396	1			T1	81		T2	898		T3	247
valid_sources[0x3f]	571063	1			T1	117		T2	916		T3	207
valid_sources[0x40]	557775	1			T1	114		T2	926		T3	211
valid_sources[0x41]	579002	1			T1	90		T2	904		T3	279
valid_sources[0x42]	614925	1			T1	154		T2	867		T3	193
valid_sources[0x43]	593791	1			T1	123		T2	949		T3	206
valid_sources[0x44]	652081	1			T1	178		T2	954		T3	239
valid_sources[0x45]	610908	1			T1	123		T2	950		T3	273
valid_sources[0x46]	733239	1			T1	130		T2	995		T3	238
valid_sources[0x47]	551185	1			T1	142		T2	816		T3	255
valid_sources[0x48]	570344	1			T1	103		T2	918		T3	227
valid_sources[0x49]	1073325	1			T1	98		T2	956		T3	254
valid_sources[0x4a]	609130	1			T1	117		T2	810		T3	222
valid_sources[0x4b]	549710	1			T1	121		T2	910		T3	218
valid_sources[0x4c]	601078	1			T1	117		T2	840		T3	231
valid_sources[0x4d]	546764	1			T1	141		T2	961		T3	236
valid_sources[0x4e]	554056	1			T1	143		T2	840		T3	259
valid_sources[0x4f]	541360	1			T1	124		T2	911		T3	204
valid_sources[0x50]	595440	1			T1	87		T2	891		T3	223
valid_sources[0x51]	542092	1			T1	144		T2	763		T3	200
valid_sources[0x52]	2156837	1			T1	147		T2	885		T3	217
valid_sources[0x53]	574227	1			T1	82		T2	886		T3	214
valid_sources[0x54]	558363	1			T1	114		T2	932		T3	286
valid_sources[0x55]	1105635	1			T1	140		T2	862		T3	256
valid_sources[0x56]	589638	1			T1	108		T2	900		T3	243
valid_sources[0x57]	552300	1			T1	126		T2	850		T3	234
valid_sources[0x58]	758252	1			T1	110		T2	867		T3	257
valid_sources[0x59]	548814	1			T1	135		T2	874		T3	245
valid_sources[0x5a]	568955	1			T1	151		T2	901		T3	238
valid_sources[0x5b]	953981	1			T1	154		T2	836		T3	249
valid_sources[0x5c]	555960	1			T1	122		T2	762		T3	231
valid_sources[0x5d]	572790	1			T1	70		T2	994		T3	270
valid_sources[0x5e]	563081	1			T1	133		T2	823		T3	234
valid_sources[0x5f]	587239	1			T1	179		T2	1010		T3	235
valid_sources[0x60]	568449	1			T1	107		T2	963		T3	206
valid_sources[0x61]	563736	1			T1	91		T2	925		T3	218
valid_sources[0x62]	983298	1			T1	147		T2	867		T3	213
valid_sources[0x63]	579217	1			T1	111		T2	886		T3	217
valid_sources[0x64]	545780	1			T1	153		T2	766		T3	256
valid_sources[0x65]	546452	1			T1	141		T2	974		T3	199
valid_sources[0x66]	549397	1			T1	116		T2	889		T3	252
valid_sources[0x67]	546896	1			T1	102		T2	951		T3	260
valid_sources[0x68]	566760	1			T1	86		T2	1020		T3	238
valid_sources[0x69]	533164	1			T1	107		T2	916		T3	235
valid_sources[0x6a]	745893	1			T1	158		T2	896		T3	239
valid_sources[0x6b]	574249	1			T1	136		T2	880		T3	270
valid_sources[0x6c]	538984	1			T1	147		T2	903		T3	263
valid_sources[0x6d]	566408	1			T1	128		T2	934		T3	229
valid_sources[0x6e]	552731	1			T1	108		T2	906		T3	197
valid_sources[0x6f]	596551	1			T1	168		T2	899		T3	224
valid_sources[0x70]	1211155	1			T1	109		T2	1030		T3	257
valid_sources[0x71]	553767	1			T1	133		T2	828		T3	202
valid_sources[0x72]	544408	1			T1	130		T2	945		T3	223
valid_sources[0x73]	562505	1			T1	107		T2	779		T3	250
valid_sources[0x74]	583316	1			T1	120		T2	859		T3	267
valid_sources[0x75]	557608	1			T1	140		T2	920		T3	219
valid_sources[0x76]	557049	1			T1	146		T2	923		T3	246
valid_sources[0x77]	564291	1			T1	66		T2	938		T3	262
valid_sources[0x78]	556814	1			T1	106		T2	852		T3	261
valid_sources[0x79]	578066	1			T1	78		T2	879		T3	251
valid_sources[0x7a]	561510	1			T1	88		T2	823		T3	216
valid_sources[0x7b]	539818	1			T1	102		T2	944		T3	234
valid_sources[0x7c]	636841	1			T1	138		T2	840		T3	247
valid_sources[0x7d]	604384	1			T1	64		T2	941		T3	250
valid_sources[0x7e]	548568	1			T1	104		T2	758		T3	260
valid_sources[0x7f]	570457	1			T1	148		T2	862		T3	267
valid_sources[0x80]	544329	1			T1	109		T2	882		T3	269

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

75150804

1

T1

14145

T2

104204

T3

260

values[0x0]

all_enables

biggest_size

39059236

1

T1

7125

T2

52761

T3

1410

values[0x1]

all_enables

biggest_size

39066385

1

T1

6943

T2

52485

T3

1378

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	47882	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

173862

1

T1

1

T2

29

T4

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	60420	1			T2	21		T6	35		T19	21
values[0x0]	77763	1			T1	3		T2	45		T3	1
values[0x1]	83561	1			T1	5		T2	42		T3	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	36963	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

184781

1

T1

1

T2

36

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	837	1			T4	1		T25	16		T8	2
valid_sources[0x01]	847	1			T2	1		T25	12		T49	2
valid_sources[0x02]	864	1			T4	1		T24	1		T25	14
valid_sources[0x03]	1069	1			T2	1		T25	17		T49	2
valid_sources[0x04]	704	1			T6	1		T24	3		T25	16
valid_sources[0x05]	957	1			T28	1		T25	10		T8	1
valid_sources[0x06]	868	1			T25	10		T54	2		T49	2
valid_sources[0x07]	670	1			T25	12		T8	2		T26	1
valid_sources[0x08]	916	1			T2	1		T14	9		T25	14
valid_sources[0x09]	1131	1			T2	1		T25	13		T52	2
valid_sources[0x0a]	1123	1			T6	1		T25	16		T54	2
valid_sources[0x0b]	1066	1			T25	14		T8	1		T49	1
valid_sources[0x0c]	915	1			T25	16		T8	4		T54	3
valid_sources[0x0d]	758	1			T7	1		T25	14		T77	1
valid_sources[0x0e]	881	1			T2	1		T23	2		T24	158
valid_sources[0x0f]	1009	1			T25	6		T8	2		T49	2
valid_sources[0x10]	1025	1			T24	400		T25	21		T8	5
valid_sources[0x11]	1084	1			T6	1		T25	11		T54	1
valid_sources[0x12]	704	1			T4	2		T25	8		T26	1
valid_sources[0x13]	669	1			T2	2		T6	1		T25	19
valid_sources[0x14]	662	1			T2	1		T7	1		T25	14
valid_sources[0x15]	1371	1			T25	14		T8	1		T49	3
valid_sources[0x16]	848	1			T25	16		T49	2		T52	2
valid_sources[0x17]	1383	1			T2	1		T19	183		T25	11
valid_sources[0x18]	755	1			T25	12		T49	2		T52	2
valid_sources[0x19]	833	1			T25	11		T54	1		T49	2
valid_sources[0x1a]	666	1			T6	2		T25	11		T26	9
valid_sources[0x1b]	750	1			T5	5		T25	16		T15	1
valid_sources[0x1c]	811	1			T2	2		T25	11		T8	2
valid_sources[0x1d]	848	1			T25	12		T77	1		T8	1
valid_sources[0x1e]	646	1			T4	1		T6	1		T25	14
valid_sources[0x1f]	840	1			T25	15		T49	1		T44	1
valid_sources[0x20]	1119	1			T25	23		T54	4		T165	1
valid_sources[0x21]	764	1			T2	1		T3	3		T25	16
valid_sources[0x22]	855	1			T25	18		T26	1		T49	4
valid_sources[0x23]	709	1			T10	1		T13	1		T25	11
valid_sources[0x24]	930	1			T6	1		T24	3		T25	21
valid_sources[0x25]	1166	1			T24	145		T25	13		T8	2
valid_sources[0x26]	723	1			T27	1		T7	1		T25	14
valid_sources[0x27]	1073	1			T2	1		T12	1		T7	1
valid_sources[0x28]	933	1			T25	12		T166	2		T49	1
valid_sources[0x29]	751	1			T25	10		T79	1		T8	2
valid_sources[0x2a]	833	1			T2	1		T6	2		T163	1
valid_sources[0x2b]	740	1			T2	1		T6	1		T76	2
valid_sources[0x2c]	949	1			T2	1		T6	1		T24	178
valid_sources[0x2d]	926	1			T12	1		T25	10		T80	1
valid_sources[0x2e]	1037	1			T13	4		T24	92		T25	13
valid_sources[0x2f]	992	1			T24	224		T25	12		T8	5
valid_sources[0x30]	721	1			T25	16		T8	3		T54	2
valid_sources[0x31]	985	1			T7	2		T25	9		T54	3
valid_sources[0x32]	750	1			T2	1		T25	18		T8	1
valid_sources[0x33]	878	1			T2	1		T24	114		T25	17
valid_sources[0x34]	934	1			T2	4		T25	14		T8	1
valid_sources[0x35]	839	1			T25	16		T15	3		T54	1
valid_sources[0x36]	828	1			T6	1		T25	10		T26	2
valid_sources[0x37]	859	1			T2	1		T25	18		T8	2
valid_sources[0x38]	751	1			T25	10		T49	1		T83	1
valid_sources[0x39]	895	1			T6	2		T25	14		T8	2
valid_sources[0x3a]	819	1			T2	1		T6	3		T25	24
valid_sources[0x3b]	771	1			T2	1		T25	6		T116	4
valid_sources[0x3c]	888	1			T25	7		T52	1		T167	1
valid_sources[0x3d]	675	1			T25	7		T8	1		T54	1
valid_sources[0x3e]	830	1			T6	1		T25	14		T46	1
valid_sources[0x3f]	759	1			T7	1		T25	28		T8	2
valid_sources[0x40]	710	1			T2	1		T25	11		T54	2
valid_sources[0x41]	843	1			T25	13		T49	1		T52	1
valid_sources[0x42]	1029	1			T6	2		T25	9		T8	2
valid_sources[0x43]	976	1			T168	1		T25	17		T26	2
valid_sources[0x44]	949	1			T25	10		T8	1		T49	1
valid_sources[0x45]	800	1			T7	1		T25	10		T49	2
valid_sources[0x46]	679	1			T12	1		T64	1		T25	17
valid_sources[0x47]	710	1			T25	18		T8	1		T52	2
valid_sources[0x48]	899	1			T25	11		T52	5		T169	1
valid_sources[0x49]	572	1			T25	10		T43	2		T49	2
valid_sources[0x4a]	965	1			T25	13		T49	1		T69	9
valid_sources[0x4b]	818	1			T6	3		T24	42		T25	12
valid_sources[0x4c]	766	1			T25	12		T8	2		T49	2
valid_sources[0x4d]	953	1			T6	1		T25	5		T49	3
valid_sources[0x4e]	887	1			T7	1		T25	12		T52	1
valid_sources[0x4f]	663	1			T6	1		T24	3		T25	22
valid_sources[0x50]	795	1			T2	1		T24	1		T25	17
valid_sources[0x51]	1000	1			T2	1		T9	1		T25	13
valid_sources[0x52]	1053	1			T2	1		T25	14		T8	1
valid_sources[0x53]	1125	1			T25	19		T8	1		T54	1
valid_sources[0x54]	912	1			T25	11		T54	1		T49	4
valid_sources[0x55]	717	1			T25	14		T166	1		T49	3
valid_sources[0x56]	806	1			T2	1		T25	6		T26	7
valid_sources[0x57]	763	1			T25	16		T8	1		T49	1
valid_sources[0x58]	1013	1			T2	2		T6	1		T24	3
valid_sources[0x59]	831	1			T25	18		T8	2		T83	2
valid_sources[0x5a]	948	1			T4	1		T25	18		T49	1
valid_sources[0x5b]	899	1			T9	1		T25	11		T8	2
valid_sources[0x5c]	913	1			T2	1		T25	16		T77	1
valid_sources[0x5d]	902	1			T25	10		T165	1		T52	6
valid_sources[0x5e]	754	1			T2	1		T25	12		T79	1
valid_sources[0x5f]	708	1			T25	11		T80	1		T170	1
valid_sources[0x60]	911	1			T25	16		T49	3		T52	1
valid_sources[0x61]	681	1			T2	3		T25	14		T49	4
valid_sources[0x62]	652	1			T6	2		T25	16		T49	1
valid_sources[0x63]	608	1			T2	1		T25	10		T77	1
valid_sources[0x64]	697	1			T2	4		T6	1		T25	19
valid_sources[0x65]	903	1			T2	1		T25	16		T79	1
valid_sources[0x66]	1612	1			T2	2		T25	12		T54	1
valid_sources[0x67]	867	1			T2	2		T25	11		T15	1
valid_sources[0x68]	761	1			T2	1		T25	13		T52	3
valid_sources[0x69]	707	1			T2	2		T25	18		T8	1
valid_sources[0x6a]	911	1			T1	8		T2	1		T25	13
valid_sources[0x6b]	649	1			T2	3		T25	22		T166	1
valid_sources[0x6c]	1346	1			T2	1		T24	371		T25	12
valid_sources[0x6d]	734	1			T4	1		T41	1		T7	2
valid_sources[0x6e]	852	1			T2	1		T24	1		T25	12
valid_sources[0x6f]	917	1			T4	1		T25	6		T77	1
valid_sources[0x70]	1134	1			T2	1		T25	20		T49	1
valid_sources[0x71]	701	1			T24	3		T25	7		T8	2
valid_sources[0x72]	953	1			T7	1		T24	3		T25	16
valid_sources[0x73]	976	1			T25	10		T54	1		T26	83
valid_sources[0x74]	1157	1			T25	11		T26	1		T52	4
valid_sources[0x75]	906	1			T2	1		T25	13		T8	2
valid_sources[0x76]	1093	1			T6	2		T25	12		T8	3
valid_sources[0x77]	788	1			T2	1		T25	18		T166	1
valid_sources[0x78]	1172	1			T168	1		T7	1		T25	8
valid_sources[0x79]	740	1			T25	18		T8	1		T54	2
valid_sources[0x7a]	744	1			T6	1		T25	13		T49	1
valid_sources[0x7b]	773	1			T2	1		T25	13		T8	1
valid_sources[0x7c]	754	1			T42	2		T7	3		T25	19
valid_sources[0x7d]	1157	1			T64	1		T24	5		T25	9
valid_sources[0x7e]	1014	1			T25	10		T8	3		T49	3
valid_sources[0x7f]	925	1			T6	1		T25	15		T8	1
valid_sources[0x80]	726	1			T4	2		T25	16		T26	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

46507

1

T2

7

T6

22

T19

14

values[0x0]

all_enables

biggest_size

65080

1

T2

16

T4

3

T9

1

values[0x1]

all_enables

biggest_size

62275

1

T1

1

T2

6

T4

1