Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16074049

1

T1

2405

T2

19434

T3

57724

full_word

150366434

1

T1

24249

T2

195948

T3

3048

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	166440173	1			T1	26654		T2	215382		T3	60772
auto[TlIntgErrCmd]	109	1			T61	10		T62	2		T63	4
auto[TlIntgErrData]	106	1			T61	7		T62	3		T63	8
auto[TlIntgErrBoth]	95	1			T61	3		T62	5		T63	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

80173644

1

T1

11159

T2

99847

T3

30208

auto[1]

86266839

1

T1

15495

T2

115535

T3

30564

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7864432	1			T1	978		T2	9145		T3	29948
auto[TlIntgErrNone]	partial	auto[1]	8209330	1			T1	1427		T2	10289		T3	27776
auto[TlIntgErrNone]	full_word	auto[0]	72309065	1			T1	10181		T2	90702		T3	260
auto[TlIntgErrNone]	full_word	auto[1]	78057346	1			T1	14068		T2	105246		T3	2788
auto[TlIntgErrCmd]	partial	auto[0]	44	1			T61	5		T63	2		T148	1
auto[TlIntgErrCmd]	partial	auto[1]	55	1			T61	4		T62	2		T63	1
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T61	1		T148	1		T146	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T63	1		T152	1		T153	1
auto[TlIntgErrData]	partial	auto[0]	50	1			T61	4		T62	1		T63	3
auto[TlIntgErrData]	partial	auto[1]	46	1			T61	3		T62	1		T63	4
auto[TlIntgErrData]	full_word	auto[0]	5	1			T63	1		T150	2		T154	2
auto[TlIntgErrData]	full_word	auto[1]	5	1			T62	1		T155	1		T152	2
auto[TlIntgErrBoth]	partial	auto[0]	42	1			T62	2		T63	6		T148	5
auto[TlIntgErrBoth]	partial	auto[1]	50	1			T61	2		T62	3		T63	2
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T61	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T146	1		T156	1		-	-