Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	924185	1			T1	229		T2	7893		T4	1620
auto[1]	10535026	1			T1	156		T2	985		T5	115707
auto[2]	717476	1			T1	129		T2	4009		T4	1100
auto[3]	10258451	1			T1	93		T2	405		T5	116016

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14414214	1			T1	465		T2	10646		T5	7748
auto[1]	2063291	1			T1	50		T2	1268		T5	34467
auto[2]	2109184	1			T1	84		T2	1230		T5	34348
auto[3]	3848449	1			T1	8		T2	148		T5	155160

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9206182

1

T1

607

T2

13292

T4

3157

auto[1]

13228956

1

T5

231723

T13

148848

T41

60820

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	350799	1			T1	193		T2	6586		T4	1347
auto[0]	auto[0]	auto[1]	35691	1			T1	13		T2	585		T4	132
auto[0]	auto[0]	auto[2]	35906	1			T1	19		T2	662		T4	132
auto[0]	auto[0]	auto[3]	32915	1			T1	4		T2	60		T4	9
auto[0]	auto[1]	auto[0]	3215534	1			T1	117		T2	559		T4	159
auto[0]	auto[1]	auto[1]	343727	1			T1	24		T2	348		T4	102
auto[0]	auto[1]	auto[2]	359164	1			T1	15		T2	46		T4	15
auto[0]	auto[1]	auto[3]	386991	1			T2	32		T4	4		T9	114
auto[0]	auto[2]	auto[0]	256047	1			T1	95		T2	3340		T4	949
auto[0]	auto[2]	auto[1]	26996	1			T1	8		T2	321		T4	84
auto[0]	auto[2]	auto[2]	28487	1			T1	23		T2	316		T4	60
auto[0]	auto[2]	auto[3]	23437	1			T1	3		T2	32		T4	7
auto[0]	auto[3]	auto[0]	3059554	1			T1	60		T2	161		T4	79
auto[0]	auto[3]	auto[1]	339569	1			T1	5		T2	14		T4	7
auto[0]	auto[3]	auto[2]	355502	1			T1	27		T2	206		T4	66
auto[0]	auto[3]	auto[3]	355863	1			T1	1		T2	24		T4	5
auto[1]	auto[0]	auto[0]	15618	1			T41	482		T115	651		T117	157
auto[1]	auto[0]	auto[1]	69911	1			T41	2221		T115	2945		T117	685
auto[1]	auto[0]	auto[2]	70154	1			T41	2141		T115	2886		T117	728
auto[1]	auto[0]	auto[3]	313191	1			T41	9714		T115	13281		T163	1
auto[1]	auto[1]	auto[0]	3752913	1			T5	3806		T13	61215		T41	311
auto[1]	auto[1]	auto[1]	624059	1			T5	17193		T13	6286		T41	2498
auto[1]	auto[1]	auto[2]	590003	1			T5	17070		T13	6100		T41	1432
auto[1]	auto[1]	auto[3]	1262635	1			T5	77638		T13	632		T41	11358
auto[1]	auto[2]	auto[0]	11482	1			T41	303		T115	623		T83	1
auto[1]	auto[2]	auto[1]	51345	1			T41	1322		T115	2710		T164	2546
auto[1]	auto[2]	auto[2]	58360	1			T41	2381		T115	2527		T117	629
auto[1]	auto[2]	auto[3]	261322	1			T41	10695		T115	11185		T117	2763
auto[1]	auto[3]	auto[0]	3752267	1			T5	3942		T13	61396		T41	110
auto[1]	auto[3]	auto[1]	571993	1			T5	17274		T13	6287		T41	553
auto[1]	auto[3]	auto[2]	611608	1			T5	17278		T13	6317		T41	2712
auto[1]	auto[3]	auto[3]	1212095	1			T5	77522		T13	615		T41	12587