Line Coverage for Module :
prim_mubi8_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Module :
prim_mubi8_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
901 |
901 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1098044706 |
1097933582 |
0 |
0 |
T1 |
351405 |
351319 |
0 |
0 |
T2 |
204360 |
204354 |
0 |
0 |
T3 |
243149 |
243050 |
0 |
0 |
T4 |
707699 |
707635 |
0 |
0 |
T5 |
786432 |
786344 |
0 |
0 |
T9 |
73974 |
73881 |
0 |
0 |
T10 |
78282 |
78192 |
0 |
0 |
T11 |
68749 |
68673 |
0 |
0 |
T12 |
786 |
724 |
0 |
0 |
T13 |
372880 |
372792 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1098044706 |
1097920436 |
0 |
2703 |
T1 |
351405 |
351316 |
0 |
3 |
T2 |
204360 |
204354 |
0 |
3 |
T3 |
243149 |
243047 |
0 |
3 |
T4 |
707699 |
707632 |
0 |
3 |
T5 |
786432 |
786341 |
0 |
3 |
T9 |
73974 |
73878 |
0 |
3 |
T10 |
78282 |
78189 |
0 |
3 |
T11 |
68749 |
68670 |
0 |
3 |
T12 |
786 |
721 |
0 |
3 |
T13 |
372880 |
372789 |
0 |
3 |