Module Definition
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Module : prim_lc_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_prim_lc_sync 100.00 100.00 100.00
tb.dut.u_tlul_lc_gate.u_err_en_sync 100.00 100.00 100.00
tb.dut.gen_instr_ctrl.u_prim_lc_sync_hw_debug_en 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_lc_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.90 100.00 88.89 100.00 100.00 70.59 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_tlul_lc_gate.u_err_en_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
89.00 100.00 100.00 100.00 95.00 50.00 u_tlul_lc_gate


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_instr_ctrl.u_prim_lc_sync_hw_debug_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.90 100.00 88.89 100.00 100.00 70.59 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=2,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_prim_lc_sync

Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 2 2


Line Coverage for Module : prim_lc_sync ( parameter NumCopies=2,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_tlul_lc_gate.u_err_en_sync

Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS8400
CONT_ASSIGN9311100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
84 unreachable
85 unreachable
87 unreachable
93 1 1
106 2 2


Line Coverage for Module : prim_lc_sync ( parameter NumCopies=1,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.gen_instr_ctrl.u_prim_lc_sync_hw_debug_en

Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 1 1


Assert Coverage for Module : prim_lc_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 2703 2703 0 0
OutputsKnown_A 2147483647 2147483647 0 0
gen_flops.OutputDelay_A 2147483647 2147483647 0 5406
gen_no_flops.OutputDelay_A 1098044706 1097933582 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2703 2703 0 0
T1 3 3 0 0
T2 3 3 0 0
T3 3 3 0 0
T4 3 3 0 0
T5 3 3 0 0
T9 3 3 0 0
T10 3 3 0 0
T11 3 3 0 0
T12 3 3 0 0
T13 3 3 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 1054215 1053957 0 0
T2 613080 613062 0 0
T3 729447 729150 0 0
T4 2123097 2122905 0 0
T5 2359296 2359032 0 0
T9 221922 221643 0 0
T10 234846 234576 0 0
T11 206247 206019 0 0
T12 2358 2172 0 0
T13 1118640 1118376 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 5406
T1 702810 702632 0 6
T2 408720 408708 0 6
T3 486298 486094 0 6
T4 1415398 1415264 0 6
T5 1572864 1572682 0 6
T9 147948 147756 0 6
T10 156564 156378 0 6
T11 137498 137340 0 6
T12 1572 1442 0 6
T13 745760 745578 0 6

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1098044706 1097933582 0 0
T1 351405 351319 0 0
T2 204360 204354 0 0
T3 243149 243050 0 0
T4 707699 707635 0 0
T5 786432 786344 0 0
T9 73974 73881 0 0
T10 78282 78192 0 0
T11 68749 68673 0 0
T12 786 724 0 0
T13 372880 372792 0 0

Line Coverage for Instance : tb.dut.u_prim_lc_sync
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 2 2


Assert Coverage for Instance : tb.dut.u_prim_lc_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 901 901 0 0
OutputsKnown_A 1098044706 1097933582 0 0
gen_flops.OutputDelay_A 1098044706 1097920436 0 2703


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 901 901 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1098044706 1097933582 0 0
T1 351405 351319 0 0
T2 204360 204354 0 0
T3 243149 243050 0 0
T4 707699 707635 0 0
T5 786432 786344 0 0
T9 73974 73881 0 0
T10 78282 78192 0 0
T11 68749 68673 0 0
T12 786 724 0 0
T13 372880 372792 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1098044706 1097920436 0 2703
T1 351405 351316 0 3
T2 204360 204354 0 3
T3 243149 243047 0 3
T4 707699 707632 0 3
T5 786432 786341 0 3
T9 73974 73878 0 3
T10 78282 78189 0 3
T11 68749 68670 0 3
T12 786 721 0 3
T13 372880 372789 0 3

Line Coverage for Instance : tb.dut.u_tlul_lc_gate.u_err_en_sync
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS8400
CONT_ASSIGN9311100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
84 unreachable
85 unreachable
87 unreachable
93 1 1
106 2 2


Assert Coverage for Instance : tb.dut.u_tlul_lc_gate.u_err_en_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 901 901 0 0
OutputsKnown_A 1098044706 1097933582 0 0
gen_no_flops.OutputDelay_A 1098044706 1097933582 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 901 901 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1098044706 1097933582 0 0
T1 351405 351319 0 0
T2 204360 204354 0 0
T3 243149 243050 0 0
T4 707699 707635 0 0
T5 786432 786344 0 0
T9 73974 73881 0 0
T10 78282 78192 0 0
T11 68749 68673 0 0
T12 786 724 0 0
T13 372880 372792 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1098044706 1097933582 0 0
T1 351405 351319 0 0
T2 204360 204354 0 0
T3 243149 243050 0 0
T4 707699 707635 0 0
T5 786432 786344 0 0
T9 73974 73881 0 0
T10 78282 78192 0 0
T11 68749 68673 0 0
T12 786 724 0 0
T13 372880 372792 0 0

Line Coverage for Instance : tb.dut.gen_instr_ctrl.u_prim_lc_sync_hw_debug_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 1 1


Assert Coverage for Instance : tb.dut.gen_instr_ctrl.u_prim_lc_sync_hw_debug_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 901 901 0 0
OutputsKnown_A 1098044706 1097933582 0 0
gen_flops.OutputDelay_A 1098044706 1097920436 0 2703


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 901 901 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1098044706 1097933582 0 0
T1 351405 351319 0 0
T2 204360 204354 0 0
T3 243149 243050 0 0
T4 707699 707635 0 0
T5 786432 786344 0 0
T9 73974 73881 0 0
T10 78282 78192 0 0
T11 68749 68673 0 0
T12 786 724 0 0
T13 372880 372792 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1098044706 1097920436 0 2703
T1 351405 351316 0 3
T2 204360 204354 0 3
T3 243149 243047 0 3
T4 707699 707632 0 3
T5 786432 786341 0 3
T9 73974 73878 0 3
T10 78282 78189 0 3
T11 68749 68670 0 3
T12 786 721 0 3
T13 372880 372789 0 3

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