Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : sram_ctrl_regs_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.sram_ctrl_regs_csr_assert 100.00 100.00



Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.90 100.00 88.89 100.00 100.00 70.59 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 1110178387 260892 0 0
ctrl_regwen_rd_A 1110178387 3744 0 0
exec_rd_A 1110178387 3587 0 0
exec_regwen_rd_A 1110178387 3748 0 0
readback_rd_A 1110178387 2048 0 0
readback_regwen_rd_A 1110178387 1833 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1110178387 260892 0 0
T8 526924 0 0 0
T15 1564 0 0 0
T24 159426 6614 0 0
T25 115651 6365 0 0
T26 0 2326 0 0
T69 0 3585 0 0
T70 0 4878 0 0
T71 0 3774 0 0
T72 0 5300 0 0
T73 0 873 0 0
T74 0 2402 0 0
T75 0 6644 0 0
T76 74513 0 0 0
T77 548108 0 0 0
T78 145031 0 0 0
T79 220016 0 0 0
T80 175018 0 0 0
T81 34160 0 0 0

ctrl_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1110178387 3744 0 0
T22 452288 0 0 0
T69 121089 169 0 0
T73 0 75 0 0
T126 0 297 0 0
T130 0 298 0 0
T131 0 149 0 0
T132 0 321 0 0
T133 0 235 0 0
T134 0 140 0 0
T135 0 189 0 0
T136 0 272 0 0
T137 42374 0 0 0
T138 74932 0 0 0
T139 33698 0 0 0
T140 269231 0 0 0
T141 206796 0 0 0
T142 103489 0 0 0
T143 541107 0 0 0
T144 33535 0 0 0

exec_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1110178387 3587 0 0
T22 452288 0 0 0
T69 121089 204 0 0
T73 0 55 0 0
T126 0 241 0 0
T130 0 267 0 0
T131 0 124 0 0
T132 0 193 0 0
T133 0 263 0 0
T134 0 110 0 0
T135 0 186 0 0
T136 0 271 0 0
T137 42374 0 0 0
T138 74932 0 0 0
T139 33698 0 0 0
T140 269231 0 0 0
T141 206796 0 0 0
T142 103489 0 0 0
T143 541107 0 0 0
T144 33535 0 0 0

exec_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1110178387 3748 0 0
T22 452288 0 0 0
T69 121089 227 0 0
T73 0 58 0 0
T126 0 321 0 0
T130 0 342 0 0
T131 0 87 0 0
T132 0 211 0 0
T133 0 272 0 0
T134 0 113 0 0
T135 0 169 0 0
T136 0 280 0 0
T137 42374 0 0 0
T138 74932 0 0 0
T139 33698 0 0 0
T140 269231 0 0 0
T141 206796 0 0 0
T142 103489 0 0 0
T143 541107 0 0 0
T144 33535 0 0 0

readback_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1110178387 2048 0 0
T22 452288 0 0 0
T69 121089 171 0 0
T73 0 100 0 0
T126 0 257 0 0
T130 0 263 0 0
T131 0 138 0 0
T132 0 158 0 0
T133 0 215 0 0
T134 0 82 0 0
T135 0 192 0 0
T136 0 207 0 0
T137 42374 0 0 0
T138 74932 0 0 0
T139 33698 0 0 0
T140 269231 0 0 0
T141 206796 0 0 0
T142 103489 0 0 0
T143 541107 0 0 0
T144 33535 0 0 0

readback_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1110178387 1833 0 0
T22 452288 0 0 0
T69 121089 137 0 0
T73 0 50 0 0
T126 0 234 0 0
T130 0 222 0 0
T131 0 98 0 0
T132 0 137 0 0
T133 0 255 0 0
T134 0 79 0 0
T135 0 203 0 0
T136 0 185 0 0
T137 42374 0 0 0
T138 74932 0 0 0
T139 33698 0 0 0
T140 269231 0 0 0
T141 206796 0 0 0
T142 103489 0 0 0
T143 541107 0 0 0
T144 33535 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%