Unified Coverage Report :: Module :: tlul_sram_byte

Module : tlul_sram_byte

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.84	99.31	93.07		100.00	91.80	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_tlul_adapter_sram.u_sram_byte	97.40	99.31	95.88		100.00	91.80	100.00

---

Module Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.40	99.31	95.88		100.00	91.80	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.19	98.79	94.94		100.00	92.23	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.26	98.70	89.47			96.88	100.00	u_tlul_adapter_sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_integ_handling.gen_readback_logic.u_rdback_check_flop	100.00	100.00				100.00
gen_integ_handling.gen_readback_logic.u_rdback_chk_ok_buf	100.00	100.00
gen_integ_handling.gen_readback_logic.u_rdback_data_exp	100.00	100.00				100.00
gen_integ_handling.gen_readback_logic.u_rdback_data_exp_intg	100.00	100.00				100.00
gen_integ_handling.gen_readback_logic.u_rdback_en_flop	100.00	100.00				100.00
gen_integ_handling.u_sync_fifo	90.73	95.00	86.67			81.25	100.00
gen_integ_handling.u_sync_fifo_a_size	100.00	100.00	100.00			100.00	100.00
gen_integ_handling.u_tlul_data_integ_enc	100.00	100.00

Line Coverage for Module : tlul_sram_byte

	Line No.	Total	Covered	Percent
TOTAL		145	144	99.31
ALWAYS	105	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
ALWAYS	239	95	94	98.95
CONT_ASSIGN	506	1	1	100.00
CONT_ASSIGN	517	1	1	100.00
ALWAYS	542	2	2	100.00
ALWAYS	553	0	0
ALWAYS	553	2	2	100.00
ALWAYS	572	2	2	100.00
ALWAYS	579	22	22	100.00
CONT_ASSIGN	633	1	1	100.00
ALWAYS	658	4	4	100.00
CONT_ASSIGN	676	1	1	100.00
CONT_ASSIGN	699	1	1	100.00
CONT_ASSIGN	716	1	1	100.00
CONT_ASSIGN	717	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
105	1	1
106	1	1
108	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
145	1	1
156	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
253	1	1
255	1	1
257	1	1
262	1	1
263	1	1
266	1	1
267	0	1
			MISSING_ELSE
			MISSING_ELSE
271	1	1
272	1	1
273	1	1
274	1	1
			MISSING_ELSE
276	1	1
280	1	1
281	1	1
			MISSING_ELSE
284	1	1
287	1	1
			MISSING_ELSE
295	1	1
296	1	1
297	1	1
298	1	1
299	1	1
300	1	1
			==> MISSING_ELSE
			MISSING_ELSE
306	1	1
307	1	1
309	1	1
310	1	1
311	1	1
312	1	1
313	1	1
			==> MISSING_ELSE
320	1	1
322		unreachable
			MISSING_ELSE
326	1	1
330	1	1
331	1	1
334	1	1
335	1	1
336	1	1
337	1	1
340	1	1
343	1	1
			MISSING_ELSE
350	1	1
352		unreachable
			MISSING_ELSE
355	1	1
357	1	1
359	1	1
365	1	1
367		unreachable
			MISSING_ELSE
371	1	1
373	1	1
375	1	1
378	1	1
			MISSING_ELSE
385	1	1
387		unreachable
			MISSING_ELSE
392	1	1
395	1	1
398	1	1
400	1	1
403	1	1
409	1	1
			==> MISSING_ELSE
417	1	1
419		unreachable
			MISSING_ELSE
422	1	1
424	1	1
426	1	1
430	1	1
432		unreachable
			MISSING_ELSE
435	1	1
438	1	1
440	1	1
443	1	1
			MISSING_ELSE
448	1	1
450		unreachable
			MISSING_ELSE
455	1	1
459	1	1
460	1	1
462	1	1
463	1	1
465	1	1
466	1	1
467	1	1
470	1	1
			MISSING_ELSE
476	1	1
478		unreachable
			MISSING_ELSE
481	1	1
483	1	1
486	1	1
488	1	1
489	1	1
490	1	1
			MISSING_ELSE
506	1	1
517	1	1
542	1	1
543	1	1
			MISSING_ELSE
553	1	1
554	1	1
572	1	1
573	1	1
579	1	1
581	1	1
590	1	1
591	1	1
593	1	1
596	1	1
598	1	1
602	1	1
603	1	1
605	1	1
606	1	1
607	1	1
608	1	1
610	1	1
612	1	1
614	1	1
617	1	1
618	1	1
620	1	1
621	1	1
			MISSING_ELSE
623	1	1
626	1	1
			MISSING_ELSE
633	1	1
658	1	1
661	1	1
665	1	1
670	1	1
676	1	1
699	1	1
716	1	1
717	1	1

---

Cond Coverage for Module : tlul_sram_byte

	Total	Covered	Percent
Conditions	101	94	93.07
Logical	101	94	93.07
Non-Logical	0	0
Event	0	0

 LINE       138
 EXPRESSION (tl_i.a_valid & tl_o.a_ready)
             ------1-----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       139
 EXPRESSION (tl_o.d_valid & tl_i.d_ready)
             ------1-----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       140
 EXPRESSION (tl_sram_o.a_valid & tl_sram_i.a_ready)
             --------1--------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       141
 EXPRESSION (tl_sram_i.d_valid & tl_sram_o.d_ready)
             --------1--------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       142
 EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData))
             ---------------1--------------   ----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       142
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       142
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (gen_integ_handling.byte_wr_txn & gen_integ_handling.a_ack & ((~error_i)))
             ---------------1--------------   ------------2-----------   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T4
1	1	1	Covered	T1,T2,T3

 LINE       145
 EXPRESSION (tl_i.a_valid & ((~&tl_i.a_mask)) & gen_integ_handling.wr_txn)
             ------1-----   --------2--------   ------------3------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION (gen_integ_handling.rdback_data_exp_q == tl_sram_i.d_data)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       266
 EXPRESSION (((!gen_integ_handling.rdback_chk_ok)) && ((!error_i)))
             ------------------1------------------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T24,T25
1	0	Not Covered
1	1	Not Covered

 LINE       281
 EXPRESSION (gen_integ_handling.wr_txn ? StWrReadBackInit : StRdReadBack)
             ------------1------------

-1-	Status	Tests
0	Covered	T3,T45,T46
1	Covered	T3,T24,T25

 LINE       297
 EXPRESSION (gen_integ_handling.pending_txn_cnt == 2'(1))
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       330
 EXPRESSION (gen_integ_handling.pending_txn_cnt == 2'(1))
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T47
1	Covered	T3,T24,T25

 LINE       395
 EXPRESSION (gen_integ_handling.pending_txn_cnt == 2'(1))
            ----------------------1----------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T3,T46,T48

 LINE       459
 EXPRESSION (gen_integ_handling.pending_txn_cnt == 2'(1))
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T47
1	Covered	T3,T45,T46

 LINE       517
 EXPRESSION (gen_integ_handling.hold_tx_data | gen_integ_handling.byte_req_ack)
             ---------------1---------------   ---------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T24,T25

 LINE       542
 EXPRESSION (gen_integ_handling.sram_d_ack && gen_integ_handling.rd_wait)
             --------------1--------------    -------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       554
 EXPRESSION (gen_integ_handling.held_data.a_mask[i] ? gen_integ_handling.held_data.a_data[(i * 8)+:8] : gen_integ_handling.rsp_data[(i * 8)+:8])
             -------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       581
 EXPRESSION (tl_i.d_ready | gen_integ_handling.rd_wait | gen_integ_handling.rdback_wait)
             ------1-----   -------------2------------   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T24,T48,T49
0	1	0	Covered	T1,T2,T4
1	0	0	Covered	T1,T2,T3

 LINE       590
 EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase | gen_integ_handling.rdback_phase_wrreadback)
             -------------1-------------   ---------------2---------------   ---------------------3--------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T3,T46,T48
0	1	0	Covered	T3,T24,T25
1	0	0	Covered	T1,T2,T3

 LINE       593
 EXPRESSION (gen_integ_handling.wr_phase ? PutFullData : Get)
             -------------1-------------

-1-	Status	Tests
0	Covered	T3,T24,T25
1	Covered	T1,T2,T3

 LINE       596
 EXPRESSION 
 Number  Term
      1  (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback) ? (2'(gen_integ_handling.AccessSize)) : gen_integ_handling.held_data.a_size)

-1-	Status	Tests
0	Covered	T3,T24,T25
1	Covered	T1,T2,T3

 LINE       596
 SUB-EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)
                 -------------1-------------   ---------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T24,T25
0	1	Covered	T3,T46,T48
1	0	Covered	T1,T2,T3

 LINE       598
 EXPRESSION ((gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback) ? ('{(*adjust*)default:'1}) : gen_integ_handling.held_data.a_mask)
             -------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T3,T24,T25
1	Covered	T1,T2,T3

 LINE       598
 SUB-EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)
                 -------------1-------------   ---------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T24,T25
0	1	Covered	T3,T46,T48
1	0	Covered	T1,T2,T3

 LINE       603
 EXPRESSION 
 Number  Term
      1  (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback) ? '0 : gen_integ_handling.held_data.a_address[(gen_integ_handling.AccessSize - 1):0])

-1-	Status	Tests
0	Covered	T3,T24,T25
1	Covered	T1,T2,T3

 LINE       603
 SUB-EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)
                 -------------1-------------   ---------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T24,T25
0	1	Covered	T3,T46,T48
1	0	Covered	T1,T2,T3

 LINE       607
 EXPRESSION (gen_integ_handling.wr_phase ? gen_integ_handling.combined_data : '0)
             -------------1-------------

-1-	Status	Tests
0	Covered	T3,T24,T25
1	Covered	T1,T2,T3

 LINE       608
 EXPRESSION (gen_integ_handling.wr_phase ? gen_integ_handling.combined_user : '0)
             -------------1-------------

-1-	Status	Tests
0	Covered	T3,T24,T25
1	Covered	T1,T2,T3

 LINE       614
 EXPRESSION (((!error_i)) || gen_integ_handling.stall_host)
             ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       620
 EXPRESSION (tl_i.a_valid & ((~gen_integ_handling.stall_host)))
             ------1-----   -----------------2----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       633
 EXPRESSION (error_i & ((~gen_integ_handling.stall_host)))
             ---1---   -----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       661
 EXPRESSION (tl_sram_i.a_ready & ((~gen_integ_handling.stall_host)) & gen_integ_handling.fifo_rdy & gen_integ_handling.size_fifo_rdy)
             --------1--------   -----------------2----------------   -------------3-------------   ----------------4---------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T3,T46,T48
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T2,T3

 LINE       665
 EXPRESSION (tl_sram_i.d_valid & ((~gen_integ_handling.rd_wait)) & ((~gen_integ_handling.rdback_wait)))
             --------1--------   ---------------2---------------   -----------------3-----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T3,T24,T25
1	1	1	Covered	T1,T2,T3

 LINE       699
 EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase | gen_integ_handling.rdback_phase_wrreadback)
             -------------1-------------   ---------------2---------------   ---------------------3--------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T3,T46,T48
0	1	0	Covered	T3,T24,T25
1	0	0	Covered	T1,T2,T3

---

FSM Coverage for Module : tlul_sram_byte

Summary for FSM :: gen_integ_handling.state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	17	17	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: gen_integ_handling.state_q

---

states	Line No.	Covered	Tests
StByteWrReadBack	403	Covered	T3,T46,T48
StByteWrReadBackDWait	409	Covered	T48,T50,T51
StByteWrReadBackInit	310	Covered	T3,T46,T48
StPassThru	310	Covered	T1,T2,T3
StRdReadBack	281	Covered	T3,T46,T48
StRdReadBackDWait	470	Covered	T48,T49,T52
StWaitRd	274	Covered	T1,T2,T3
StWrReadBack	340	Covered	T3,T24,T25
StWrReadBackDWait	343	Covered	T48,T49,T52
StWrReadBackInit	281	Covered	T3,T24,T25
StWriteCmd	300	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StByteWrReadBack->StPassThru	426	Covered	T3,T46,T48
StByteWrReadBackDWait->StByteWrReadBack	443	Covered	T48,T50,T51
StByteWrReadBackInit->StByteWrReadBack	403	Covered	T3,T46,T48
StByteWrReadBackInit->StByteWrReadBackDWait	409	Covered	T48,T50,T51
StPassThru->StRdReadBack	281	Covered	T3,T46,T48
StPassThru->StWaitRd	274	Covered	T1,T2,T3
StPassThru->StWrReadBackInit	281	Covered	T3,T24,T25
StRdReadBack->StPassThru	463	Covered	T3,T46,T48
StRdReadBack->StRdReadBackDWait	470	Covered	T48,T49,T52
StRdReadBackDWait->StPassThru	486	Covered	T48,T49,T52
StWaitRd->StWriteCmd	300	Covered	T1,T2,T3
StWrReadBack->StPassThru	359	Covered	T3,T24,T25
StWrReadBackDWait->StWrReadBack	378	Covered	T48,T49,T52
StWrReadBackInit->StWrReadBack	340	Covered	T3,T24,T25
StWrReadBackInit->StWrReadBackDWait	343	Covered	T48,T49,T52
StWriteCmd->StByteWrReadBackInit	310	Covered	T3,T46,T48
StWriteCmd->StPassThru	310	Covered	T1,T2,T5

---

Branch Coverage for Module : tlul_sram_byte

	Line No.	Total	Covered	Percent
Branches		61	56	91.80
IF	105	2	2	100.00
CASE	255	39	34	87.18
IF	542	2	2	100.00
TERNARY	554	2	2	100.00
IF	590	16	16	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	105	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	255	case (gen_integ_handling.state_q)
-2-:	257	if ((prim_mubi_pkg::mubi4_test_true_loose(gen_integ_handling.rdback_en_q) && prim_mubi_pkg::mubi4_test_true_loose(gen_integ_handling.rdback_check_q)))
-3-:	266	if (((!gen_integ_handling.rdback_chk_ok) && (!error_i)))
-4-:	271	if (gen_integ_handling.byte_wr_txn)
-5-:	273	if (gen_integ_handling.byte_req_ack)
-6-:	276	if (((gen_integ_handling.a_ack && prim_mubi_pkg::mubi4_test_true_loose(gen_integ_handling.rdback_en_q)) && (!error_i)))
-7-:	281	(gen_integ_handling.wr_txn) ? 
-8-:	284	if ((((!tl_sram_o.a_valid) && (!tl_o.d_valid)) && prim_mubi_pkg::mubi4_test_false_strict(gen_integ_handling.rdback_check_q)))
-9-:	297	if ((gen_integ_handling.pending_txn_cnt == 2'(1)))
-10-:	299	if (gen_integ_handling.sram_d_ack)
-11-:	309	if (gen_integ_handling.sram_a_ack)
-12-:	320	if ((EnableReadback == 1'b0))
-13-:	330	if ((gen_integ_handling.pending_txn_cnt == 2'(1)))
-14-:	337	if (gen_integ_handling.d_ack)
-15-:	350	if ((EnableReadback == 1'b0))
-16-:	365	if ((EnableReadback == 1'b0))
-17-:	375	if (gen_integ_handling.d_ack)
-18-:	385	if ((EnableReadback == 1'b0))
-19-:	395	if ((gen_integ_handling.pending_txn_cnt == 2'(1)))
-20-:	400	if (gen_integ_handling.d_ack)
-21-:	417	if ((EnableReadback == 1'b0))
-22-:	430	if ((EnableReadback == 1'b0))
-23-:	440	if (gen_integ_handling.d_ack)
-24-:	448	if ((EnableReadback == 1'b0))
-25-:	459	if ((gen_integ_handling.pending_txn_cnt == 2'(1)))
-26-:	462	if (gen_integ_handling.d_ack)
-27-:	476	if ((EnableReadback == 1'b0))
-28-:	483	if (gen_integ_handling.d_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	-22-	-23-	-24-	-25-	-26-	-27-	-28-	Status	Tests
StPassThru	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StPassThru	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T24,T25
StPassThru	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPassThru	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPassThru	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
StPassThru	-	-	0	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T24,T25
StPassThru	-	-	0	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T45,T46
StPassThru	-	-	0	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPassThru	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPassThru	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StWaitRd	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StWaitRd	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StWaitRd	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
StWriteCmd	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StWriteCmd	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StWrReadBackInit	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
StWrReadBackInit	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T24,T25
StWrReadBackInit	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T24,T25
StWrReadBackInit	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T24,T45,T48
StWrReadBackInit	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T47
StWrReadBack	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
StWrReadBack	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T24,T25
StWrReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
StWrReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T48,T49,T52
StWrReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T48,T49,T52
StWrReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T48,T49,T52
StByteWrReadBackInit	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Unreachable
StByteWrReadBackInit	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T3,T46,T48
StByteWrReadBackInit	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	Covered	T3,T46,T48
StByteWrReadBackInit	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	Covered	T48,T50,T53
StByteWrReadBackInit	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Not Covered
StByteWrReadBack	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Unreachable
StByteWrReadBack	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T3,T46,T48
StByteWrReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Unreachable
StByteWrReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T48,T50,T51
StByteWrReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T48,T50,T51
StByteWrReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T48,T50,T51
StRdReadBack	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Unreachable
StRdReadBack	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T3,T45,T46
StRdReadBack	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T3,T45,T46
StRdReadBack	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T45,T48,T49
StRdReadBack	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	Covered	T47
StRdReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Unreachable
StRdReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T48,T49,T52
StRdReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T48,T49,T52
StRdReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T48,T49,T52
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	542	if ((gen_integ_handling.sram_d_ack && gen_integ_handling.rd_wait))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	554	(gen_integ_handling.held_data.a_mask[i]) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	590	if (((gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase) | gen_integ_handling.rdback_phase_wrreadback))
-2-:	593	(gen_integ_handling.wr_phase) ? 
-3-:	596	((gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)) ? 
-4-:	598	((gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)) ? 
-5-:	603	((gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)) ? 
-6-:	607	(gen_integ_handling.wr_phase) ? 
-7-:	608	(gen_integ_handling.wr_phase) ? 
-8-:	610	if (gen_integ_handling.rd_phase)
-9-:	614	if (((!error_i) || gen_integ_handling.stall_host))
-10-:	623	if (gen_integ_handling.wait_phase)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	Status	Tests
1	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
1	0	-	-	-	-	-	-	-	-	Covered	T3,T24,T25
1	-	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
1	-	0	-	-	-	-	-	-	-	Covered	T3,T24,T25
1	-	-	1	-	-	-	-	-	-	Covered	T1,T2,T3
1	-	-	0	-	-	-	-	-	-	Covered	T3,T24,T25
1	-	-	-	1	-	-	-	-	-	Covered	T1,T2,T3
1	-	-	-	0	-	-	-	-	-	Covered	T3,T24,T25
1	-	-	-	-	1	-	-	-	-	Covered	T1,T2,T3
1	-	-	-	-	0	-	-	-	-	Covered	T3,T24,T25
1	-	-	-	-	-	1	-	-	-	Covered	T1,T2,T3
1	-	-	-	-	-	0	-	-	-	Covered	T3,T24,T25
0	-	-	-	-	-	-	1	1	-	Covered	T1,T2,T3
0	-	-	-	-	-	-	1	0	-	Covered	T1,T2,T4
0	-	-	-	-	-	-	0	-	1	Covered	T3,T24,T25
0	-	-	-	-	-	-	0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : tlul_sram_byte

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SramReadbackAndIntg	901	901	0	0
gen_integ_handling.ByteAccessStateChange_A	1098044706	7264156	0	0
gen_integ_handling.ReadCompleteStateChange_A	1098044706	7264156	0	0
gen_integ_handling.ReadbackAccessAlwaysGranted_A	1098044706	2323143	0	0
gen_integ_handling.ReadbackDataImmediatelyAvailable_A	1098044706	3289933	0	0
gen_integ_handling.TlulSramByteTlSize_A	1098044706	1097933582	0	0
gen_integ_handling.gen_readback_logic.NoPendingWriteAfterWrite_A	1098044706	491522	0	0
gen_integ_handling.gen_readback_logic.WRCollisionDuringReadBack_A	1098044706	5631192	0	0

SramReadbackAndIntg

Name	Attempts	Real Successes	Failures	Incomplete
Total	901	901	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

gen_integ_handling.ByteAccessStateChange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1098044706	7264156	0	0
T1	351405	565	0	0
T2	204360	4085	0	0
T3	243149	27776	0	0
T4	707699	987	0	0
T5	786432	112795	0	0
T9	73974	568	0	0
T10	78282	228	0	0
T11	68749	130	0	0
T12	786	0	0	0
T13	372880	8205	0	0
T41	0	96633	0	0

gen_integ_handling.ReadCompleteStateChange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1098044706	7264156	0	0
T1	351405	565	0	0
T2	204360	4085	0	0
T3	243149	27776	0	0
T4	707699	987	0	0
T5	786432	112795	0	0
T9	73974	568	0	0
T10	78282	228	0	0
T11	68749	130	0	0
T12	786	0	0	0
T13	372880	8205	0	0
T41	0	96633	0	0

gen_integ_handling.ReadbackAccessAlwaysGranted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1098044706	2323143	0	0
T3	243149	59228	0	0
T4	707699	0	0	0
T5	786432	0	0	0
T9	73974	0	0	0
T10	78282	0	0	0
T11	68749	0	0	0
T12	786	0	0	0
T13	372880	0	0	0
T24	0	123	0	0
T25	0	3196	0	0
T41	172648	0	0	0
T45	0	131070	0	0
T46	0	28867	0	0
T48	0	20026	0	0
T49	0	5987	0	0
T52	0	5591	0	0
T54	0	131070	0	0
T55	0	3854	0	0
T56	48313	0	0	0

gen_integ_handling.ReadbackDataImmediatelyAvailable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1098044706	3289933	0	0
T3	243149	59105	0	0
T4	707699	0	0	0
T5	786432	0	0	0
T9	73974	0	0	0
T10	78282	0	0	0
T11	68749	0	0	0
T12	786	0	0	0
T13	372880	0	0	0
T24	0	273	0	0
T25	0	3196	0	0
T41	172648	0	0	0
T45	0	196605	0	0
T46	0	28726	0	0
T48	0	33288	0	0
T49	0	14926	0	0
T52	0	14155	0	0
T54	0	196605	0	0
T55	0	9349	0	0
T56	48313	0	0	0

gen_integ_handling.TlulSramByteTlSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1098044706	1097933582	0	0
T1	351405	351319	0	0
T2	204360	204354	0	0
T3	243149	243050	0	0
T4	707699	707635	0	0
T5	786432	786344	0	0
T9	73974	73881	0	0
T10	78282	78192	0	0
T11	68749	68673	0	0
T12	786	724	0	0
T13	372880	372792	0	0

gen_integ_handling.gen_readback_logic.NoPendingWriteAfterWrite_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1098044706	491522	0	0
T3	243149	27776	0	0
T4	707699	0	0	0
T5	786432	0	0	0
T9	73974	0	0	0
T10	78282	0	0	0
T11	68749	0	0	0
T12	786	0	0	0
T13	372880	0	0	0
T41	172648	0	0	0
T46	0	13774	0	0
T48	0	27278	0	0
T50	0	14527	0	0
T51	0	14051	0	0
T53	0	13861	0	0
T56	48313	0	0	0
T57	0	13884	0	0
T58	0	27395	0	0
T59	0	27632	0	0
T60	0	871	0	0

gen_integ_handling.gen_readback_logic.WRCollisionDuringReadBack_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1098044706	5631192	0	0
T3	243149	60772	0	0
T4	707699	0	0	0
T5	786432	0	0	0
T9	73974	0	0	0
T10	78282	0	0	0
T11	68749	0	0	0
T12	786	0	0	0
T13	372880	0	0	0
T24	0	1483	0	0
T25	0	3198	0	0
T41	172648	0	0	0
T45	0	196606	0	0
T46	0	30430	0	0
T48	0	59497	0	0
T49	0	97831	0	0
T52	0	93064	0	0
T54	0	196606	0	0
T55	0	61852	0	0
T56	48313	0	0	0

Line Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte

	Line No.	Total	Covered	Percent
TOTAL		145	144	99.31
ALWAYS	105	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
ALWAYS	239	95	94	98.95
CONT_ASSIGN	506	1	1	100.00
CONT_ASSIGN	517	1	1	100.00
ALWAYS	542	2	2	100.00
ALWAYS	553	0	0
ALWAYS	553	2	2	100.00
ALWAYS	572	2	2	100.00
ALWAYS	579	22	22	100.00
CONT_ASSIGN	633	1	1	100.00
ALWAYS	658	4	4	100.00
CONT_ASSIGN	676	1	1	100.00
CONT_ASSIGN	699	1	1	100.00
CONT_ASSIGN	716	1	1	100.00
CONT_ASSIGN	717	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
105	1	1
106	1	1
108	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
145	1	1
156	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
253	1	1
255	1	1
257	1	1
262	1	1
263	1	1
266	1	1
267	0	1
			MISSING_ELSE
			MISSING_ELSE
271	1	1
272	1	1
273	1	1
274	1	1
			MISSING_ELSE
276	1	1
280	1	1
281	1	1
			MISSING_ELSE
284	1	1
287	1	1
			MISSING_ELSE
295	1	1
296	1	1
297	1	1
298	1	1
299	1	1
300	1	1
			==> MISSING_ELSE
			MISSING_ELSE
306	1	1
307	1	1
309	1	1
310	1	1
311	1	1
312	1	1
313	1	1
			==> MISSING_ELSE
320	1	1
322		unreachable
			MISSING_ELSE
326	1	1
330	1	1
331	1	1
334	1	1
335	1	1
336	1	1
337	1	1
340	1	1
343	1	1
			MISSING_ELSE
350	1	1
352		unreachable
			MISSING_ELSE
355	1	1
357	1	1
359	1	1
365	1	1
367		unreachable
			MISSING_ELSE
371	1	1
373	1	1
375	1	1
378	1	1
			MISSING_ELSE
385	1	1
387		unreachable
			MISSING_ELSE
392	1	1
395	1	1
398	1	1
400	1	1
403	1	1
409	1	1
			==> MISSING_ELSE
417	1	1
419		unreachable
			MISSING_ELSE
422	1	1
424	1	1
426	1	1
430	1	1
432		unreachable
			MISSING_ELSE
435	1	1
438	1	1
440	1	1
443	1	1
			MISSING_ELSE
448	1	1
450		unreachable
			MISSING_ELSE
455	1	1
459	1	1
460	1	1
462	1	1
463	1	1
465	1	1
466	1	1
467	1	1
470	1	1
			MISSING_ELSE
476	1	1
478		unreachable
			MISSING_ELSE
481	1	1
483	1	1
486	1	1
488	1	1
489	1	1
490	1	1
			MISSING_ELSE
506	1	1
517	1	1
542	1	1
543	1	1
			MISSING_ELSE
553	1	1
554	1	1
572	1	1
573	1	1
579	1	1
581	1	1
590	1	1
591	1	1
593	1	1
596	1	1
598	1	1
602	1	1
603	1	1
605	1	1
606	1	1
607	1	1
608	1	1
610	1	1
612	1	1
614	1	1
617	1	1
618	1	1
620	1	1
621	1	1
			MISSING_ELSE
623	1	1
626	1	1
			MISSING_ELSE
633	1	1
658	1	1
661	1	1
665	1	1
670	1	1
676	1	1
699	1	1
716	1	1
717	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte

	Total	Covered	Percent
Conditions	97	93	95.88
Logical	97	93	95.88
Non-Logical	0	0
Event	0	0

 LINE       138
 EXPRESSION (tl_i.a_valid & tl_o.a_ready)
             ------1-----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       139
 EXPRESSION (tl_o.d_valid & tl_i.d_ready)
             ------1-----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       140
 EXPRESSION (tl_sram_o.a_valid & tl_sram_i.a_ready)
             --------1--------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       141
 EXPRESSION (tl_sram_i.d_valid & tl_sram_o.d_ready)
             --------1--------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       142
 EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData))
             ---------------1--------------   ----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       142
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       142
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (gen_integ_handling.byte_wr_txn & gen_integ_handling.a_ack & ((~error_i)))
             ---------------1--------------   ------------2-----------   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T4
1	1	1	Covered	T1,T2,T3

 LINE       145
 EXPRESSION (tl_i.a_valid & ((~&tl_i.a_mask)) & gen_integ_handling.wr_txn)
             ------1-----   --------2--------   ------------3------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION (gen_integ_handling.rdback_data_exp_q == tl_sram_i.d_data)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       266
 EXPRESSION (((!gen_integ_handling.rdback_chk_ok)) && ((!error_i)))
             ------------------1------------------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T24,T25
1	0	Not Covered
1	1	Not Covered

 LINE       281
 EXPRESSION (gen_integ_handling.wr_txn ? StWrReadBackInit : StRdReadBack)
             ------------1------------

-1-	Status	Tests
0	Covered	T3,T45,T46
1	Covered	T3,T24,T25

 LINE       297
 EXPRESSION (gen_integ_handling.pending_txn_cnt == 2'(1))
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       330
 EXPRESSION (gen_integ_handling.pending_txn_cnt == 2'(1))
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T47
1	Covered	T3,T24,T25

 LINE       395
 EXPRESSION (gen_integ_handling.pending_txn_cnt == 2'(1))
            ----------------------1----------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T3,T46,T48

 LINE       459
 EXPRESSION (gen_integ_handling.pending_txn_cnt == 2'(1))
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T47
1	Covered	T3,T45,T46

 LINE       517
 EXPRESSION (gen_integ_handling.hold_tx_data | gen_integ_handling.byte_req_ack)
             ---------------1---------------   ---------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T24,T25

 LINE       542
 EXPRESSION (gen_integ_handling.sram_d_ack && gen_integ_handling.rd_wait)
             --------------1--------------    -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		[UNR] this should not happen because the read latency of prim_ram_1p_scr is always 1 cycle
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       554
 EXPRESSION (gen_integ_handling.held_data.a_mask[i] ? gen_integ_handling.held_data.a_data[(i * 8)+:8] : gen_integ_handling.rsp_data[(i * 8)+:8])
             -------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       581
 EXPRESSION (tl_i.d_ready | gen_integ_handling.rd_wait | gen_integ_handling.rdback_wait)
             ------1-----   -------------2------------   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T24,T48,T49
0	1	0	Covered	T1,T2,T4
1	0	0	Covered	T1,T2,T3

 LINE       590
 EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase | gen_integ_handling.rdback_phase_wrreadback)
             -------------1-------------   ---------------2---------------   ---------------------3--------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T3,T46,T48
0	1	0	Covered	T3,T24,T25
1	0	0	Covered	T1,T2,T3

 LINE       593
 EXPRESSION (gen_integ_handling.wr_phase ? PutFullData : Get)
             -------------1-------------

-1-	Status	Tests
0	Covered	T3,T24,T25
1	Covered	T1,T2,T3

 LINE       596
 EXPRESSION 
 Number  Term
      1  (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback) ? (2'(gen_integ_handling.AccessSize)) : gen_integ_handling.held_data.a_size)

-1-	Status	Tests
0	Covered	T3,T24,T25
1	Covered	T1,T2,T3

 LINE       596
 SUB-EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)
                 -------------1-------------   ---------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T24,T25
0	1	Covered	T3,T46,T48
1	0	Covered	T1,T2,T3

 LINE       598
 EXPRESSION ((gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback) ? ('{(*adjust*)default:'1}) : gen_integ_handling.held_data.a_mask)
             -------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T3,T24,T25
1	Covered	T1,T2,T3

 LINE       598
 SUB-EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)
                 -------------1-------------   ---------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T24,T25
0	1	Covered	T3,T46,T48
1	0	Covered	T1,T2,T3

 LINE       603
 EXPRESSION 
 Number  Term
      1  (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback) ? '0 : gen_integ_handling.held_data.a_address[(gen_integ_handling.AccessSize - 1):0])

-1-	Status	Tests
0	Covered	T3,T24,T25
1	Covered	T1,T2,T3

 LINE       603
 SUB-EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)
                 -------------1-------------   ---------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T24,T25
0	1	Covered	T3,T46,T48
1	0	Covered	T1,T2,T3

 LINE       607
 EXPRESSION (gen_integ_handling.wr_phase ? gen_integ_handling.combined_data : '0)
             -------------1-------------

-1-	Status	Tests
0	Covered	T3,T24,T25
1	Covered	T1,T2,T3

 LINE       608
 EXPRESSION (gen_integ_handling.wr_phase ? gen_integ_handling.combined_user : '0)
             -------------1-------------

-1-	Status	Tests
0	Covered	T3,T24,T25
1	Covered	T1,T2,T3

 LINE       614
 EXPRESSION (((!error_i)) || gen_integ_handling.stall_host)
             ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       620
 EXPRESSION (tl_i.a_valid & ((~gen_integ_handling.stall_host)))
             ------1-----   -----------------2----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       633
 EXPRESSION (error_i & ((~gen_integ_handling.stall_host)))
             ---1---   -----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       661
 EXPRESSION (tl_sram_i.a_ready & ((~gen_integ_handling.stall_host)) & gen_integ_handling.fifo_rdy & gen_integ_handling.size_fifo_rdy)
             --------1--------   -----------------2----------------   -------------3-------------   ----------------4---------------

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Excluded	T3,T46,T48	VC_COV_UNR
1	1	0	1	Excluded		VC_COV_UNR
1	1	1	0	Excluded		VC_COV_UNR
1	1	1	1	Covered	T1,T2,T3

 LINE       665
 EXPRESSION (tl_sram_i.d_valid & ((~gen_integ_handling.rd_wait)) & ((~gen_integ_handling.rdback_wait)))
             --------1--------   ---------------2---------------   -----------------3-----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T3,T24,T25
1	1	1	Covered	T1,T2,T3

 LINE       699
 EXPRESSION (gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase | gen_integ_handling.rdback_phase_wrreadback)
             -------------1-------------   ---------------2---------------   ---------------------3--------------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T3,T46,T48
0	1	0	Covered	T3,T24,T25
1	0	0	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte

Summary for FSM :: gen_integ_handling.state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	17	17	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: gen_integ_handling.state_q

---

states	Line No.	Covered	Tests
StByteWrReadBack	403	Covered	T3,T46,T48
StByteWrReadBackDWait	409	Covered	T48,T50,T51
StByteWrReadBackInit	310	Covered	T3,T46,T48
StPassThru	310	Covered	T1,T2,T3
StRdReadBack	281	Covered	T3,T46,T48
StRdReadBackDWait	470	Covered	T48,T49,T52
StWaitRd	274	Covered	T1,T2,T3
StWrReadBack	340	Covered	T3,T24,T25
StWrReadBackDWait	343	Covered	T48,T49,T52
StWrReadBackInit	281	Covered	T3,T24,T25
StWriteCmd	300	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StByteWrReadBack->StPassThru	426	Covered	T3,T46,T48
StByteWrReadBackDWait->StByteWrReadBack	443	Covered	T48,T50,T51
StByteWrReadBackInit->StByteWrReadBack	403	Covered	T3,T46,T48
StByteWrReadBackInit->StByteWrReadBackDWait	409	Covered	T48,T50,T51
StPassThru->StRdReadBack	281	Covered	T3,T46,T48
StPassThru->StWaitRd	274	Covered	T1,T2,T3
StPassThru->StWrReadBackInit	281	Covered	T3,T24,T25
StRdReadBack->StPassThru	463	Covered	T3,T46,T48
StRdReadBack->StRdReadBackDWait	470	Covered	T48,T49,T52
StRdReadBackDWait->StPassThru	486	Covered	T48,T49,T52
StWaitRd->StWriteCmd	300	Covered	T1,T2,T3
StWrReadBack->StPassThru	359	Covered	T3,T24,T25
StWrReadBackDWait->StWrReadBack	378	Covered	T48,T49,T52
StWrReadBackInit->StWrReadBack	340	Covered	T3,T24,T25
StWrReadBackInit->StWrReadBackDWait	343	Covered	T48,T49,T52
StWriteCmd->StByteWrReadBackInit	310	Covered	T3,T46,T48
StWriteCmd->StPassThru	310	Covered	T1,T2,T5

---

Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte

	Line No.	Total	Covered	Percent
Branches		61	56	91.80
IF	105	2	2	100.00
CASE	255	39	34	87.18
IF	542	2	2	100.00
TERNARY	554	2	2	100.00
IF	590	16	16	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	105	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	255	case (gen_integ_handling.state_q)
-2-:	257	if ((prim_mubi_pkg::mubi4_test_true_loose(gen_integ_handling.rdback_en_q) && prim_mubi_pkg::mubi4_test_true_loose(gen_integ_handling.rdback_check_q)))
-3-:	266	if (((!gen_integ_handling.rdback_chk_ok) && (!error_i)))
-4-:	271	if (gen_integ_handling.byte_wr_txn)
-5-:	273	if (gen_integ_handling.byte_req_ack)
-6-:	276	if (((gen_integ_handling.a_ack && prim_mubi_pkg::mubi4_test_true_loose(gen_integ_handling.rdback_en_q)) && (!error_i)))
-7-:	281	(gen_integ_handling.wr_txn) ? 
-8-:	284	if ((((!tl_sram_o.a_valid) && (!tl_o.d_valid)) && prim_mubi_pkg::mubi4_test_false_strict(gen_integ_handling.rdback_check_q)))
-9-:	297	if ((gen_integ_handling.pending_txn_cnt == 2'(1)))
-10-:	299	if (gen_integ_handling.sram_d_ack)
-11-:	309	if (gen_integ_handling.sram_a_ack)
-12-:	320	if ((EnableReadback == 1'b0))
-13-:	330	if ((gen_integ_handling.pending_txn_cnt == 2'(1)))
-14-:	337	if (gen_integ_handling.d_ack)
-15-:	350	if ((EnableReadback == 1'b0))
-16-:	365	if ((EnableReadback == 1'b0))
-17-:	375	if (gen_integ_handling.d_ack)
-18-:	385	if ((EnableReadback == 1'b0))
-19-:	395	if ((gen_integ_handling.pending_txn_cnt == 2'(1)))
-20-:	400	if (gen_integ_handling.d_ack)
-21-:	417	if ((EnableReadback == 1'b0))
-22-:	430	if ((EnableReadback == 1'b0))
-23-:	440	if (gen_integ_handling.d_ack)
-24-:	448	if ((EnableReadback == 1'b0))
-25-:	459	if ((gen_integ_handling.pending_txn_cnt == 2'(1)))
-26-:	462	if (gen_integ_handling.d_ack)
-27-:	476	if ((EnableReadback == 1'b0))
-28-:	483	if (gen_integ_handling.d_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	-22-	-23-	-24-	-25-	-26-	-27-	-28-	Status	Tests
StPassThru	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StPassThru	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T24,T25
StPassThru	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPassThru	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPassThru	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
StPassThru	-	-	0	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T24,T25
StPassThru	-	-	0	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T45,T46
StPassThru	-	-	0	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPassThru	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPassThru	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StWaitRd	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StWaitRd	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StWaitRd	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
StWriteCmd	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StWriteCmd	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StWrReadBackInit	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
StWrReadBackInit	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T24,T25
StWrReadBackInit	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T24,T25
StWrReadBackInit	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T24,T45,T48
StWrReadBackInit	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T47
StWrReadBack	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
StWrReadBack	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T24,T25
StWrReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
StWrReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T48,T49,T52
StWrReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T48,T49,T52
StWrReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T48,T49,T52
StByteWrReadBackInit	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Unreachable
StByteWrReadBackInit	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T3,T46,T48
StByteWrReadBackInit	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	Covered	T3,T46,T48
StByteWrReadBackInit	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	Covered	T48,T50,T53
StByteWrReadBackInit	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Not Covered
StByteWrReadBack	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Unreachable
StByteWrReadBack	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T3,T46,T48
StByteWrReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Unreachable
StByteWrReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T48,T50,T51
StByteWrReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T48,T50,T51
StByteWrReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T48,T50,T51
StRdReadBack	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Unreachable
StRdReadBack	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T3,T45,T46
StRdReadBack	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T3,T45,T46
StRdReadBack	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T45,T48,T49
StRdReadBack	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	Covered	T47
StRdReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Unreachable
StRdReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T48,T49,T52
StRdReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T48,T49,T52
StRdReadBackDWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T48,T49,T52
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	542	if ((gen_integ_handling.sram_d_ack && gen_integ_handling.rd_wait))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	554	(gen_integ_handling.held_data.a_mask[i]) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	590	if (((gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase) | gen_integ_handling.rdback_phase_wrreadback))
-2-:	593	(gen_integ_handling.wr_phase) ? 
-3-:	596	((gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)) ? 
-4-:	598	((gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)) ? 
-5-:	603	((gen_integ_handling.wr_phase | gen_integ_handling.rdback_phase_wrreadback)) ? 
-6-:	607	(gen_integ_handling.wr_phase) ? 
-7-:	608	(gen_integ_handling.wr_phase) ? 
-8-:	610	if (gen_integ_handling.rd_phase)
-9-:	614	if (((!error_i) || gen_integ_handling.stall_host))
-10-:	623	if (gen_integ_handling.wait_phase)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	Status	Tests
1	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
1	0	-	-	-	-	-	-	-	-	Covered	T3,T24,T25
1	-	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
1	-	0	-	-	-	-	-	-	-	Covered	T3,T24,T25
1	-	-	1	-	-	-	-	-	-	Covered	T1,T2,T3
1	-	-	0	-	-	-	-	-	-	Covered	T3,T24,T25
1	-	-	-	1	-	-	-	-	-	Covered	T1,T2,T3
1	-	-	-	0	-	-	-	-	-	Covered	T3,T24,T25
1	-	-	-	-	1	-	-	-	-	Covered	T1,T2,T3
1	-	-	-	-	0	-	-	-	-	Covered	T3,T24,T25
1	-	-	-	-	-	1	-	-	-	Covered	T1,T2,T3
1	-	-	-	-	-	0	-	-	-	Covered	T3,T24,T25
0	-	-	-	-	-	-	1	1	-	Covered	T1,T2,T3
0	-	-	-	-	-	-	1	0	-	Covered	T1,T2,T4
0	-	-	-	-	-	-	0	-	1	Covered	T3,T24,T25
0	-	-	-	-	-	-	0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SramReadbackAndIntg	901	901	0	0
gen_integ_handling.ByteAccessStateChange_A	1098044706	7264156	0	0
gen_integ_handling.ReadCompleteStateChange_A	1098044706	7264156	0	0
gen_integ_handling.ReadbackAccessAlwaysGranted_A	1098044706	2323143	0	0
gen_integ_handling.ReadbackDataImmediatelyAvailable_A	1098044706	3289933	0	0
gen_integ_handling.TlulSramByteTlSize_A	1098044706	1097933582	0	0
gen_integ_handling.gen_readback_logic.NoPendingWriteAfterWrite_A	1098044706	491522	0	0
gen_integ_handling.gen_readback_logic.WRCollisionDuringReadBack_A	1098044706	5631192	0	0

SramReadbackAndIntg

Name	Attempts	Real Successes	Failures	Incomplete
Total	901	901	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

gen_integ_handling.ByteAccessStateChange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1098044706	7264156	0	0
T1	351405	565	0	0
T2	204360	4085	0	0
T3	243149	27776	0	0
T4	707699	987	0	0
T5	786432	112795	0	0
T9	73974	568	0	0
T10	78282	228	0	0
T11	68749	130	0	0
T12	786	0	0	0
T13	372880	8205	0	0
T41	0	96633	0	0

gen_integ_handling.ReadCompleteStateChange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1098044706	7264156	0	0
T1	351405	565	0	0
T2	204360	4085	0	0
T3	243149	27776	0	0
T4	707699	987	0	0
T5	786432	112795	0	0
T9	73974	568	0	0
T10	78282	228	0	0
T11	68749	130	0	0
T12	786	0	0	0
T13	372880	8205	0	0
T41	0	96633	0	0

gen_integ_handling.ReadbackAccessAlwaysGranted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1098044706	2323143	0	0
T3	243149	59228	0	0
T4	707699	0	0	0
T5	786432	0	0	0
T9	73974	0	0	0
T10	78282	0	0	0
T11	68749	0	0	0
T12	786	0	0	0
T13	372880	0	0	0
T24	0	123	0	0
T25	0	3196	0	0
T41	172648	0	0	0
T45	0	131070	0	0
T46	0	28867	0	0
T48	0	20026	0	0
T49	0	5987	0	0
T52	0	5591	0	0
T54	0	131070	0	0
T55	0	3854	0	0
T56	48313	0	0	0

gen_integ_handling.ReadbackDataImmediatelyAvailable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1098044706	3289933	0	0
T3	243149	59105	0	0
T4	707699	0	0	0
T5	786432	0	0	0
T9	73974	0	0	0
T10	78282	0	0	0
T11	68749	0	0	0
T12	786	0	0	0
T13	372880	0	0	0
T24	0	273	0	0
T25	0	3196	0	0
T41	172648	0	0	0
T45	0	196605	0	0
T46	0	28726	0	0
T48	0	33288	0	0
T49	0	14926	0	0
T52	0	14155	0	0
T54	0	196605	0	0
T55	0	9349	0	0
T56	48313	0	0	0

gen_integ_handling.TlulSramByteTlSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1098044706	1097933582	0	0
T1	351405	351319	0	0
T2	204360	204354	0	0
T3	243149	243050	0	0
T4	707699	707635	0	0
T5	786432	786344	0	0
T9	73974	73881	0	0
T10	78282	78192	0	0
T11	68749	68673	0	0
T12	786	724	0	0
T13	372880	372792	0	0

gen_integ_handling.gen_readback_logic.NoPendingWriteAfterWrite_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1098044706	491522	0	0
T3	243149	27776	0	0
T4	707699	0	0	0
T5	786432	0	0	0
T9	73974	0	0	0
T10	78282	0	0	0
T11	68749	0	0	0
T12	786	0	0	0
T13	372880	0	0	0
T41	172648	0	0	0
T46	0	13774	0	0
T48	0	27278	0	0
T50	0	14527	0	0
T51	0	14051	0	0
T53	0	13861	0	0
T56	48313	0	0	0
T57	0	13884	0	0
T58	0	27395	0	0
T59	0	27632	0	0
T60	0	871	0	0

gen_integ_handling.gen_readback_logic.WRCollisionDuringReadBack_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1098044706	5631192	0	0
T3	243149	60772	0	0
T4	707699	0	0	0
T5	786432	0	0	0
T9	73974	0	0	0
T10	78282	0	0	0
T11	68749	0	0	0
T12	786	0	0	0
T13	372880	0	0	0
T24	0	1483	0	0
T25	0	3198	0	0
T41	172648	0	0	0
T45	0	196606	0	0
T46	0	30430	0	0
T48	0	59497	0	0
T49	0	97831	0	0
T52	0	93064	0	0
T54	0	196606	0	0
T55	0	61852	0	0
T56	48313	0	0	0