| T807 |
/workspace/coverage/default/2.sram_ctrl_mem_partial_access.1655686687 |
|
|
Jul 11 06:03:02 PM PDT 24 |
Jul 11 06:06:18 PM PDT 24 |
83647164409 ps |
| T808 |
/workspace/coverage/default/38.sram_ctrl_bijection.2855163850 |
|
|
Jul 11 06:05:19 PM PDT 24 |
Jul 11 06:44:15 PM PDT 24 |
106833671822 ps |
| T809 |
/workspace/coverage/default/2.sram_ctrl_executable.4034338916 |
|
|
Jul 11 06:03:04 PM PDT 24 |
Jul 11 06:09:17 PM PDT 24 |
23717879011 ps |
| T810 |
/workspace/coverage/default/8.sram_ctrl_mem_walk.505979387 |
|
|
Jul 11 06:03:28 PM PDT 24 |
Jul 11 06:09:00 PM PDT 24 |
14373372024 ps |
| T811 |
/workspace/coverage/default/48.sram_ctrl_mem_walk.2087314168 |
|
|
Jul 11 06:06:39 PM PDT 24 |
Jul 11 06:12:15 PM PDT 24 |
18692913513 ps |
| T812 |
/workspace/coverage/default/4.sram_ctrl_stress_pipeline.2388604841 |
|
|
Jul 11 06:03:02 PM PDT 24 |
Jul 11 06:07:21 PM PDT 24 |
14116834143 ps |
| T119 |
/workspace/coverage/default/4.sram_ctrl_alert_test.2332916991 |
|
|
Jul 11 06:03:06 PM PDT 24 |
Jul 11 06:03:24 PM PDT 24 |
14309633 ps |
| T120 |
/workspace/coverage/default/15.sram_ctrl_access_during_key_req.2421550190 |
|
|
Jul 11 06:03:43 PM PDT 24 |
Jul 11 06:10:31 PM PDT 24 |
11187622468 ps |
| T121 |
/workspace/coverage/default/24.sram_ctrl_partial_access_b2b.160582423 |
|
|
Jul 11 06:04:05 PM PDT 24 |
Jul 11 06:09:18 PM PDT 24 |
4672172021 ps |
| T122 |
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.3106402433 |
|
|
Jul 11 06:06:38 PM PDT 24 |
Jul 11 06:12:48 PM PDT 24 |
17289223478 ps |
| T123 |
/workspace/coverage/default/19.sram_ctrl_access_during_key_req.919569836 |
|
|
Jul 11 06:03:56 PM PDT 24 |
Jul 11 06:10:39 PM PDT 24 |
14800309510 ps |
| T124 |
/workspace/coverage/default/21.sram_ctrl_stress_all.4080063811 |
|
|
Jul 11 06:04:00 PM PDT 24 |
Jul 11 08:11:36 PM PDT 24 |
339284392150 ps |
| T125 |
/workspace/coverage/default/29.sram_ctrl_multiple_keys.3231649639 |
|
|
Jul 11 06:04:22 PM PDT 24 |
Jul 11 06:23:52 PM PDT 24 |
17601713022 ps |
| T126 |
/workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.3741767236 |
|
|
Jul 11 06:04:18 PM PDT 24 |
Jul 11 06:04:48 PM PDT 24 |
3344125527 ps |
| T127 |
/workspace/coverage/default/26.sram_ctrl_alert_test.2989466760 |
|
|
Jul 11 06:04:20 PM PDT 24 |
Jul 11 06:04:24 PM PDT 24 |
12226427 ps |
| T128 |
/workspace/coverage/default/32.sram_ctrl_access_during_key_req.3822671378 |
|
|
Jul 11 06:04:41 PM PDT 24 |
Jul 11 06:14:47 PM PDT 24 |
35972457416 ps |
| T813 |
/workspace/coverage/default/49.sram_ctrl_mem_walk.1189506035 |
|
|
Jul 11 06:06:48 PM PDT 24 |
Jul 11 06:11:58 PM PDT 24 |
28210838481 ps |
| T814 |
/workspace/coverage/default/37.sram_ctrl_access_during_key_req.1052685391 |
|
|
Jul 11 06:05:13 PM PDT 24 |
Jul 11 06:15:18 PM PDT 24 |
33662673560 ps |
| T815 |
/workspace/coverage/default/13.sram_ctrl_stress_pipeline.3785910444 |
|
|
Jul 11 06:03:44 PM PDT 24 |
Jul 11 06:10:07 PM PDT 24 |
21756528336 ps |
| T816 |
/workspace/coverage/default/5.sram_ctrl_max_throughput.2761128076 |
|
|
Jul 11 06:03:26 PM PDT 24 |
Jul 11 06:05:06 PM PDT 24 |
771578639 ps |
| T817 |
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.1007464095 |
|
|
Jul 11 06:02:52 PM PDT 24 |
Jul 11 06:09:34 PM PDT 24 |
39667629348 ps |
| T818 |
/workspace/coverage/default/30.sram_ctrl_access_during_key_req.3479059788 |
|
|
Jul 11 06:04:33 PM PDT 24 |
Jul 11 06:20:03 PM PDT 24 |
9141242880 ps |
| T819 |
/workspace/coverage/default/41.sram_ctrl_regwen.2769183371 |
|
|
Jul 11 06:05:46 PM PDT 24 |
Jul 11 06:08:04 PM PDT 24 |
14552683088 ps |
| T820 |
/workspace/coverage/default/4.sram_ctrl_regwen.977212255 |
|
|
Jul 11 06:03:26 PM PDT 24 |
Jul 11 06:15:13 PM PDT 24 |
15987839114 ps |
| T821 |
/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.2798606309 |
|
|
Jul 11 06:03:43 PM PDT 24 |
Jul 11 06:05:30 PM PDT 24 |
767104106 ps |
| T822 |
/workspace/coverage/default/38.sram_ctrl_smoke.236522631 |
|
|
Jul 11 06:05:20 PM PDT 24 |
Jul 11 06:05:43 PM PDT 24 |
396516766 ps |
| T823 |
/workspace/coverage/default/43.sram_ctrl_access_during_key_req.3256733424 |
|
|
Jul 11 06:06:03 PM PDT 24 |
Jul 11 06:14:20 PM PDT 24 |
8860103265 ps |
| T824 |
/workspace/coverage/default/43.sram_ctrl_regwen.619877880 |
|
|
Jul 11 06:06:06 PM PDT 24 |
Jul 11 06:35:53 PM PDT 24 |
97620755358 ps |
| T825 |
/workspace/coverage/default/17.sram_ctrl_smoke.2078578452 |
|
|
Jul 11 06:03:44 PM PDT 24 |
Jul 11 06:04:08 PM PDT 24 |
1476196882 ps |
| T826 |
/workspace/coverage/default/20.sram_ctrl_regwen.2116191159 |
|
|
Jul 11 06:04:00 PM PDT 24 |
Jul 11 06:17:48 PM PDT 24 |
10241741977 ps |
| T827 |
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.2240649018 |
|
|
Jul 11 06:03:24 PM PDT 24 |
Jul 11 06:03:45 PM PDT 24 |
710048063 ps |
| T828 |
/workspace/coverage/default/28.sram_ctrl_mem_partial_access.4201638742 |
|
|
Jul 11 06:04:23 PM PDT 24 |
Jul 11 06:05:31 PM PDT 24 |
2048355028 ps |
| T829 |
/workspace/coverage/default/3.sram_ctrl_ram_cfg.906493231 |
|
|
Jul 11 06:03:11 PM PDT 24 |
Jul 11 06:03:30 PM PDT 24 |
1412317441 ps |
| T830 |
/workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.536962775 |
|
|
Jul 11 06:03:58 PM PDT 24 |
Jul 11 06:04:18 PM PDT 24 |
526246924 ps |
| T831 |
/workspace/coverage/default/11.sram_ctrl_partial_access.4018303042 |
|
|
Jul 11 06:03:19 PM PDT 24 |
Jul 11 06:03:59 PM PDT 24 |
434842381 ps |
| T832 |
/workspace/coverage/default/44.sram_ctrl_regwen.2987758617 |
|
|
Jul 11 06:06:11 PM PDT 24 |
Jul 11 06:17:39 PM PDT 24 |
5571053812 ps |
| T833 |
/workspace/coverage/default/18.sram_ctrl_stress_all.550970212 |
|
|
Jul 11 06:03:52 PM PDT 24 |
Jul 11 08:01:38 PM PDT 24 |
352520866305 ps |
| T834 |
/workspace/coverage/default/42.sram_ctrl_mem_walk.376443343 |
|
|
Jul 11 06:05:55 PM PDT 24 |
Jul 11 06:11:20 PM PDT 24 |
81370023037 ps |
| T835 |
/workspace/coverage/default/29.sram_ctrl_executable.4255037143 |
|
|
Jul 11 06:04:30 PM PDT 24 |
Jul 11 06:16:04 PM PDT 24 |
5298713112 ps |
| T836 |
/workspace/coverage/default/33.sram_ctrl_mem_walk.2213389192 |
|
|
Jul 11 06:04:54 PM PDT 24 |
Jul 11 06:09:56 PM PDT 24 |
27652337942 ps |
| T837 |
/workspace/coverage/default/16.sram_ctrl_multiple_keys.1530494935 |
|
|
Jul 11 06:03:39 PM PDT 24 |
Jul 11 06:26:44 PM PDT 24 |
97383386319 ps |
| T838 |
/workspace/coverage/default/18.sram_ctrl_ram_cfg.4131182099 |
|
|
Jul 11 06:03:56 PM PDT 24 |
Jul 11 06:04:08 PM PDT 24 |
807871742 ps |
| T839 |
/workspace/coverage/default/2.sram_ctrl_max_throughput.1880528297 |
|
|
Jul 11 06:03:13 PM PDT 24 |
Jul 11 06:03:36 PM PDT 24 |
686599364 ps |
| T840 |
/workspace/coverage/default/42.sram_ctrl_stress_all.3628944091 |
|
|
Jul 11 06:05:58 PM PDT 24 |
Jul 11 07:04:38 PM PDT 24 |
179584529452 ps |
| T841 |
/workspace/coverage/default/3.sram_ctrl_max_throughput.3210864600 |
|
|
Jul 11 06:03:00 PM PDT 24 |
Jul 11 06:04:03 PM PDT 24 |
785825119 ps |
| T31 |
/workspace/coverage/default/2.sram_ctrl_sec_cm.2350164995 |
|
|
Jul 11 06:03:04 PM PDT 24 |
Jul 11 06:03:24 PM PDT 24 |
94084484 ps |
| T842 |
/workspace/coverage/default/12.sram_ctrl_multiple_keys.4280683069 |
|
|
Jul 11 06:03:28 PM PDT 24 |
Jul 11 06:05:28 PM PDT 24 |
1721179576 ps |
| T843 |
/workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.1245670178 |
|
|
Jul 11 06:03:45 PM PDT 24 |
Jul 11 06:06:01 PM PDT 24 |
27440827106 ps |
| T844 |
/workspace/coverage/default/34.sram_ctrl_smoke.1060749038 |
|
|
Jul 11 06:04:52 PM PDT 24 |
Jul 11 06:05:26 PM PDT 24 |
422706466 ps |
| T845 |
/workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.1713660724 |
|
|
Jul 11 06:04:11 PM PDT 24 |
Jul 11 06:05:57 PM PDT 24 |
1622624905 ps |
| T846 |
/workspace/coverage/default/25.sram_ctrl_multiple_keys.3003026453 |
|
|
Jul 11 06:04:07 PM PDT 24 |
Jul 11 06:19:53 PM PDT 24 |
63829179707 ps |
| T847 |
/workspace/coverage/default/7.sram_ctrl_multiple_keys.2734750715 |
|
|
Jul 11 06:03:19 PM PDT 24 |
Jul 11 06:21:14 PM PDT 24 |
13980604310 ps |
| T848 |
/workspace/coverage/default/25.sram_ctrl_alert_test.3528322943 |
|
|
Jul 11 06:04:05 PM PDT 24 |
Jul 11 06:04:15 PM PDT 24 |
35926373 ps |
| T849 |
/workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.2943706646 |
|
|
Jul 11 06:03:10 PM PDT 24 |
Jul 11 06:06:36 PM PDT 24 |
2438189539 ps |
| T850 |
/workspace/coverage/default/2.sram_ctrl_bijection.451633790 |
|
|
Jul 11 06:02:57 PM PDT 24 |
Jul 11 06:43:06 PM PDT 24 |
33459401906 ps |
| T851 |
/workspace/coverage/default/4.sram_ctrl_ram_cfg.4099273335 |
|
|
Jul 11 06:03:24 PM PDT 24 |
Jul 11 06:03:40 PM PDT 24 |
1405036368 ps |
| T852 |
/workspace/coverage/default/16.sram_ctrl_ram_cfg.3794043428 |
|
|
Jul 11 06:03:46 PM PDT 24 |
Jul 11 06:04:00 PM PDT 24 |
345690875 ps |
| T853 |
/workspace/coverage/default/41.sram_ctrl_mem_partial_access.410793034 |
|
|
Jul 11 06:05:49 PM PDT 24 |
Jul 11 06:08:00 PM PDT 24 |
1638552459 ps |
| T854 |
/workspace/coverage/default/49.sram_ctrl_ram_cfg.4086223571 |
|
|
Jul 11 06:06:49 PM PDT 24 |
Jul 11 06:06:54 PM PDT 24 |
1410584136 ps |
| T855 |
/workspace/coverage/default/6.sram_ctrl_alert_test.2052995103 |
|
|
Jul 11 06:03:13 PM PDT 24 |
Jul 11 06:03:29 PM PDT 24 |
16189003 ps |
| T856 |
/workspace/coverage/default/2.sram_ctrl_access_during_key_req.421458932 |
|
|
Jul 11 06:02:58 PM PDT 24 |
Jul 11 06:10:00 PM PDT 24 |
2888876930 ps |
| T857 |
/workspace/coverage/default/42.sram_ctrl_mem_partial_access.1598889511 |
|
|
Jul 11 06:05:55 PM PDT 24 |
Jul 11 06:08:57 PM PDT 24 |
5691767998 ps |
| T858 |
/workspace/coverage/default/16.sram_ctrl_partial_access_b2b.902815582 |
|
|
Jul 11 06:03:40 PM PDT 24 |
Jul 11 06:11:29 PM PDT 24 |
66029137527 ps |
| T859 |
/workspace/coverage/default/26.sram_ctrl_ram_cfg.1624118711 |
|
|
Jul 11 06:04:11 PM PDT 24 |
Jul 11 06:04:23 PM PDT 24 |
357973629 ps |
| T860 |
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.2403140134 |
|
|
Jul 11 06:02:53 PM PDT 24 |
Jul 11 06:06:11 PM PDT 24 |
13722395001 ps |
| T861 |
/workspace/coverage/default/44.sram_ctrl_lc_escalation.1690415009 |
|
|
Jul 11 06:06:04 PM PDT 24 |
Jul 11 06:06:59 PM PDT 24 |
9234777397 ps |
| T862 |
/workspace/coverage/default/26.sram_ctrl_max_throughput.1476924800 |
|
|
Jul 11 06:04:12 PM PDT 24 |
Jul 11 06:04:27 PM PDT 24 |
704465354 ps |
| T863 |
/workspace/coverage/default/23.sram_ctrl_stress_all.1393081259 |
|
|
Jul 11 06:03:58 PM PDT 24 |
Jul 11 06:54:40 PM PDT 24 |
291653066936 ps |
| T864 |
/workspace/coverage/default/37.sram_ctrl_mem_partial_access.223354568 |
|
|
Jul 11 06:05:16 PM PDT 24 |
Jul 11 06:06:21 PM PDT 24 |
9648442787 ps |
| T865 |
/workspace/coverage/default/23.sram_ctrl_partial_access_b2b.125596285 |
|
|
Jul 11 06:04:03 PM PDT 24 |
Jul 11 06:11:08 PM PDT 24 |
38197930198 ps |
| T866 |
/workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.2023634078 |
|
|
Jul 11 06:04:08 PM PDT 24 |
Jul 11 06:04:27 PM PDT 24 |
316678935 ps |
| T867 |
/workspace/coverage/default/46.sram_ctrl_smoke.616546088 |
|
|
Jul 11 06:06:13 PM PDT 24 |
Jul 11 06:06:29 PM PDT 24 |
828363901 ps |
| T868 |
/workspace/coverage/default/39.sram_ctrl_lc_escalation.2729685740 |
|
|
Jul 11 06:05:24 PM PDT 24 |
Jul 11 06:06:19 PM PDT 24 |
8528326140 ps |
| T869 |
/workspace/coverage/default/2.sram_ctrl_regwen.131495205 |
|
|
Jul 11 06:02:59 PM PDT 24 |
Jul 11 06:14:55 PM PDT 24 |
95258545679 ps |
| T870 |
/workspace/coverage/default/0.sram_ctrl_lc_escalation.3880376400 |
|
|
Jul 11 06:03:01 PM PDT 24 |
Jul 11 06:03:42 PM PDT 24 |
14380376029 ps |
| T871 |
/workspace/coverage/default/39.sram_ctrl_smoke.2499180345 |
|
|
Jul 11 06:05:25 PM PDT 24 |
Jul 11 06:05:45 PM PDT 24 |
957591502 ps |
| T872 |
/workspace/coverage/default/38.sram_ctrl_regwen.3225104936 |
|
|
Jul 11 06:05:17 PM PDT 24 |
Jul 11 06:21:16 PM PDT 24 |
8317938111 ps |
| T873 |
/workspace/coverage/default/34.sram_ctrl_regwen.2167997787 |
|
|
Jul 11 06:04:59 PM PDT 24 |
Jul 11 06:14:28 PM PDT 24 |
5204890672 ps |
| T874 |
/workspace/coverage/default/45.sram_ctrl_stress_all.2106414991 |
|
|
Jul 11 06:06:13 PM PDT 24 |
Jul 11 08:20:42 PM PDT 24 |
117313033754 ps |
| T875 |
/workspace/coverage/default/0.sram_ctrl_stress_all.459597988 |
|
|
Jul 11 06:02:53 PM PDT 24 |
Jul 11 06:50:27 PM PDT 24 |
240317643151 ps |
| T876 |
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.162193136 |
|
|
Jul 11 06:05:55 PM PDT 24 |
Jul 11 06:10:47 PM PDT 24 |
11693464732 ps |
| T877 |
/workspace/coverage/default/20.sram_ctrl_access_during_key_req.785094946 |
|
|
Jul 11 06:03:55 PM PDT 24 |
Jul 11 06:16:18 PM PDT 24 |
22484224721 ps |
| T878 |
/workspace/coverage/default/18.sram_ctrl_lc_escalation.862603203 |
|
|
Jul 11 06:03:54 PM PDT 24 |
Jul 11 06:05:06 PM PDT 24 |
94594253828 ps |
| T879 |
/workspace/coverage/default/36.sram_ctrl_max_throughput.26685454 |
|
|
Jul 11 06:05:12 PM PDT 24 |
Jul 11 06:07:47 PM PDT 24 |
5093491686 ps |
| T880 |
/workspace/coverage/default/41.sram_ctrl_smoke.1367247336 |
|
|
Jul 11 06:05:43 PM PDT 24 |
Jul 11 06:05:53 PM PDT 24 |
420588914 ps |
| T881 |
/workspace/coverage/default/30.sram_ctrl_mem_partial_access.3039818406 |
|
|
Jul 11 06:04:31 PM PDT 24 |
Jul 11 06:06:45 PM PDT 24 |
6112111472 ps |
| T882 |
/workspace/coverage/default/38.sram_ctrl_multiple_keys.274101654 |
|
|
Jul 11 06:05:18 PM PDT 24 |
Jul 11 06:08:23 PM PDT 24 |
3191631250 ps |
| T883 |
/workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.166749214 |
|
|
Jul 11 06:04:34 PM PDT 24 |
Jul 11 06:04:51 PM PDT 24 |
1792042757 ps |
| T884 |
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.1228581275 |
|
|
Jul 11 06:06:43 PM PDT 24 |
Jul 11 06:07:16 PM PDT 24 |
1573352000 ps |
| T885 |
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.3681507477 |
|
|
Jul 11 06:03:17 PM PDT 24 |
Jul 11 06:04:32 PM PDT 24 |
4871811393 ps |
| T886 |
/workspace/coverage/default/14.sram_ctrl_regwen.3810483421 |
|
|
Jul 11 06:03:40 PM PDT 24 |
Jul 11 06:15:00 PM PDT 24 |
34556305213 ps |
| T887 |
/workspace/coverage/default/7.sram_ctrl_mem_walk.2036839641 |
|
|
Jul 11 06:03:13 PM PDT 24 |
Jul 11 06:06:45 PM PDT 24 |
43124181963 ps |
| T888 |
/workspace/coverage/default/25.sram_ctrl_stress_pipeline.666212155 |
|
|
Jul 11 06:04:07 PM PDT 24 |
Jul 11 06:07:35 PM PDT 24 |
15768117853 ps |
| T889 |
/workspace/coverage/default/23.sram_ctrl_smoke.2793389401 |
|
|
Jul 11 06:04:06 PM PDT 24 |
Jul 11 06:04:35 PM PDT 24 |
15492301833 ps |
| T890 |
/workspace/coverage/default/20.sram_ctrl_bijection.797379105 |
|
|
Jul 11 06:03:59 PM PDT 24 |
Jul 11 06:35:40 PM PDT 24 |
27669916225 ps |
| T891 |
/workspace/coverage/default/30.sram_ctrl_smoke.3394339171 |
|
|
Jul 11 06:04:28 PM PDT 24 |
Jul 11 06:04:37 PM PDT 24 |
1326748594 ps |
| T892 |
/workspace/coverage/default/30.sram_ctrl_lc_escalation.3755771879 |
|
|
Jul 11 06:04:30 PM PDT 24 |
Jul 11 06:05:19 PM PDT 24 |
26933358056 ps |
| T893 |
/workspace/coverage/default/16.sram_ctrl_smoke.3813871208 |
|
|
Jul 11 06:03:46 PM PDT 24 |
Jul 11 06:05:22 PM PDT 24 |
4848385369 ps |
| T894 |
/workspace/coverage/default/43.sram_ctrl_mem_walk.3145509202 |
|
|
Jul 11 06:06:02 PM PDT 24 |
Jul 11 06:10:31 PM PDT 24 |
26272170142 ps |
| T895 |
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.2353805132 |
|
|
Jul 11 06:06:40 PM PDT 24 |
Jul 11 06:11:27 PM PDT 24 |
11807892878 ps |
| T896 |
/workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.1066190641 |
|
|
Jul 11 06:04:24 PM PDT 24 |
Jul 11 06:04:39 PM PDT 24 |
634097342 ps |
| T897 |
/workspace/coverage/default/3.sram_ctrl_alert_test.2575472225 |
|
|
Jul 11 06:03:14 PM PDT 24 |
Jul 11 06:03:30 PM PDT 24 |
49560835 ps |
| T898 |
/workspace/coverage/default/47.sram_ctrl_smoke.1221924197 |
|
|
Jul 11 06:06:26 PM PDT 24 |
Jul 11 06:06:42 PM PDT 24 |
1599339607 ps |
| T899 |
/workspace/coverage/default/20.sram_ctrl_lc_escalation.2338239748 |
|
|
Jul 11 06:03:55 PM PDT 24 |
Jul 11 06:04:55 PM PDT 24 |
26618996870 ps |
| T900 |
/workspace/coverage/default/14.sram_ctrl_ram_cfg.3724557550 |
|
|
Jul 11 06:03:37 PM PDT 24 |
Jul 11 06:03:50 PM PDT 24 |
793187408 ps |
| T901 |
/workspace/coverage/default/22.sram_ctrl_partial_access.3482192966 |
|
|
Jul 11 06:03:59 PM PDT 24 |
Jul 11 06:06:14 PM PDT 24 |
1396395713 ps |
| T902 |
/workspace/coverage/default/24.sram_ctrl_ram_cfg.2902782750 |
|
|
Jul 11 06:04:09 PM PDT 24 |
Jul 11 06:04:21 PM PDT 24 |
561938134 ps |
| T903 |
/workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.3854427225 |
|
|
Jul 11 06:03:59 PM PDT 24 |
Jul 11 06:04:16 PM PDT 24 |
405272534 ps |
| T904 |
/workspace/coverage/default/32.sram_ctrl_ram_cfg.2463390183 |
|
|
Jul 11 06:04:42 PM PDT 24 |
Jul 11 06:04:48 PM PDT 24 |
711060127 ps |
| T905 |
/workspace/coverage/default/46.sram_ctrl_multiple_keys.857102783 |
|
|
Jul 11 06:06:13 PM PDT 24 |
Jul 11 06:27:25 PM PDT 24 |
80154513440 ps |
| T906 |
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.580077790 |
|
|
Jul 11 06:06:47 PM PDT 24 |
Jul 11 06:07:53 PM PDT 24 |
957863983 ps |
| T907 |
/workspace/coverage/default/35.sram_ctrl_smoke.455148046 |
|
|
Jul 11 06:04:58 PM PDT 24 |
Jul 11 06:05:22 PM PDT 24 |
5575905174 ps |
| T136 |
/workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.83383793 |
|
|
Jul 11 06:05:25 PM PDT 24 |
Jul 11 06:06:39 PM PDT 24 |
1305696676 ps |
| T908 |
/workspace/coverage/default/2.sram_ctrl_stress_pipeline.978227352 |
|
|
Jul 11 06:03:02 PM PDT 24 |
Jul 11 06:08:35 PM PDT 24 |
21994523489 ps |
| T909 |
/workspace/coverage/default/14.sram_ctrl_access_during_key_req.662617086 |
|
|
Jul 11 06:03:40 PM PDT 24 |
Jul 11 06:18:54 PM PDT 24 |
50149010298 ps |
| T910 |
/workspace/coverage/default/20.sram_ctrl_stress_all.1296509903 |
|
|
Jul 11 06:03:55 PM PDT 24 |
Jul 11 06:15:35 PM PDT 24 |
39031514246 ps |
| T911 |
/workspace/coverage/default/11.sram_ctrl_regwen.2877575130 |
|
|
Jul 11 06:03:30 PM PDT 24 |
Jul 11 06:18:14 PM PDT 24 |
15564414359 ps |
| T912 |
/workspace/coverage/default/26.sram_ctrl_stress_all.2621310686 |
|
|
Jul 11 06:04:14 PM PDT 24 |
Jul 11 07:02:42 PM PDT 24 |
49639245373 ps |
| T913 |
/workspace/coverage/default/24.sram_ctrl_regwen.2968572143 |
|
|
Jul 11 06:04:06 PM PDT 24 |
Jul 11 06:05:07 PM PDT 24 |
2100892519 ps |
| T914 |
/workspace/coverage/default/10.sram_ctrl_stress_all.1560219619 |
|
|
Jul 11 06:03:18 PM PDT 24 |
Jul 11 06:44:04 PM PDT 24 |
100314053900 ps |
| T915 |
/workspace/coverage/default/19.sram_ctrl_smoke.388033990 |
|
|
Jul 11 06:03:54 PM PDT 24 |
Jul 11 06:04:25 PM PDT 24 |
1407162610 ps |
| T916 |
/workspace/coverage/default/13.sram_ctrl_partial_access_b2b.2396048317 |
|
|
Jul 11 06:03:42 PM PDT 24 |
Jul 11 06:13:15 PM PDT 24 |
319342873120 ps |
| T917 |
/workspace/coverage/default/25.sram_ctrl_stress_all.292382532 |
|
|
Jul 11 06:04:10 PM PDT 24 |
Jul 11 07:10:59 PM PDT 24 |
142276044779 ps |
| T918 |
/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.3981061230 |
|
|
Jul 11 06:04:41 PM PDT 24 |
Jul 11 06:10:46 PM PDT 24 |
19929475386 ps |
| T919 |
/workspace/coverage/default/22.sram_ctrl_mem_walk.1707821353 |
|
|
Jul 11 06:04:00 PM PDT 24 |
Jul 11 06:06:22 PM PDT 24 |
5060021043 ps |
| T920 |
/workspace/coverage/default/34.sram_ctrl_bijection.3068944492 |
|
|
Jul 11 06:04:51 PM PDT 24 |
Jul 11 06:45:08 PM PDT 24 |
33197240161 ps |
| T921 |
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.715063001 |
|
|
Jul 11 06:06:20 PM PDT 24 |
Jul 11 06:08:58 PM PDT 24 |
4952921294 ps |
| T922 |
/workspace/coverage/default/36.sram_ctrl_multiple_keys.1381329111 |
|
|
Jul 11 06:05:09 PM PDT 24 |
Jul 11 06:19:06 PM PDT 24 |
63258873597 ps |
| T923 |
/workspace/coverage/default/40.sram_ctrl_stress_pipeline.1250514242 |
|
|
Jul 11 06:05:45 PM PDT 24 |
Jul 11 06:10:18 PM PDT 24 |
69982046784 ps |
| T924 |
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.2454591703 |
|
|
Jul 11 06:03:30 PM PDT 24 |
Jul 11 06:04:01 PM PDT 24 |
1067315767 ps |
| T925 |
/workspace/coverage/default/17.sram_ctrl_multiple_keys.3280679438 |
|
|
Jul 11 06:03:51 PM PDT 24 |
Jul 11 06:11:10 PM PDT 24 |
12382605057 ps |
| T926 |
/workspace/coverage/default/26.sram_ctrl_lc_escalation.892240135 |
|
|
Jul 11 06:04:09 PM PDT 24 |
Jul 11 06:05:03 PM PDT 24 |
25353039688 ps |
| T927 |
/workspace/coverage/default/24.sram_ctrl_access_during_key_req.3244603593 |
|
|
Jul 11 06:04:07 PM PDT 24 |
Jul 11 06:39:13 PM PDT 24 |
80843450552 ps |
| T928 |
/workspace/coverage/default/30.sram_ctrl_regwen.4150507015 |
|
|
Jul 11 06:04:34 PM PDT 24 |
Jul 11 06:24:39 PM PDT 24 |
15044320083 ps |
| T929 |
/workspace/coverage/default/35.sram_ctrl_stress_pipeline.2273179997 |
|
|
Jul 11 06:05:04 PM PDT 24 |
Jul 11 06:10:08 PM PDT 24 |
8565835650 ps |
| T930 |
/workspace/coverage/default/19.sram_ctrl_stress_all.3307519030 |
|
|
Jul 11 06:03:59 PM PDT 24 |
Jul 11 08:53:42 PM PDT 24 |
360022701976 ps |
| T931 |
/workspace/coverage/default/28.sram_ctrl_lc_escalation.1877601570 |
|
|
Jul 11 06:04:22 PM PDT 24 |
Jul 11 06:05:19 PM PDT 24 |
27079601468 ps |
| T932 |
/workspace/coverage/default/25.sram_ctrl_mem_partial_access.2045013852 |
|
|
Jul 11 06:04:10 PM PDT 24 |
Jul 11 06:05:38 PM PDT 24 |
9834752357 ps |
| T933 |
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.1449349862 |
|
|
Jul 11 06:03:07 PM PDT 24 |
Jul 11 06:04:47 PM PDT 24 |
4815459806 ps |
| T934 |
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.955654521 |
|
|
Jul 11 06:06:13 PM PDT 24 |
Jul 11 06:06:35 PM PDT 24 |
811318129 ps |
| T935 |
/workspace/coverage/default/34.sram_ctrl_max_throughput.2500454709 |
|
|
Jul 11 06:04:53 PM PDT 24 |
Jul 11 06:05:24 PM PDT 24 |
1412910827 ps |
| T936 |
/workspace/coverage/default/2.sram_ctrl_mem_walk.4111134818 |
|
|
Jul 11 06:02:58 PM PDT 24 |
Jul 11 06:05:25 PM PDT 24 |
1983045113 ps |
| T937 |
/workspace/coverage/default/42.sram_ctrl_regwen.4139738193 |
|
|
Jul 11 06:05:49 PM PDT 24 |
Jul 11 06:33:50 PM PDT 24 |
20810259350 ps |
| T938 |
/workspace/coverage/default/24.sram_ctrl_executable.1514048099 |
|
|
Jul 11 06:04:04 PM PDT 24 |
Jul 11 06:24:34 PM PDT 24 |
36471336247 ps |
| T939 |
/workspace/coverage/default/12.sram_ctrl_bijection.3524917926 |
|
|
Jul 11 06:03:30 PM PDT 24 |
Jul 11 06:37:28 PM PDT 24 |
496931551260 ps |
| T940 |
/workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.315997061 |
|
|
Jul 11 06:03:00 PM PDT 24 |
Jul 11 06:05:23 PM PDT 24 |
2895110493 ps |
| T941 |
/workspace/coverage/default/25.sram_ctrl_partial_access.555967150 |
|
|
Jul 11 06:04:11 PM PDT 24 |
Jul 11 06:05:04 PM PDT 24 |
3235620992 ps |
| T942 |
/workspace/coverage/default/3.sram_ctrl_partial_access_b2b.31673621 |
|
|
Jul 11 06:03:17 PM PDT 24 |
Jul 11 06:10:01 PM PDT 24 |
30707901182 ps |
| T943 |
/workspace/coverage/default/34.sram_ctrl_mem_walk.3360114133 |
|
|
Jul 11 06:05:02 PM PDT 24 |
Jul 11 06:07:51 PM PDT 24 |
32097951192 ps |
| T944 |
/workspace/coverage/default/38.sram_ctrl_stress_all.3109268661 |
|
|
Jul 11 06:05:25 PM PDT 24 |
Jul 11 06:49:49 PM PDT 24 |
104428390508 ps |
| T945 |
/workspace/coverage/default/14.sram_ctrl_smoke.2788851044 |
|
|
Jul 11 06:03:37 PM PDT 24 |
Jul 11 06:03:53 PM PDT 24 |
689948797 ps |
| T65 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1161991249 |
|
|
Jul 11 05:48:17 PM PDT 24 |
Jul 11 05:48:23 PM PDT 24 |
19988672 ps |
| T946 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.4018527794 |
|
|
Jul 11 05:47:58 PM PDT 24 |
Jul 11 05:48:06 PM PDT 24 |
36660290 ps |
| T66 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.505972176 |
|
|
Jul 11 05:47:54 PM PDT 24 |
Jul 11 05:48:01 PM PDT 24 |
56237678 ps |
| T67 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.21090438 |
|
|
Jul 11 05:48:05 PM PDT 24 |
Jul 11 05:48:13 PM PDT 24 |
148027959 ps |
| T947 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1731009274 |
|
|
Jul 11 05:48:08 PM PDT 24 |
Jul 11 05:48:18 PM PDT 24 |
353149966 ps |
| T84 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1770450192 |
|
|
Jul 11 05:47:55 PM PDT 24 |
Jul 11 05:48:02 PM PDT 24 |
52441082 ps |
| T61 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.901120086 |
|
|
Jul 11 05:47:57 PM PDT 24 |
Jul 11 05:48:05 PM PDT 24 |
724293562 ps |
| T85 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1893618429 |
|
|
Jul 11 05:48:07 PM PDT 24 |
Jul 11 05:48:14 PM PDT 24 |
23080583 ps |
| T86 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1127211388 |
|
|
Jul 11 05:48:04 PM PDT 24 |
Jul 11 05:48:11 PM PDT 24 |
13089199 ps |
| T948 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1948669414 |
|
|
Jul 11 05:48:11 PM PDT 24 |
Jul 11 05:48:21 PM PDT 24 |
33360820 ps |
| T87 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3641962295 |
|
|
Jul 11 05:48:04 PM PDT 24 |
Jul 11 05:48:12 PM PDT 24 |
179380789 ps |
| T62 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.419424515 |
|
|
Jul 11 05:48:20 PM PDT 24 |
Jul 11 05:48:28 PM PDT 24 |
350376656 ps |
| T949 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3408519969 |
|
|
Jul 11 05:48:09 PM PDT 24 |
Jul 11 05:48:20 PM PDT 24 |
470403214 ps |
| T129 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.220108850 |
|
|
Jul 11 05:48:20 PM PDT 24 |
Jul 11 05:48:27 PM PDT 24 |
25869893 ps |
| T88 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3526978001 |
|
|
Jul 11 05:48:10 PM PDT 24 |
Jul 11 05:49:08 PM PDT 24 |
7501470390 ps |
| T110 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1281691088 |
|
|
Jul 11 05:48:03 PM PDT 24 |
Jul 11 05:48:10 PM PDT 24 |
158852001 ps |
| T950 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2622368642 |
|
|
Jul 11 05:48:57 PM PDT 24 |
Jul 11 05:49:08 PM PDT 24 |
512948482 ps |
| T111 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1789509639 |
|
|
Jul 11 05:48:09 PM PDT 24 |
Jul 11 05:48:16 PM PDT 24 |
24031635 ps |
| T112 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1408870482 |
|
|
Jul 11 05:48:20 PM PDT 24 |
Jul 11 05:48:27 PM PDT 24 |
28029228 ps |
| T951 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.510065031 |
|
|
Jul 11 05:48:12 PM PDT 24 |
Jul 11 05:48:21 PM PDT 24 |
410276565 ps |
| T952 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1563430596 |
|
|
Jul 11 05:47:55 PM PDT 24 |
Jul 11 05:48:03 PM PDT 24 |
127746749 ps |
| T63 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3842965494 |
|
|
Jul 11 05:48:10 PM PDT 24 |
Jul 11 05:48:18 PM PDT 24 |
174982685 ps |
| T148 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1996212924 |
|
|
Jul 11 05:48:03 PM PDT 24 |
Jul 11 05:48:11 PM PDT 24 |
469116648 ps |
| T146 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3000548960 |
|
|
Jul 11 05:48:19 PM PDT 24 |
Jul 11 05:48:27 PM PDT 24 |
621611405 ps |
| T89 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1050554265 |
|
|
Jul 11 05:57:16 PM PDT 24 |
Jul 11 05:57:18 PM PDT 24 |
29156932 ps |
| T953 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3001709254 |
|
|
Jul 11 05:48:05 PM PDT 24 |
Jul 11 05:48:16 PM PDT 24 |
1467858865 ps |
| T954 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1144324897 |
|
|
Jul 11 05:48:03 PM PDT 24 |
Jul 11 05:48:12 PM PDT 24 |
738720551 ps |
| T955 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3354611402 |
|
|
Jul 11 05:48:20 PM PDT 24 |
Jul 11 05:48:26 PM PDT 24 |
36171731 ps |
| T956 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.626632253 |
|
|
Jul 11 05:48:07 PM PDT 24 |
Jul 11 05:48:17 PM PDT 24 |
730366794 ps |
| T957 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1877886522 |
|
|
Jul 11 05:47:59 PM PDT 24 |
Jul 11 05:48:08 PM PDT 24 |
362982454 ps |
| T958 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2566498646 |
|
|
Jul 11 05:48:19 PM PDT 24 |
Jul 11 05:48:25 PM PDT 24 |
38834320 ps |
| T147 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.218127400 |
|
|
Jul 11 05:47:58 PM PDT 24 |
Jul 11 05:48:06 PM PDT 24 |
375600668 ps |
| T959 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2991465593 |
|
|
Jul 11 05:48:09 PM PDT 24 |
Jul 11 05:48:19 PM PDT 24 |
1357681577 ps |
| T960 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2634558144 |
|
|
Jul 11 05:48:21 PM PDT 24 |
Jul 11 05:48:31 PM PDT 24 |
145576046 ps |
| T90 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.438735976 |
|
|
Jul 11 05:47:54 PM PDT 24 |
Jul 11 05:48:00 PM PDT 24 |
133716174 ps |
| T961 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.742776719 |
|
|
Jul 11 05:48:03 PM PDT 24 |
Jul 11 05:48:09 PM PDT 24 |
43774882 ps |
| T962 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.299222318 |
|
|
Jul 11 05:47:57 PM PDT 24 |
Jul 11 05:48:05 PM PDT 24 |
83766013 ps |
| T113 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3552252514 |
|
|
Jul 11 05:48:09 PM PDT 24 |
Jul 11 05:48:16 PM PDT 24 |
31520303 ps |
| T91 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3663161153 |
|
|
Jul 11 05:48:12 PM PDT 24 |
Jul 11 05:48:18 PM PDT 24 |
42074319 ps |
| T963 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3894983314 |
|
|
Jul 11 05:47:57 PM PDT 24 |
Jul 11 05:48:04 PM PDT 24 |
16157921 ps |
| T114 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2947210310 |
|
|
Jul 11 05:47:58 PM PDT 24 |
Jul 11 05:48:04 PM PDT 24 |
26094266 ps |
| T964 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.77096880 |
|
|
Jul 11 05:48:01 PM PDT 24 |
Jul 11 05:48:09 PM PDT 24 |
29350258 ps |
| T965 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3718715836 |
|
|
Jul 11 05:48:57 PM PDT 24 |
Jul 11 05:49:06 PM PDT 24 |
29908039 ps |
| T966 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2241064950 |
|
|
Jul 11 05:47:59 PM PDT 24 |
Jul 11 05:48:08 PM PDT 24 |
4874914766 ps |
| T967 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.834020140 |
|
|
Jul 11 05:48:06 PM PDT 24 |
Jul 11 05:48:13 PM PDT 24 |
51262027 ps |
| T968 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.630893299 |
|
|
Jul 11 05:48:26 PM PDT 24 |
Jul 11 05:48:32 PM PDT 24 |
295804188 ps |
| T92 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1496750751 |
|
|
Jul 11 05:48:01 PM PDT 24 |
Jul 11 05:48:35 PM PDT 24 |
28346720770 ps |
| T969 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2114409845 |
|
|
Jul 11 05:48:08 PM PDT 24 |
Jul 11 05:48:19 PM PDT 24 |
178645926 ps |
| T93 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3247879654 |
|
|
Jul 11 05:48:07 PM PDT 24 |
Jul 11 05:49:06 PM PDT 24 |
29322644409 ps |
| T94 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3191266229 |
|
|
Jul 11 05:48:05 PM PDT 24 |
Jul 11 05:48:41 PM PDT 24 |
3855727890 ps |
| T970 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3295188262 |
|
|
Jul 11 05:48:06 PM PDT 24 |
Jul 11 05:48:13 PM PDT 24 |
26730583 ps |
| T95 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3185414369 |
|
|
Jul 11 05:48:25 PM PDT 24 |
Jul 11 05:49:18 PM PDT 24 |
7134685759 ps |
| T971 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2315072381 |
|
|
Jul 11 05:47:51 PM PDT 24 |
Jul 11 05:47:58 PM PDT 24 |
155629532 ps |
| T972 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1603808569 |
|
|
Jul 11 05:48:15 PM PDT 24 |
Jul 11 05:48:52 PM PDT 24 |
33528846401 ps |
| T973 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.665381713 |
|
|
Jul 11 05:48:17 PM PDT 24 |
Jul 11 05:48:27 PM PDT 24 |
1476791011 ps |
| T974 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.4123914428 |
|
|
Jul 11 05:48:09 PM PDT 24 |
Jul 11 05:48:16 PM PDT 24 |
43839396 ps |
| T96 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2456373336 |
|
|
Jul 11 05:48:15 PM PDT 24 |
Jul 11 05:49:12 PM PDT 24 |
29429546356 ps |
| T975 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3272780975 |
|
|
Jul 11 05:48:09 PM PDT 24 |
Jul 11 05:48:18 PM PDT 24 |
83219210 ps |
| T97 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2018226967 |
|
|
Jul 11 05:48:02 PM PDT 24 |
Jul 11 05:48:35 PM PDT 24 |
26345216478 ps |
| T976 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.327753287 |
|
|
Jul 11 05:48:04 PM PDT 24 |
Jul 11 05:48:13 PM PDT 24 |
1362479687 ps |
| T977 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3270117952 |
|
|
Jul 11 05:47:56 PM PDT 24 |
Jul 11 05:48:03 PM PDT 24 |
86722451 ps |
| T978 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2208029964 |
|
|
Jul 11 05:48:19 PM PDT 24 |
Jul 11 05:48:25 PM PDT 24 |
78309636 ps |
| T979 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3369767927 |
|
|
Jul 11 05:48:05 PM PDT 24 |
Jul 11 05:48:12 PM PDT 24 |
145765373 ps |
| T980 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3665653676 |
|
|
Jul 11 05:48:02 PM PDT 24 |
Jul 11 05:48:08 PM PDT 24 |
34213808 ps |
| T150 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2387413842 |
|
|
Jul 11 05:48:03 PM PDT 24 |
Jul 11 05:48:11 PM PDT 24 |
336713188 ps |
| T98 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1616436655 |
|
|
Jul 11 05:48:02 PM PDT 24 |
Jul 11 05:48:59 PM PDT 24 |
7041396563 ps |
| T981 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.719457020 |
|
|
Jul 11 05:48:03 PM PDT 24 |
Jul 11 05:48:10 PM PDT 24 |
31735325 ps |
| T151 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2440496530 |
|
|
Jul 11 05:48:17 PM PDT 24 |
Jul 11 05:48:25 PM PDT 24 |
358275754 ps |
| T982 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2918070991 |
|
|
Jul 11 05:48:02 PM PDT 24 |
Jul 11 05:48:08 PM PDT 24 |
14449294 ps |
| T104 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1666326168 |
|
|
Jul 11 05:48:13 PM PDT 24 |
Jul 11 05:48:20 PM PDT 24 |
49624026 ps |
| T983 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3426019841 |
|
|
Jul 11 05:48:00 PM PDT 24 |
Jul 11 05:48:55 PM PDT 24 |
7791268321 ps |
| T984 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2987736541 |
|
|
Jul 11 05:48:00 PM PDT 24 |
Jul 11 05:48:11 PM PDT 24 |
362086423 ps |
| T985 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2200575745 |
|
|
Jul 11 05:47:57 PM PDT 24 |
Jul 11 05:48:06 PM PDT 24 |
70232865 ps |
| T986 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.827719941 |
|
|
Jul 11 05:48:05 PM PDT 24 |
Jul 11 05:48:12 PM PDT 24 |
18369679 ps |
| T987 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3881567327 |
|
|
Jul 11 05:48:22 PM PDT 24 |
Jul 11 05:48:28 PM PDT 24 |
15922611 ps |
| T988 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.548839779 |
|
|
Jul 11 05:48:05 PM PDT 24 |
Jul 11 05:48:12 PM PDT 24 |
191592173 ps |
| T989 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2142997041 |
|
|
Jul 11 05:48:14 PM PDT 24 |
Jul 11 05:48:20 PM PDT 24 |
1026798514 ps |
| T990 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1919799706 |
|
|
Jul 11 05:48:13 PM PDT 24 |
Jul 11 05:48:45 PM PDT 24 |
3839919545 ps |
| T991 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3334376767 |
|
|
Jul 11 05:47:58 PM PDT 24 |
Jul 11 05:48:05 PM PDT 24 |
461120592 ps |
| T107 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.472253005 |
|
|
Jul 11 05:48:15 PM PDT 24 |
Jul 11 05:49:13 PM PDT 24 |
7092135394 ps |
| T992 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.744578537 |
|
|
Jul 11 05:48:07 PM PDT 24 |
Jul 11 05:48:14 PM PDT 24 |
33030522 ps |
| T993 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1093881762 |
|
|
Jul 11 05:48:27 PM PDT 24 |
Jul 11 05:48:33 PM PDT 24 |
154321167 ps |
| T994 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3882297047 |
|
|
Jul 11 05:48:18 PM PDT 24 |
Jul 11 05:48:27 PM PDT 24 |
26590017 ps |
| T995 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.4034121015 |
|
|
Jul 11 05:47:55 PM PDT 24 |
Jul 11 05:48:04 PM PDT 24 |
150944310 ps |
| T996 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.747479818 |
|
|
Jul 11 05:48:07 PM PDT 24 |
Jul 11 05:48:18 PM PDT 24 |
125323126 ps |
| T105 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1092102411 |
|
|
Jul 11 05:48:04 PM PDT 24 |
Jul 11 05:48:37 PM PDT 24 |
21733180649 ps |
| T997 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.4214837696 |
|
|
Jul 11 05:48:21 PM PDT 24 |
Jul 11 05:48:29 PM PDT 24 |
81272004 ps |
| T998 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3560962710 |
|
|
Jul 11 05:48:05 PM PDT 24 |
Jul 11 05:48:12 PM PDT 24 |
54250332 ps |
| T999 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2077565000 |
|
|
Jul 11 05:48:14 PM PDT 24 |
Jul 11 05:48:22 PM PDT 24 |
23397245 ps |
| T1000 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1625912964 |
|
|
Jul 11 05:48:17 PM PDT 24 |
Jul 11 05:48:24 PM PDT 24 |
47254329 ps |
| T1001 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.2256762405 |
|
|
Jul 11 05:48:20 PM PDT 24 |
Jul 11 05:48:26 PM PDT 24 |
53864884 ps |
| T1002 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3965447644 |
|
|
Jul 11 05:48:09 PM PDT 24 |
Jul 11 05:48:19 PM PDT 24 |
3126898871 ps |
| T1003 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3749625001 |
|
|
Jul 11 05:47:52 PM PDT 24 |
Jul 11 05:47:58 PM PDT 24 |
16934158 ps |
| T1004 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.4021468806 |
|
|
Jul 11 05:48:01 PM PDT 24 |
Jul 11 05:48:09 PM PDT 24 |
152586214 ps |
| T155 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1459750209 |
|
|
Jul 11 05:48:10 PM PDT 24 |
Jul 11 05:48:18 PM PDT 24 |
205342821 ps |
| T1005 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.276361065 |
|
|
Jul 11 05:48:06 PM PDT 24 |
Jul 11 05:48:13 PM PDT 24 |
85333025 ps |
| T1006 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3317232922 |
|
|
Jul 11 05:48:09 PM PDT 24 |
Jul 11 05:48:18 PM PDT 24 |
101068306 ps |
| T1007 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.246667812 |
|
|
Jul 11 05:47:53 PM PDT 24 |
Jul 11 05:48:03 PM PDT 24 |
1461817289 ps |
| T106 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.454641632 |
|
|
Jul 11 05:48:18 PM PDT 24 |
Jul 11 05:49:17 PM PDT 24 |
7510288186 ps |