SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
97.97 | 99.19 | 94.27 | 99.72 | 100.00 | 96.03 | 99.12 | 97.44 |
T1008 | /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2207564055 | Jul 11 05:48:17 PM PDT 24 | Jul 11 05:48:26 PM PDT 24 | 2832391389 ps | ||
T1009 | /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.335071937 | Jul 11 05:48:00 PM PDT 24 | Jul 11 05:48:06 PM PDT 24 | 14338929 ps | ||
T108 | /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3418690008 | Jul 11 05:47:56 PM PDT 24 | Jul 11 05:48:30 PM PDT 24 | 3868018971 ps | ||
T1010 | /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2594517729 | Jul 11 05:48:11 PM PDT 24 | Jul 11 05:48:21 PM PDT 24 | 684687794 ps | ||
T109 | /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2965549311 | Jul 11 05:48:15 PM PDT 24 | Jul 11 05:49:11 PM PDT 24 | 14123097925 ps | ||
T1011 | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1348422817 | Jul 11 05:48:02 PM PDT 24 | Jul 11 05:48:11 PM PDT 24 | 355688576 ps | ||
T1012 | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.799343980 | Jul 11 05:48:00 PM PDT 24 | Jul 11 05:48:07 PM PDT 24 | 18692383 ps | ||
T1013 | /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2957808223 | Jul 11 05:48:20 PM PDT 24 | Jul 11 05:48:27 PM PDT 24 | 18916024 ps | ||
T152 | /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2020210030 | Jul 11 05:48:06 PM PDT 24 | Jul 11 05:48:15 PM PDT 24 | 514209314 ps | ||
T1014 | /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3485050443 | Jul 11 05:48:06 PM PDT 24 | Jul 11 05:48:42 PM PDT 24 | 14805591442 ps | ||
T1015 | /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1315366656 | Jul 11 05:48:06 PM PDT 24 | Jul 11 05:48:15 PM PDT 24 | 241551056 ps | ||
T153 | /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2033995044 | Jul 11 05:50:33 PM PDT 24 | Jul 11 05:50:36 PM PDT 24 | 676187977 ps | ||
T1016 | /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.4228613125 | Jul 11 05:48:14 PM PDT 24 | Jul 11 05:48:19 PM PDT 24 | 37904744 ps | ||
T1017 | /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1635052926 | Jul 11 05:48:13 PM PDT 24 | Jul 11 05:48:19 PM PDT 24 | 89158243 ps | ||
T1018 | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1320754096 | Jul 11 05:48:04 PM PDT 24 | Jul 11 05:48:11 PM PDT 24 | 53089327 ps | ||
T1019 | /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1957359072 | Jul 11 05:48:10 PM PDT 24 | Jul 11 05:48:19 PM PDT 24 | 1202159917 ps | ||
T1020 | /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1388134499 | Jul 11 05:48:03 PM PDT 24 | Jul 11 05:48:37 PM PDT 24 | 3704970424 ps | ||
T154 | /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.365320710 | Jul 11 05:48:19 PM PDT 24 | Jul 11 05:48:28 PM PDT 24 | 790842296 ps | ||
T1021 | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.4185220407 | Jul 11 05:48:09 PM PDT 24 | Jul 11 05:48:16 PM PDT 24 | 16030985 ps | ||
T1022 | /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.522503567 | Jul 11 05:48:17 PM PDT 24 | Jul 11 05:48:27 PM PDT 24 | 1869869029 ps | ||
T1023 | /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1346930801 | Jul 11 05:48:08 PM PDT 24 | Jul 11 05:48:20 PM PDT 24 | 2502783893 ps | ||
T1024 | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.4017360732 | Jul 11 05:47:56 PM PDT 24 | Jul 11 05:48:03 PM PDT 24 | 15313505 ps | ||
T1025 | /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.768023373 | Jul 11 05:47:55 PM PDT 24 | Jul 11 05:48:48 PM PDT 24 | 7556556982 ps | ||
T1026 | /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3134940215 | Jul 11 05:48:06 PM PDT 24 | Jul 11 05:48:13 PM PDT 24 | 38420185 ps | ||
T149 | /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.380780753 | Jul 11 05:48:12 PM PDT 24 | Jul 11 05:48:20 PM PDT 24 | 493287314 ps | ||
T1027 | /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.331849955 | Jul 11 05:48:18 PM PDT 24 | Jul 11 05:48:51 PM PDT 24 | 33566600929 ps | ||
T1028 | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3682169163 | Jul 11 05:48:04 PM PDT 24 | Jul 11 05:48:12 PM PDT 24 | 46015071 ps | ||
T1029 | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2649051280 | Jul 11 05:48:08 PM PDT 24 | Jul 11 05:48:19 PM PDT 24 | 1810210261 ps | ||
T1030 | /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.895628229 | Jul 11 05:48:02 PM PDT 24 | Jul 11 05:48:09 PM PDT 24 | 18271249 ps | ||
T1031 | /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2805661334 | Jul 11 05:48:04 PM PDT 24 | Jul 11 05:48:11 PM PDT 24 | 52503231 ps | ||
T1032 | /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3492525646 | Jul 11 05:48:12 PM PDT 24 | Jul 11 05:48:19 PM PDT 24 | 122466257 ps | ||
T156 | /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3780453380 | Jul 11 05:48:06 PM PDT 24 | Jul 11 05:48:14 PM PDT 24 | 96851043 ps | ||
T1033 | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2448989197 | Jul 11 05:48:05 PM PDT 24 | Jul 11 05:48:12 PM PDT 24 | 46639037 ps | ||
T1034 | /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3705360278 | Jul 11 05:48:30 PM PDT 24 | Jul 11 05:48:34 PM PDT 24 | 239610676 ps | ||
T1035 | /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2185110294 | Jul 11 05:48:03 PM PDT 24 | Jul 11 05:48:10 PM PDT 24 | 18291659 ps | ||
T1036 | /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2005068188 | Jul 11 05:48:06 PM PDT 24 | Jul 11 05:48:17 PM PDT 24 | 1456659313 ps |
Test location | /workspace/coverage/default/38.sram_ctrl_executable.3240275115 |
Short name | T4 |
Test name | |
Test status | |
Simulation time | 88462679377 ps |
CPU time | 480.65 seconds |
Started | Jul 11 06:05:17 PM PDT 24 |
Finished | Jul 11 06:13:19 PM PDT 24 |
Peak memory | 369492 kb |
Host | smart-2ea14750-eb2b-4879-8fca-fd3b95c7e6d1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240275115 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_executab le.3240275115 |
Directory | /workspace/38.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_mem_partial_access.2209318201 |
Short name | T48 |
Test name | |
Test status | |
Simulation time | 32687645051 ps |
CPU time | 177.77 seconds |
Started | Jul 11 06:05:32 PM PDT 24 |
Finished | Jul 11 06:08:31 PM PDT 24 |
Peak memory | 219164 kb |
Host | smart-c32b1459-475b-4a8a-a55f-42f968ec3512 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209318201 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 8.sram_ctrl_mem_partial_access.2209318201 |
Directory | /workspace/38.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.3634723369 |
Short name | T25 |
Test name | |
Test status | |
Simulation time | 1779333550 ps |
CPU time | 47.58 seconds |
Started | Jul 11 06:03:40 PM PDT 24 |
Finished | Jul 11 06:04:38 PM PDT 24 |
Peak memory | 212664 kb |
Host | smart-52ebd67e-4719-4ed9-9227-6435d69abbb3 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3634723369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all_with_rand_reset.3634723369 |
Directory | /workspace/14.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_lc_escalation.1219784540 |
Short name | T6 |
Test name | |
Test status | |
Simulation time | 21694968264 ps |
CPU time | 69.88 seconds |
Started | Jul 11 06:03:42 PM PDT 24 |
Finished | Jul 11 06:05:02 PM PDT 24 |
Peak memory | 216084 kb |
Host | smart-5417c3f7-1e08-4387-b316-84bb650f8eac |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219784540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_es calation.1219784540 |
Directory | /workspace/14.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_stress_all.953943775 |
Short name | T8 |
Test name | |
Test status | |
Simulation time | 219553646485 ps |
CPU time | 6821.29 seconds |
Started | Jul 11 06:05:43 PM PDT 24 |
Finished | Jul 11 07:59:28 PM PDT 24 |
Peak memory | 382908 kb |
Host | smart-10415516-b408-442f-89e9-9003cf737fe7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953943775 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 40.sram_ctrl_stress_all.953943775 |
Directory | /workspace/40.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3842965494 |
Short name | T63 |
Test name | |
Test status | |
Simulation time | 174982685 ps |
CPU time | 2.16 seconds |
Started | Jul 11 05:48:10 PM PDT 24 |
Finished | Jul 11 05:48:18 PM PDT 24 |
Peak memory | 211004 kb |
Host | smart-3720db2f-e134-47d5-8bdb-5c15dab92a2d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842965494 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 13.sram_ctrl_tl_intg_err.3842965494 |
Directory | /workspace/13.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.1823381136 |
Short name | T115 |
Test name | |
Test status | |
Simulation time | 25018810339 ps |
CPU time | 288.76 seconds |
Started | Jul 11 06:05:20 PM PDT 24 |
Finished | Jul 11 06:10:11 PM PDT 24 |
Peak memory | 202840 kb |
Host | smart-8e5a2934-03cd-4c4a-a767-8eaa2f55a4f1 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823381136 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 38.sram_ctrl_partial_access_b2b.1823381136 |
Directory | /workspace/38.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_sec_cm.3754306324 |
Short name | T30 |
Test name | |
Test status | |
Simulation time | 984823140 ps |
CPU time | 2.08 seconds |
Started | Jul 11 06:02:53 PM PDT 24 |
Finished | Jul 11 06:03:15 PM PDT 24 |
Peak memory | 222188 kb |
Host | smart-770a8d34-013f-46d8-adc5-52c2259850bd |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754306324 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_sec_cm.3754306324 |
Directory | /workspace/0.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_stress_pipeline.514847122 |
Short name | T13 |
Test name | |
Test status | |
Simulation time | 3766479926 ps |
CPU time | 231.22 seconds |
Started | Jul 11 06:04:32 PM PDT 24 |
Finished | Jul 11 06:08:26 PM PDT 24 |
Peak memory | 202856 kb |
Host | smart-a7c18464-ecfe-4855-a438-c1ffb7303cb8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514847122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30 .sram_ctrl_stress_pipeline.514847122 |
Directory | /workspace/30.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_alert_test.3413195827 |
Short name | T194 |
Test name | |
Test status | |
Simulation time | 19972449 ps |
CPU time | 0.67 seconds |
Started | Jul 11 06:03:01 PM PDT 24 |
Finished | Jul 11 06:03:20 PM PDT 24 |
Peak memory | 202316 kb |
Host | smart-6f0269cd-9226-410f-9ab0-de75476a2c22 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413195827 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_alert_test.3413195827 |
Directory | /workspace/1.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3526978001 |
Short name | T88 |
Test name | |
Test status | |
Simulation time | 7501470390 ps |
CPU time | 51.39 seconds |
Started | Jul 11 05:48:10 PM PDT 24 |
Finished | Jul 11 05:49:08 PM PDT 24 |
Peak memory | 203312 kb |
Host | smart-b7cc987e-fc50-433c-9405-41abbbde1172 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526978001 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 18.sram_ctrl_passthru_mem_tl_intg_err.3526978001 |
Directory | /workspace/18.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_ram_cfg.240009893 |
Short name | T29 |
Test name | |
Test status | |
Simulation time | 693564726 ps |
CPU time | 3.27 seconds |
Started | Jul 11 06:03:40 PM PDT 24 |
Finished | Jul 11 06:03:53 PM PDT 24 |
Peak memory | 202916 kb |
Host | smart-589acde8-6473-4be4-b362-c7362595dffe |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240009893 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.240009893 |
Directory | /workspace/15.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.901120086 |
Short name | T61 |
Test name | |
Test status | |
Simulation time | 724293562 ps |
CPU time | 2.43 seconds |
Started | Jul 11 05:47:57 PM PDT 24 |
Finished | Jul 11 05:48:05 PM PDT 24 |
Peak memory | 211168 kb |
Host | smart-0aa6447c-fce2-48c7-b9d3-03cad4cc3430 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901120086 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 2.sram_ctrl_tl_intg_err.901120086 |
Directory | /workspace/2.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.959957180 |
Short name | T73 |
Test name | |
Test status | |
Simulation time | 342724550 ps |
CPU time | 5.7 seconds |
Started | Jul 11 06:03:44 PM PDT 24 |
Finished | Jul 11 06:04:00 PM PDT 24 |
Peak memory | 211120 kb |
Host | smart-11e2f112-0656-4a1d-9c14-aacdafeb489e |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=959957180 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all_with_rand_reset.959957180 |
Directory | /workspace/13.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.3037473324 |
Short name | T47 |
Test name | |
Test status | |
Simulation time | 10299667245 ps |
CPU time | 88.52 seconds |
Started | Jul 11 06:06:07 PM PDT 24 |
Finished | Jul 11 06:07:36 PM PDT 24 |
Peak memory | 315360 kb |
Host | smart-b94fc2f6-39cf-4f87-a99a-42c82251e7c9 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3037473324 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all_with_rand_reset.3037473324 |
Directory | /workspace/44.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_stress_all.2697767914 |
Short name | T222 |
Test name | |
Test status | |
Simulation time | 62232967132 ps |
CPU time | 4502.57 seconds |
Started | Jul 11 06:03:04 PM PDT 24 |
Finished | Jul 11 07:18:25 PM PDT 24 |
Peak memory | 380924 kb |
Host | smart-348460a6-8944-4dda-8b1b-e932c2adacee |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697767914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 2.sram_ctrl_stress_all.2697767914 |
Directory | /workspace/2.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.419424515 |
Short name | T62 |
Test name | |
Test status | |
Simulation time | 350376656 ps |
CPU time | 1.67 seconds |
Started | Jul 11 05:48:20 PM PDT 24 |
Finished | Jul 11 05:48:28 PM PDT 24 |
Peak memory | 211056 kb |
Host | smart-eba33cf6-6e1a-43cd-8cc4-1ec4e040485d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419424515 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 10.sram_ctrl_tl_intg_err.419424515 |
Directory | /workspace/10.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3780453380 |
Short name | T156 |
Test name | |
Test status | |
Simulation time | 96851043 ps |
CPU time | 1.42 seconds |
Started | Jul 11 05:48:06 PM PDT 24 |
Finished | Jul 11 05:48:14 PM PDT 24 |
Peak memory | 211124 kb |
Host | smart-2069eb39-c22d-4278-8269-36c6cd8fd1d3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780453380 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 15.sram_ctrl_tl_intg_err.3780453380 |
Directory | /workspace/15.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_stress_all.4112750570 |
Short name | T246 |
Test name | |
Test status | |
Simulation time | 331030916428 ps |
CPU time | 1419.77 seconds |
Started | Jul 11 06:03:43 PM PDT 24 |
Finished | Jul 11 06:27:33 PM PDT 24 |
Peak memory | 381804 kb |
Host | smart-6f29d5d9-edd8-4b75-9c97-a6aafe668fc5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112750570 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 17.sram_ctrl_stress_all.4112750570 |
Directory | /workspace/17.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3191266229 |
Short name | T94 |
Test name | |
Test status | |
Simulation time | 3855727890 ps |
CPU time | 28.56 seconds |
Started | Jul 11 05:48:05 PM PDT 24 |
Finished | Jul 11 05:48:41 PM PDT 24 |
Peak memory | 202940 kb |
Host | smart-26d6e811-e0eb-44a0-8e14-2cfbafb3eeb4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191266229 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 1.sram_ctrl_passthru_mem_tl_intg_err.3191266229 |
Directory | /workspace/1.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.505972176 |
Short name | T66 |
Test name | |
Test status | |
Simulation time | 56237678 ps |
CPU time | 0.67 seconds |
Started | Jul 11 05:47:54 PM PDT 24 |
Finished | Jul 11 05:48:01 PM PDT 24 |
Peak memory | 202744 kb |
Host | smart-5c1606da-5342-43d9-ab57-96030f4cfe9f |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505972176 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_aliasing.505972176 |
Directory | /workspace/0.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.299222318 |
Short name | T962 |
Test name | |
Test status | |
Simulation time | 83766013 ps |
CPU time | 1.84 seconds |
Started | Jul 11 05:47:57 PM PDT 24 |
Finished | Jul 11 05:48:05 PM PDT 24 |
Peak memory | 202920 kb |
Host | smart-0584bb90-5cf5-4ef5-983a-06b0f4f8050b |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299222318 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_bit_bash.299222318 |
Directory | /workspace/0.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.438735976 |
Short name | T90 |
Test name | |
Test status | |
Simulation time | 133716174 ps |
CPU time | 0.69 seconds |
Started | Jul 11 05:47:54 PM PDT 24 |
Finished | Jul 11 05:48:00 PM PDT 24 |
Peak memory | 202760 kb |
Host | smart-56e0a507-defd-47ca-b93a-0eb3e90e79fe |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438735976 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_hw_reset.438735976 |
Directory | /workspace/0.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3001709254 |
Short name | T953 |
Test name | |
Test status | |
Simulation time | 1467858865 ps |
CPU time | 4.37 seconds |
Started | Jul 11 05:48:05 PM PDT 24 |
Finished | Jul 11 05:48:16 PM PDT 24 |
Peak memory | 211148 kb |
Host | smart-84e060cb-aa55-410b-ad85-2c931c9b8ec9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001709254 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_mem_rw_with_rand_reset.3001709254 |
Directory | /workspace/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1770450192 |
Short name | T84 |
Test name | |
Test status | |
Simulation time | 52441082 ps |
CPU time | 0.66 seconds |
Started | Jul 11 05:47:55 PM PDT 24 |
Finished | Jul 11 05:48:02 PM PDT 24 |
Peak memory | 202748 kb |
Host | smart-d69d8961-dd8c-4ae3-bfd3-975ff0a6abc9 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770450192 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 0.sram_ctrl_csr_rw.1770450192 |
Directory | /workspace/0.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.768023373 |
Short name | T1025 |
Test name | |
Test status | |
Simulation time | 7556556982 ps |
CPU time | 47.05 seconds |
Started | Jul 11 05:47:55 PM PDT 24 |
Finished | Jul 11 05:48:48 PM PDT 24 |
Peak memory | 203036 kb |
Host | smart-70517ebf-ff13-4018-b8fe-880ea77039e9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768023373 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 0.sram_ctrl_passthru_mem_tl_intg_err.768023373 |
Directory | /workspace/0.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3270117952 |
Short name | T977 |
Test name | |
Test status | |
Simulation time | 86722451 ps |
CPU time | 0.79 seconds |
Started | Jul 11 05:47:56 PM PDT 24 |
Finished | Jul 11 05:48:03 PM PDT 24 |
Peak memory | 202704 kb |
Host | smart-154acde2-811d-43d5-b909-93033ebeafec |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270117952 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 0.sram_ctrl_same_csr_outstanding.3270117952 |
Directory | /workspace/0.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1563430596 |
Short name | T952 |
Test name | |
Test status | |
Simulation time | 127746749 ps |
CPU time | 2.23 seconds |
Started | Jul 11 05:47:55 PM PDT 24 |
Finished | Jul 11 05:48:03 PM PDT 24 |
Peak memory | 211116 kb |
Host | smart-7187f474-a78c-4d4f-b934-9d5ad3008ddf |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563430596 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 0.sram_ctrl_tl_errors.1563430596 |
Directory | /workspace/0.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.218127400 |
Short name | T147 |
Test name | |
Test status | |
Simulation time | 375600668 ps |
CPU time | 2.55 seconds |
Started | Jul 11 05:47:58 PM PDT 24 |
Finished | Jul 11 05:48:06 PM PDT 24 |
Peak memory | 211052 kb |
Host | smart-915fa83a-d0ad-4300-89db-06fc2b9c0b9e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218127400 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 0.sram_ctrl_tl_intg_err.218127400 |
Directory | /workspace/0.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3560962710 |
Short name | T998 |
Test name | |
Test status | |
Simulation time | 54250332 ps |
CPU time | 0.73 seconds |
Started | Jul 11 05:48:05 PM PDT 24 |
Finished | Jul 11 05:48:12 PM PDT 24 |
Peak memory | 202688 kb |
Host | smart-7f902829-28e4-4b21-a7ca-0b859f21ce5a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560962710 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.sram_ctrl_csr_aliasing.3560962710 |
Directory | /workspace/1.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2315072381 |
Short name | T971 |
Test name | |
Test status | |
Simulation time | 155629532 ps |
CPU time | 1.84 seconds |
Started | Jul 11 05:47:51 PM PDT 24 |
Finished | Jul 11 05:47:58 PM PDT 24 |
Peak memory | 202796 kb |
Host | smart-85b9806a-cf21-4581-bed9-4272ecca0bc2 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315072381 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.sram_ctrl_csr_bit_bash.2315072381 |
Directory | /workspace/1.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3749625001 |
Short name | T1003 |
Test name | |
Test status | |
Simulation time | 16934158 ps |
CPU time | 0.64 seconds |
Started | Jul 11 05:47:52 PM PDT 24 |
Finished | Jul 11 05:47:58 PM PDT 24 |
Peak memory | 202528 kb |
Host | smart-3dbfd216-2b13-4857-be43-5a791567979b |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749625001 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.sram_ctrl_csr_hw_reset.3749625001 |
Directory | /workspace/1.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.246667812 |
Short name | T1007 |
Test name | |
Test status | |
Simulation time | 1461817289 ps |
CPU time | 4.04 seconds |
Started | Jul 11 05:47:53 PM PDT 24 |
Finished | Jul 11 05:48:03 PM PDT 24 |
Peak memory | 211024 kb |
Host | smart-e0ee773b-7e69-425a-87ba-dee4a87d3807 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246667812 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_rw_with_rand_reset.246667812 |
Directory | /workspace/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3894983314 |
Short name | T963 |
Test name | |
Test status | |
Simulation time | 16157921 ps |
CPU time | 0.66 seconds |
Started | Jul 11 05:47:57 PM PDT 24 |
Finished | Jul 11 05:48:04 PM PDT 24 |
Peak memory | 202648 kb |
Host | smart-37175ed6-14af-4101-820c-f346bbb19579 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894983314 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 1.sram_ctrl_csr_rw.3894983314 |
Directory | /workspace/1.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.548839779 |
Short name | T988 |
Test name | |
Test status | |
Simulation time | 191592173 ps |
CPU time | 0.81 seconds |
Started | Jul 11 05:48:05 PM PDT 24 |
Finished | Jul 11 05:48:12 PM PDT 24 |
Peak memory | 202696 kb |
Host | smart-4fc8a7e0-9170-4957-bdfa-9204fcc0f28e |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548839779 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 1.sram_ctrl_same_csr_outstanding.548839779 |
Directory | /workspace/1.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.4034121015 |
Short name | T995 |
Test name | |
Test status | |
Simulation time | 150944310 ps |
CPU time | 3.24 seconds |
Started | Jul 11 05:47:55 PM PDT 24 |
Finished | Jul 11 05:48:04 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-f6e949f2-8469-4b6a-bd80-f1200f10e010 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034121015 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 1.sram_ctrl_tl_errors.4034121015 |
Directory | /workspace/1.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1996212924 |
Short name | T148 |
Test name | |
Test status | |
Simulation time | 469116648 ps |
CPU time | 2.34 seconds |
Started | Jul 11 05:48:03 PM PDT 24 |
Finished | Jul 11 05:48:11 PM PDT 24 |
Peak memory | 202876 kb |
Host | smart-a2afc88d-dbf5-47aa-acf5-c411527285e1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996212924 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 1.sram_ctrl_tl_intg_err.1996212924 |
Directory | /workspace/1.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1346930801 |
Short name | T1023 |
Test name | |
Test status | |
Simulation time | 2502783893 ps |
CPU time | 4.95 seconds |
Started | Jul 11 05:48:08 PM PDT 24 |
Finished | Jul 11 05:48:20 PM PDT 24 |
Peak memory | 211132 kb |
Host | smart-5a7163a2-5194-428f-a09d-b334c7a6f051 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346930801 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_rw_with_rand_reset.1346930801 |
Directory | /workspace/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1893618429 |
Short name | T85 |
Test name | |
Test status | |
Simulation time | 23080583 ps |
CPU time | 0.66 seconds |
Started | Jul 11 05:48:07 PM PDT 24 |
Finished | Jul 11 05:48:14 PM PDT 24 |
Peak memory | 202568 kb |
Host | smart-a765a7f3-6edc-4615-b5b7-74db5c0d89d3 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893618429 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 10.sram_ctrl_csr_rw.1893618429 |
Directory | /workspace/10.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.454641632 |
Short name | T106 |
Test name | |
Test status | |
Simulation time | 7510288186 ps |
CPU time | 52.48 seconds |
Started | Jul 11 05:48:18 PM PDT 24 |
Finished | Jul 11 05:49:17 PM PDT 24 |
Peak memory | 203088 kb |
Host | smart-3f6d1c39-30c7-4b56-8325-f3161c3fa88d |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454641632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 10.sram_ctrl_passthru_mem_tl_intg_err.454641632 |
Directory | /workspace/10.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.834020140 |
Short name | T967 |
Test name | |
Test status | |
Simulation time | 51262027 ps |
CPU time | 0.73 seconds |
Started | Jul 11 05:48:06 PM PDT 24 |
Finished | Jul 11 05:48:13 PM PDT 24 |
Peak memory | 202716 kb |
Host | smart-5cd74aeb-70bc-43a5-a08d-219fd60c1b5a |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834020140 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 10.sram_ctrl_same_csr_outstanding.834020140 |
Directory | /workspace/10.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2634558144 |
Short name | T960 |
Test name | |
Test status | |
Simulation time | 145576046 ps |
CPU time | 4.57 seconds |
Started | Jul 11 05:48:21 PM PDT 24 |
Finished | Jul 11 05:48:31 PM PDT 24 |
Peak memory | 211076 kb |
Host | smart-3484f3d2-15b4-4bd8-9f34-e0aee28d2ae6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634558144 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 10.sram_ctrl_tl_errors.2634558144 |
Directory | /workspace/10.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1144324897 |
Short name | T954 |
Test name | |
Test status | |
Simulation time | 738720551 ps |
CPU time | 3.65 seconds |
Started | Jul 11 05:48:03 PM PDT 24 |
Finished | Jul 11 05:48:12 PM PDT 24 |
Peak memory | 210924 kb |
Host | smart-70fad294-8bc5-418e-85c1-303bee91e7bd |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144324897 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_mem_rw_with_rand_reset.1144324897 |
Directory | /workspace/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1408870482 |
Short name | T112 |
Test name | |
Test status | |
Simulation time | 28029228 ps |
CPU time | 0.65 seconds |
Started | Jul 11 05:48:20 PM PDT 24 |
Finished | Jul 11 05:48:27 PM PDT 24 |
Peak memory | 202600 kb |
Host | smart-831ec20a-b2a0-4b65-a916-894b17278cf0 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408870482 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 11.sram_ctrl_csr_rw.1408870482 |
Directory | /workspace/11.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1919799706 |
Short name | T990 |
Test name | |
Test status | |
Simulation time | 3839919545 ps |
CPU time | 26.79 seconds |
Started | Jul 11 05:48:13 PM PDT 24 |
Finished | Jul 11 05:48:45 PM PDT 24 |
Peak memory | 202940 kb |
Host | smart-494cbcc1-fb70-4740-801a-a27aba32f324 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919799706 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 11.sram_ctrl_passthru_mem_tl_intg_err.1919799706 |
Directory | /workspace/11.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1281691088 |
Short name | T110 |
Test name | |
Test status | |
Simulation time | 158852001 ps |
CPU time | 0.8 seconds |
Started | Jul 11 05:48:03 PM PDT 24 |
Finished | Jul 11 05:48:10 PM PDT 24 |
Peak memory | 202904 kb |
Host | smart-34d2899b-7f33-4b04-b017-9a9935485961 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281691088 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 11.sram_ctrl_same_csr_outstanding.1281691088 |
Directory | /workspace/11.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1948669414 |
Short name | T948 |
Test name | |
Test status | |
Simulation time | 33360820 ps |
CPU time | 3.38 seconds |
Started | Jul 11 05:48:11 PM PDT 24 |
Finished | Jul 11 05:48:21 PM PDT 24 |
Peak memory | 202900 kb |
Host | smart-4da37f93-864e-4f68-b1ba-60ab61417799 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948669414 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 11.sram_ctrl_tl_errors.1948669414 |
Directory | /workspace/11.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.380780753 |
Short name | T149 |
Test name | |
Test status | |
Simulation time | 493287314 ps |
CPU time | 2.16 seconds |
Started | Jul 11 05:48:12 PM PDT 24 |
Finished | Jul 11 05:48:20 PM PDT 24 |
Peak memory | 213676 kb |
Host | smart-ba0bc8e7-831b-4316-9c6a-259fcf931310 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380780753 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 11.sram_ctrl_tl_intg_err.380780753 |
Directory | /workspace/11.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2005068188 |
Short name | T1036 |
Test name | |
Test status | |
Simulation time | 1456659313 ps |
CPU time | 3.99 seconds |
Started | Jul 11 05:48:06 PM PDT 24 |
Finished | Jul 11 05:48:17 PM PDT 24 |
Peak memory | 210908 kb |
Host | smart-e9fc431e-be86-4d2a-b796-da4832b995e7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005068188 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_mem_rw_with_rand_reset.2005068188 |
Directory | /workspace/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.4123914428 |
Short name | T974 |
Test name | |
Test status | |
Simulation time | 43839396 ps |
CPU time | 0.66 seconds |
Started | Jul 11 05:48:09 PM PDT 24 |
Finished | Jul 11 05:48:16 PM PDT 24 |
Peak memory | 202584 kb |
Host | smart-73f3c45a-29d0-49dd-adc0-546d9c0a09a1 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123914428 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 12.sram_ctrl_csr_rw.4123914428 |
Directory | /workspace/12.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2456373336 |
Short name | T96 |
Test name | |
Test status | |
Simulation time | 29429546356 ps |
CPU time | 51.87 seconds |
Started | Jul 11 05:48:15 PM PDT 24 |
Finished | Jul 11 05:49:12 PM PDT 24 |
Peak memory | 203012 kb |
Host | smart-6b210540-bb5c-44d9-9317-66112f5076b5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456373336 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 12.sram_ctrl_passthru_mem_tl_intg_err.2456373336 |
Directory | /workspace/12.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3134940215 |
Short name | T1026 |
Test name | |
Test status | |
Simulation time | 38420185 ps |
CPU time | 0.7 seconds |
Started | Jul 11 05:48:06 PM PDT 24 |
Finished | Jul 11 05:48:13 PM PDT 24 |
Peak memory | 202728 kb |
Host | smart-7d39cf93-6499-49d5-bf63-fbfa0f49580d |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134940215 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 12.sram_ctrl_same_csr_outstanding.3134940215 |
Directory | /workspace/12.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.747479818 |
Short name | T996 |
Test name | |
Test status | |
Simulation time | 125323126 ps |
CPU time | 4.31 seconds |
Started | Jul 11 05:48:07 PM PDT 24 |
Finished | Jul 11 05:48:18 PM PDT 24 |
Peak memory | 211132 kb |
Host | smart-8f76b41b-40ce-4f0a-bd2d-e886941c3183 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747479818 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_tl_errors.747479818 |
Directory | /workspace/12.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3492525646 |
Short name | T1032 |
Test name | |
Test status | |
Simulation time | 122466257 ps |
CPU time | 1.66 seconds |
Started | Jul 11 05:48:12 PM PDT 24 |
Finished | Jul 11 05:48:19 PM PDT 24 |
Peak memory | 211188 kb |
Host | smart-979d77c6-63c6-4ab9-a8a2-7646050d158f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492525646 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 12.sram_ctrl_tl_intg_err.3492525646 |
Directory | /workspace/12.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.327753287 |
Short name | T976 |
Test name | |
Test status | |
Simulation time | 1362479687 ps |
CPU time | 3.25 seconds |
Started | Jul 11 05:48:04 PM PDT 24 |
Finished | Jul 11 05:48:13 PM PDT 24 |
Peak memory | 202816 kb |
Host | smart-628e3ed4-d6f4-4d83-9805-efc1c95b7f34 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327753287 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_mem_rw_with_rand_reset.327753287 |
Directory | /workspace/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1666326168 |
Short name | T104 |
Test name | |
Test status | |
Simulation time | 49624026 ps |
CPU time | 0.69 seconds |
Started | Jul 11 05:48:13 PM PDT 24 |
Finished | Jul 11 05:48:20 PM PDT 24 |
Peak memory | 202720 kb |
Host | smart-a24438cd-a4e6-4cbd-ab8d-e2682a517baa |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666326168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 13.sram_ctrl_csr_rw.1666326168 |
Directory | /workspace/13.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3247879654 |
Short name | T93 |
Test name | |
Test status | |
Simulation time | 29322644409 ps |
CPU time | 52.24 seconds |
Started | Jul 11 05:48:07 PM PDT 24 |
Finished | Jul 11 05:49:06 PM PDT 24 |
Peak memory | 203128 kb |
Host | smart-5195e9dd-ce3e-4706-bc9a-502310af5379 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247879654 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 13.sram_ctrl_passthru_mem_tl_intg_err.3247879654 |
Directory | /workspace/13.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2957808223 |
Short name | T1013 |
Test name | |
Test status | |
Simulation time | 18916024 ps |
CPU time | 0.68 seconds |
Started | Jul 11 05:48:20 PM PDT 24 |
Finished | Jul 11 05:48:27 PM PDT 24 |
Peak memory | 202560 kb |
Host | smart-7e865a28-bcc4-4f85-a357-4d197bf8c085 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957808223 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 13.sram_ctrl_same_csr_outstanding.2957808223 |
Directory | /workspace/13.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3317232922 |
Short name | T1006 |
Test name | |
Test status | |
Simulation time | 101068306 ps |
CPU time | 2.2 seconds |
Started | Jul 11 05:48:09 PM PDT 24 |
Finished | Jul 11 05:48:18 PM PDT 24 |
Peak memory | 212348 kb |
Host | smart-24a643ca-fd63-48a8-80a4-5ebe17a3e136 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317232922 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 13.sram_ctrl_tl_errors.3317232922 |
Directory | /workspace/13.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.626632253 |
Short name | T956 |
Test name | |
Test status | |
Simulation time | 730366794 ps |
CPU time | 3.44 seconds |
Started | Jul 11 05:48:07 PM PDT 24 |
Finished | Jul 11 05:48:17 PM PDT 24 |
Peak memory | 210988 kb |
Host | smart-c4fb43c1-f264-418f-972b-e9b929a2cac0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626632253 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.626632253 |
Directory | /workspace/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.220108850 |
Short name | T129 |
Test name | |
Test status | |
Simulation time | 25869893 ps |
CPU time | 0.69 seconds |
Started | Jul 11 05:48:20 PM PDT 24 |
Finished | Jul 11 05:48:27 PM PDT 24 |
Peak memory | 202640 kb |
Host | smart-824f2c9c-d256-4aba-8b18-eb634e659373 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220108850 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 14.sram_ctrl_csr_rw.220108850 |
Directory | /workspace/14.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.331849955 |
Short name | T1027 |
Test name | |
Test status | |
Simulation time | 33566600929 ps |
CPU time | 26.46 seconds |
Started | Jul 11 05:48:18 PM PDT 24 |
Finished | Jul 11 05:48:51 PM PDT 24 |
Peak memory | 202588 kb |
Host | smart-fe98ca03-d270-4c08-acc8-7838b441e41f |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331849955 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 14.sram_ctrl_passthru_mem_tl_intg_err.331849955 |
Directory | /workspace/14.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.744578537 |
Short name | T992 |
Test name | |
Test status | |
Simulation time | 33030522 ps |
CPU time | 0.67 seconds |
Started | Jul 11 05:48:07 PM PDT 24 |
Finished | Jul 11 05:48:14 PM PDT 24 |
Peak memory | 202652 kb |
Host | smart-5231c8a3-cade-485e-8716-d6459cbf54a5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744578537 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 14.sram_ctrl_same_csr_outstanding.744578537 |
Directory | /workspace/14.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.4214837696 |
Short name | T997 |
Test name | |
Test status | |
Simulation time | 81272004 ps |
CPU time | 2.8 seconds |
Started | Jul 11 05:48:21 PM PDT 24 |
Finished | Jul 11 05:48:29 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-e7e790c6-627d-4fd5-807d-941bc904fdc7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214837696 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 14.sram_ctrl_tl_errors.4214837696 |
Directory | /workspace/14.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2142997041 |
Short name | T989 |
Test name | |
Test status | |
Simulation time | 1026798514 ps |
CPU time | 1.56 seconds |
Started | Jul 11 05:48:14 PM PDT 24 |
Finished | Jul 11 05:48:20 PM PDT 24 |
Peak memory | 211108 kb |
Host | smart-6cf1e1e9-c532-4b00-a4ca-b6628e096fb0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142997041 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 14.sram_ctrl_tl_intg_err.2142997041 |
Directory | /workspace/14.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1731009274 |
Short name | T947 |
Test name | |
Test status | |
Simulation time | 353149966 ps |
CPU time | 3.16 seconds |
Started | Jul 11 05:48:08 PM PDT 24 |
Finished | Jul 11 05:48:18 PM PDT 24 |
Peak memory | 210860 kb |
Host | smart-981d4bcc-50e8-4ea8-9b63-6e70751c34e6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731009274 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_mem_rw_with_rand_reset.1731009274 |
Directory | /workspace/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3354611402 |
Short name | T955 |
Test name | |
Test status | |
Simulation time | 36171731 ps |
CPU time | 0.63 seconds |
Started | Jul 11 05:48:20 PM PDT 24 |
Finished | Jul 11 05:48:26 PM PDT 24 |
Peak memory | 202632 kb |
Host | smart-cba31b4d-0bf0-44f3-ba07-4996056076d5 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354611402 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 15.sram_ctrl_csr_rw.3354611402 |
Directory | /workspace/15.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1092102411 |
Short name | T105 |
Test name | |
Test status | |
Simulation time | 21733180649 ps |
CPU time | 26.66 seconds |
Started | Jul 11 05:48:04 PM PDT 24 |
Finished | Jul 11 05:48:37 PM PDT 24 |
Peak memory | 202848 kb |
Host | smart-24b8a68f-4365-4da4-92fd-e5c7167387c1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092102411 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 15.sram_ctrl_passthru_mem_tl_intg_err.1092102411 |
Directory | /workspace/15.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.276361065 |
Short name | T1005 |
Test name | |
Test status | |
Simulation time | 85333025 ps |
CPU time | 0.72 seconds |
Started | Jul 11 05:48:06 PM PDT 24 |
Finished | Jul 11 05:48:13 PM PDT 24 |
Peak memory | 202728 kb |
Host | smart-943b2312-1f2d-4f7c-bcb8-e8b2468fc712 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276361065 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 15.sram_ctrl_same_csr_outstanding.276361065 |
Directory | /workspace/15.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2114409845 |
Short name | T969 |
Test name | |
Test status | |
Simulation time | 178645926 ps |
CPU time | 4.52 seconds |
Started | Jul 11 05:48:08 PM PDT 24 |
Finished | Jul 11 05:48:19 PM PDT 24 |
Peak memory | 211024 kb |
Host | smart-2f046262-3cf6-4b32-8fcf-9fb9c1e51b6f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114409845 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 15.sram_ctrl_tl_errors.2114409845 |
Directory | /workspace/15.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2622368642 |
Short name | T950 |
Test name | |
Test status | |
Simulation time | 512948482 ps |
CPU time | 3.52 seconds |
Started | Jul 11 05:48:57 PM PDT 24 |
Finished | Jul 11 05:49:08 PM PDT 24 |
Peak memory | 210760 kb |
Host | smart-2e1c7958-ab22-45d3-b94c-64211c914327 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622368642 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_mem_rw_with_rand_reset.2622368642 |
Directory | /workspace/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3881567327 |
Short name | T987 |
Test name | |
Test status | |
Simulation time | 15922611 ps |
CPU time | 0.67 seconds |
Started | Jul 11 05:48:22 PM PDT 24 |
Finished | Jul 11 05:48:28 PM PDT 24 |
Peak memory | 202680 kb |
Host | smart-8b674517-057a-45ef-9c9f-ba6a95590b88 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881567327 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 16.sram_ctrl_csr_rw.3881567327 |
Directory | /workspace/16.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3185414369 |
Short name | T95 |
Test name | |
Test status | |
Simulation time | 7134685759 ps |
CPU time | 48.83 seconds |
Started | Jul 11 05:48:25 PM PDT 24 |
Finished | Jul 11 05:49:18 PM PDT 24 |
Peak memory | 203116 kb |
Host | smart-dcfbd43a-8485-453e-8437-7086829c107f |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185414369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 16.sram_ctrl_passthru_mem_tl_intg_err.3185414369 |
Directory | /workspace/16.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3663161153 |
Short name | T91 |
Test name | |
Test status | |
Simulation time | 42074319 ps |
CPU time | 0.76 seconds |
Started | Jul 11 05:48:12 PM PDT 24 |
Finished | Jul 11 05:48:18 PM PDT 24 |
Peak memory | 202764 kb |
Host | smart-c1187526-659f-42f5-ad91-7ef218a1b68c |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663161153 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 16.sram_ctrl_same_csr_outstanding.3663161153 |
Directory | /workspace/16.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2077565000 |
Short name | T999 |
Test name | |
Test status | |
Simulation time | 23397245 ps |
CPU time | 2.21 seconds |
Started | Jul 11 05:48:14 PM PDT 24 |
Finished | Jul 11 05:48:22 PM PDT 24 |
Peak memory | 202932 kb |
Host | smart-e364eeb6-1bf1-4bbb-93e1-902869b17087 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077565000 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 16.sram_ctrl_tl_errors.2077565000 |
Directory | /workspace/16.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2440496530 |
Short name | T151 |
Test name | |
Test status | |
Simulation time | 358275754 ps |
CPU time | 1.66 seconds |
Started | Jul 11 05:48:17 PM PDT 24 |
Finished | Jul 11 05:48:25 PM PDT 24 |
Peak memory | 211032 kb |
Host | smart-8228b391-f0b2-43fc-870c-b0a7ae585082 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440496530 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 16.sram_ctrl_tl_intg_err.2440496530 |
Directory | /workspace/16.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.522503567 |
Short name | T1022 |
Test name | |
Test status | |
Simulation time | 1869869029 ps |
CPU time | 4.56 seconds |
Started | Jul 11 05:48:17 PM PDT 24 |
Finished | Jul 11 05:48:27 PM PDT 24 |
Peak memory | 211148 kb |
Host | smart-85725198-1cc0-4885-a705-aecf3387902d |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522503567 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_mem_rw_with_rand_reset.522503567 |
Directory | /workspace/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.4228613125 |
Short name | T1016 |
Test name | |
Test status | |
Simulation time | 37904744 ps |
CPU time | 0.66 seconds |
Started | Jul 11 05:48:14 PM PDT 24 |
Finished | Jul 11 05:48:19 PM PDT 24 |
Peak memory | 202536 kb |
Host | smart-40d8f847-cf0c-4dce-9365-d2c6829684f8 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228613125 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 17.sram_ctrl_csr_rw.4228613125 |
Directory | /workspace/17.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2965549311 |
Short name | T109 |
Test name | |
Test status | |
Simulation time | 14123097925 ps |
CPU time | 50.69 seconds |
Started | Jul 11 05:48:15 PM PDT 24 |
Finished | Jul 11 05:49:11 PM PDT 24 |
Peak memory | 203156 kb |
Host | smart-cd8d0c69-9f02-4a37-a332-c07d5b37dcb2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965549311 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 17.sram_ctrl_passthru_mem_tl_intg_err.2965549311 |
Directory | /workspace/17.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1625912964 |
Short name | T1000 |
Test name | |
Test status | |
Simulation time | 47254329 ps |
CPU time | 0.75 seconds |
Started | Jul 11 05:48:17 PM PDT 24 |
Finished | Jul 11 05:48:24 PM PDT 24 |
Peak memory | 202632 kb |
Host | smart-3aed0bef-8ac7-4182-938a-de5ac253c9a0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625912964 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 17.sram_ctrl_same_csr_outstanding.1625912964 |
Directory | /workspace/17.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1093881762 |
Short name | T993 |
Test name | |
Test status | |
Simulation time | 154321167 ps |
CPU time | 2.67 seconds |
Started | Jul 11 05:48:27 PM PDT 24 |
Finished | Jul 11 05:48:33 PM PDT 24 |
Peak memory | 211128 kb |
Host | smart-c7eefe38-de58-44ad-9ba9-de30d90793aa |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093881762 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 17.sram_ctrl_tl_errors.1093881762 |
Directory | /workspace/17.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2033995044 |
Short name | T153 |
Test name | |
Test status | |
Simulation time | 676187977 ps |
CPU time | 2.29 seconds |
Started | Jul 11 05:50:33 PM PDT 24 |
Finished | Jul 11 05:50:36 PM PDT 24 |
Peak memory | 202896 kb |
Host | smart-7e442679-8404-4278-a92c-0e545d5beba0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033995044 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 17.sram_ctrl_tl_intg_err.2033995044 |
Directory | /workspace/17.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.510065031 |
Short name | T951 |
Test name | |
Test status | |
Simulation time | 410276565 ps |
CPU time | 3.58 seconds |
Started | Jul 11 05:48:12 PM PDT 24 |
Finished | Jul 11 05:48:21 PM PDT 24 |
Peak memory | 210932 kb |
Host | smart-6c757750-7c9e-4306-9d65-9f30d670d66f |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510065031 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_rw_with_rand_reset.510065031 |
Directory | /workspace/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1161991249 |
Short name | T65 |
Test name | |
Test status | |
Simulation time | 19988672 ps |
CPU time | 0.66 seconds |
Started | Jul 11 05:48:17 PM PDT 24 |
Finished | Jul 11 05:48:23 PM PDT 24 |
Peak memory | 202752 kb |
Host | smart-15c030e9-bd37-414a-9c99-63aa3166f873 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161991249 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 18.sram_ctrl_csr_rw.1161991249 |
Directory | /workspace/18.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3718715836 |
Short name | T965 |
Test name | |
Test status | |
Simulation time | 29908039 ps |
CPU time | 0.79 seconds |
Started | Jul 11 05:48:57 PM PDT 24 |
Finished | Jul 11 05:49:06 PM PDT 24 |
Peak memory | 202548 kb |
Host | smart-6718aef9-818e-44fa-bc73-63860ee8c2d1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718715836 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 18.sram_ctrl_same_csr_outstanding.3718715836 |
Directory | /workspace/18.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3882297047 |
Short name | T994 |
Test name | |
Test status | |
Simulation time | 26590017 ps |
CPU time | 2.41 seconds |
Started | Jul 11 05:48:18 PM PDT 24 |
Finished | Jul 11 05:48:27 PM PDT 24 |
Peak memory | 202388 kb |
Host | smart-4df5f4bb-0147-49f7-ad69-e66d055923ba |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882297047 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 18.sram_ctrl_tl_errors.3882297047 |
Directory | /workspace/18.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3705360278 |
Short name | T1034 |
Test name | |
Test status | |
Simulation time | 239610676 ps |
CPU time | 1.36 seconds |
Started | Jul 11 05:48:30 PM PDT 24 |
Finished | Jul 11 05:48:34 PM PDT 24 |
Peak memory | 202948 kb |
Host | smart-254b913e-bbdf-4f44-83a4-229fd911d26e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705360278 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 18.sram_ctrl_tl_intg_err.3705360278 |
Directory | /workspace/18.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2594517729 |
Short name | T1010 |
Test name | |
Test status | |
Simulation time | 684687794 ps |
CPU time | 3.79 seconds |
Started | Jul 11 05:48:11 PM PDT 24 |
Finished | Jul 11 05:48:21 PM PDT 24 |
Peak memory | 211160 kb |
Host | smart-dd98870e-bba1-40a6-989e-3e1117dd10a5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594517729 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_mem_rw_with_rand_reset.2594517729 |
Directory | /workspace/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1635052926 |
Short name | T1017 |
Test name | |
Test status | |
Simulation time | 89158243 ps |
CPU time | 0.7 seconds |
Started | Jul 11 05:48:13 PM PDT 24 |
Finished | Jul 11 05:48:19 PM PDT 24 |
Peak memory | 202620 kb |
Host | smart-fc12753f-b609-4a8b-a83b-169b91e298b3 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635052926 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 19.sram_ctrl_csr_rw.1635052926 |
Directory | /workspace/19.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.472253005 |
Short name | T107 |
Test name | |
Test status | |
Simulation time | 7092135394 ps |
CPU time | 51.87 seconds |
Started | Jul 11 05:48:15 PM PDT 24 |
Finished | Jul 11 05:49:13 PM PDT 24 |
Peak memory | 203160 kb |
Host | smart-008ec678-5add-4274-add9-cfb5ffea3d81 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472253005 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 19.sram_ctrl_passthru_mem_tl_intg_err.472253005 |
Directory | /workspace/19.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1050554265 |
Short name | T89 |
Test name | |
Test status | |
Simulation time | 29156932 ps |
CPU time | 0.68 seconds |
Started | Jul 11 05:57:16 PM PDT 24 |
Finished | Jul 11 05:57:18 PM PDT 24 |
Peak memory | 202668 kb |
Host | smart-7eeafaba-ea52-4396-811a-1d657b6e7a8e |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050554265 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 19.sram_ctrl_same_csr_outstanding.1050554265 |
Directory | /workspace/19.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.630893299 |
Short name | T968 |
Test name | |
Test status | |
Simulation time | 295804188 ps |
CPU time | 2.58 seconds |
Started | Jul 11 05:48:26 PM PDT 24 |
Finished | Jul 11 05:48:32 PM PDT 24 |
Peak memory | 203024 kb |
Host | smart-bef2b320-a0ee-4d5d-af44-564f229e5e20 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630893299 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_tl_errors.630893299 |
Directory | /workspace/19.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1957359072 |
Short name | T1019 |
Test name | |
Test status | |
Simulation time | 1202159917 ps |
CPU time | 2.32 seconds |
Started | Jul 11 05:48:10 PM PDT 24 |
Finished | Jul 11 05:48:19 PM PDT 24 |
Peak memory | 211140 kb |
Host | smart-1b0c390c-2340-4cdb-9e98-60bada44af8f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957359072 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 19.sram_ctrl_tl_intg_err.1957359072 |
Directory | /workspace/19.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2448989197 |
Short name | T1033 |
Test name | |
Test status | |
Simulation time | 46639037 ps |
CPU time | 0.67 seconds |
Started | Jul 11 05:48:05 PM PDT 24 |
Finished | Jul 11 05:48:12 PM PDT 24 |
Peak memory | 202696 kb |
Host | smart-64793cf0-0d2f-402a-a94e-84458fdc6b3e |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448989197 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.sram_ctrl_csr_aliasing.2448989197 |
Directory | /workspace/2.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.21090438 |
Short name | T67 |
Test name | |
Test status | |
Simulation time | 148027959 ps |
CPU time | 1.83 seconds |
Started | Jul 11 05:48:05 PM PDT 24 |
Finished | Jul 11 05:48:13 PM PDT 24 |
Peak memory | 202920 kb |
Host | smart-6227153b-43b6-41c5-b638-70343249bc27 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21090438 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_bit_bash.21090438 |
Directory | /workspace/2.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.799343980 |
Short name | T1012 |
Test name | |
Test status | |
Simulation time | 18692383 ps |
CPU time | 0.66 seconds |
Started | Jul 11 05:48:00 PM PDT 24 |
Finished | Jul 11 05:48:07 PM PDT 24 |
Peak memory | 202676 kb |
Host | smart-2a37ecb3-4d26-4620-b8f1-9c8671fe319d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799343980 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_hw_reset.799343980 |
Directory | /workspace/2.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2649051280 |
Short name | T1029 |
Test name | |
Test status | |
Simulation time | 1810210261 ps |
CPU time | 4.14 seconds |
Started | Jul 11 05:48:08 PM PDT 24 |
Finished | Jul 11 05:48:19 PM PDT 24 |
Peak memory | 211196 kb |
Host | smart-b46d2930-4f5c-47f9-9789-df8d8f8a3be6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649051280 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_rw_with_rand_reset.2649051280 |
Directory | /workspace/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.4017360732 |
Short name | T1024 |
Test name | |
Test status | |
Simulation time | 15313505 ps |
CPU time | 0.69 seconds |
Started | Jul 11 05:47:56 PM PDT 24 |
Finished | Jul 11 05:48:03 PM PDT 24 |
Peak memory | 202632 kb |
Host | smart-8c7eb4af-34b6-4072-a3ea-246aacc60d73 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017360732 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 2.sram_ctrl_csr_rw.4017360732 |
Directory | /workspace/2.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3418690008 |
Short name | T108 |
Test name | |
Test status | |
Simulation time | 3868018971 ps |
CPU time | 27.67 seconds |
Started | Jul 11 05:47:56 PM PDT 24 |
Finished | Jul 11 05:48:30 PM PDT 24 |
Peak memory | 203144 kb |
Host | smart-026242bb-22b0-4a1b-933b-ad01750dff48 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418690008 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 2.sram_ctrl_passthru_mem_tl_intg_err.3418690008 |
Directory | /workspace/2.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2805661334 |
Short name | T1031 |
Test name | |
Test status | |
Simulation time | 52503231 ps |
CPU time | 0.76 seconds |
Started | Jul 11 05:48:04 PM PDT 24 |
Finished | Jul 11 05:48:11 PM PDT 24 |
Peak memory | 202744 kb |
Host | smart-66fb4812-479e-4fc8-8f76-a8e50cecd8ea |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805661334 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 2.sram_ctrl_same_csr_outstanding.2805661334 |
Directory | /workspace/2.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2200575745 |
Short name | T985 |
Test name | |
Test status | |
Simulation time | 70232865 ps |
CPU time | 3.53 seconds |
Started | Jul 11 05:47:57 PM PDT 24 |
Finished | Jul 11 05:48:06 PM PDT 24 |
Peak memory | 203100 kb |
Host | smart-ca45ba5f-73d5-4c7d-a9e1-bc0c0b714e9e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200575745 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 2.sram_ctrl_tl_errors.2200575745 |
Directory | /workspace/2.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.827719941 |
Short name | T986 |
Test name | |
Test status | |
Simulation time | 18369679 ps |
CPU time | 0.75 seconds |
Started | Jul 11 05:48:05 PM PDT 24 |
Finished | Jul 11 05:48:12 PM PDT 24 |
Peak memory | 202588 kb |
Host | smart-7232e031-2efd-4985-a43e-81b6c3e936cf |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827719941 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_aliasing.827719941 |
Directory | /workspace/3.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3641962295 |
Short name | T87 |
Test name | |
Test status | |
Simulation time | 179380789 ps |
CPU time | 2.18 seconds |
Started | Jul 11 05:48:04 PM PDT 24 |
Finished | Jul 11 05:48:12 PM PDT 24 |
Peak memory | 202976 kb |
Host | smart-dd9af47c-099b-4e48-8cd3-6dad5bc51432 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641962295 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.sram_ctrl_csr_bit_bash.3641962295 |
Directory | /workspace/3.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1320754096 |
Short name | T1018 |
Test name | |
Test status | |
Simulation time | 53089327 ps |
CPU time | 0.67 seconds |
Started | Jul 11 05:48:04 PM PDT 24 |
Finished | Jul 11 05:48:11 PM PDT 24 |
Peak memory | 202712 kb |
Host | smart-6bc30a62-7f87-4a8d-af81-401b3eb80a82 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320754096 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.sram_ctrl_csr_hw_reset.1320754096 |
Directory | /workspace/3.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.665381713 |
Short name | T973 |
Test name | |
Test status | |
Simulation time | 1476791011 ps |
CPU time | 4.68 seconds |
Started | Jul 11 05:48:17 PM PDT 24 |
Finished | Jul 11 05:48:27 PM PDT 24 |
Peak memory | 211132 kb |
Host | smart-d83550de-542a-4ec3-a827-244b5847cabb |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665381713 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_mem_rw_with_rand_reset.665381713 |
Directory | /workspace/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.719457020 |
Short name | T981 |
Test name | |
Test status | |
Simulation time | 31735325 ps |
CPU time | 0.65 seconds |
Started | Jul 11 05:48:03 PM PDT 24 |
Finished | Jul 11 05:48:10 PM PDT 24 |
Peak memory | 202604 kb |
Host | smart-8016e989-7980-4477-b5db-bda398344a05 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719457020 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 3.sram_ctrl_csr_rw.719457020 |
Directory | /workspace/3.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3485050443 |
Short name | T1014 |
Test name | |
Test status | |
Simulation time | 14805591442 ps |
CPU time | 29.06 seconds |
Started | Jul 11 05:48:06 PM PDT 24 |
Finished | Jul 11 05:48:42 PM PDT 24 |
Peak memory | 202932 kb |
Host | smart-447a9ac4-ea07-4139-9143-5d91712f69e5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485050443 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 3.sram_ctrl_passthru_mem_tl_intg_err.3485050443 |
Directory | /workspace/3.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2185110294 |
Short name | T1035 |
Test name | |
Test status | |
Simulation time | 18291659 ps |
CPU time | 0.71 seconds |
Started | Jul 11 05:48:03 PM PDT 24 |
Finished | Jul 11 05:48:10 PM PDT 24 |
Peak memory | 202708 kb |
Host | smart-ec26949b-9264-457d-9f9c-a8b1d1b0187a |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185110294 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 3.sram_ctrl_same_csr_outstanding.2185110294 |
Directory | /workspace/3.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.4018527794 |
Short name | T946 |
Test name | |
Test status | |
Simulation time | 36660290 ps |
CPU time | 3.19 seconds |
Started | Jul 11 05:47:58 PM PDT 24 |
Finished | Jul 11 05:48:06 PM PDT 24 |
Peak memory | 202908 kb |
Host | smart-4cc9b399-db47-4d5c-9527-a869ef9a555f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018527794 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 3.sram_ctrl_tl_errors.4018527794 |
Directory | /workspace/3.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2020210030 |
Short name | T152 |
Test name | |
Test status | |
Simulation time | 514209314 ps |
CPU time | 2.09 seconds |
Started | Jul 11 05:48:06 PM PDT 24 |
Finished | Jul 11 05:48:15 PM PDT 24 |
Peak memory | 211180 kb |
Host | smart-2554c813-948b-4131-ba5b-6de8f5481cbe |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020210030 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 3.sram_ctrl_tl_intg_err.2020210030 |
Directory | /workspace/3.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2566498646 |
Short name | T958 |
Test name | |
Test status | |
Simulation time | 38834320 ps |
CPU time | 0.69 seconds |
Started | Jul 11 05:48:19 PM PDT 24 |
Finished | Jul 11 05:48:25 PM PDT 24 |
Peak memory | 202668 kb |
Host | smart-786864e3-e651-4f0a-9231-a3fb0b97dd89 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566498646 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_aliasing.2566498646 |
Directory | /workspace/4.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3682169163 |
Short name | T1028 |
Test name | |
Test status | |
Simulation time | 46015071 ps |
CPU time | 1.93 seconds |
Started | Jul 11 05:48:04 PM PDT 24 |
Finished | Jul 11 05:48:12 PM PDT 24 |
Peak memory | 202852 kb |
Host | smart-963289f3-4b82-40c2-aae1-6237f0c1a7c6 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682169163 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_bit_bash.3682169163 |
Directory | /workspace/4.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1127211388 |
Short name | T86 |
Test name | |
Test status | |
Simulation time | 13089199 ps |
CPU time | 0.71 seconds |
Started | Jul 11 05:48:04 PM PDT 24 |
Finished | Jul 11 05:48:11 PM PDT 24 |
Peak memory | 202648 kb |
Host | smart-adcdf68b-609a-444a-8a5d-c70ddf3d9c34 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127211388 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_hw_reset.1127211388 |
Directory | /workspace/4.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1348422817 |
Short name | T1011 |
Test name | |
Test status | |
Simulation time | 355688576 ps |
CPU time | 3.61 seconds |
Started | Jul 11 05:48:02 PM PDT 24 |
Finished | Jul 11 05:48:11 PM PDT 24 |
Peak memory | 210896 kb |
Host | smart-92a8c400-a79d-4e32-9841-c000cab4210c |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348422817 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_mem_rw_with_rand_reset.1348422817 |
Directory | /workspace/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.4185220407 |
Short name | T1021 |
Test name | |
Test status | |
Simulation time | 16030985 ps |
CPU time | 0.67 seconds |
Started | Jul 11 05:48:09 PM PDT 24 |
Finished | Jul 11 05:48:16 PM PDT 24 |
Peak memory | 202708 kb |
Host | smart-f81756fd-c764-4329-8034-c6578e936ae6 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185220407 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 4.sram_ctrl_csr_rw.4185220407 |
Directory | /workspace/4.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1603808569 |
Short name | T972 |
Test name | |
Test status | |
Simulation time | 33528846401 ps |
CPU time | 31.56 seconds |
Started | Jul 11 05:48:15 PM PDT 24 |
Finished | Jul 11 05:48:52 PM PDT 24 |
Peak memory | 211268 kb |
Host | smart-c69d8f90-13ea-4c10-aec7-c368ddabaeaf |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603808569 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 4.sram_ctrl_passthru_mem_tl_intg_err.1603808569 |
Directory | /workspace/4.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3295188262 |
Short name | T970 |
Test name | |
Test status | |
Simulation time | 26730583 ps |
CPU time | 0.75 seconds |
Started | Jul 11 05:48:06 PM PDT 24 |
Finished | Jul 11 05:48:13 PM PDT 24 |
Peak memory | 202704 kb |
Host | smart-95965dea-14ed-4caa-a834-3ad27a3a9c0e |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295188262 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 4.sram_ctrl_same_csr_outstanding.3295188262 |
Directory | /workspace/4.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.77096880 |
Short name | T964 |
Test name | |
Test status | |
Simulation time | 29350258 ps |
CPU time | 2.39 seconds |
Started | Jul 11 05:48:01 PM PDT 24 |
Finished | Jul 11 05:48:09 PM PDT 24 |
Peak memory | 211116 kb |
Host | smart-6415790a-3bf1-42ca-aa43-9ddecaaef3b7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77096880 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST _SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_tl_errors.77096880 |
Directory | /workspace/4.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3000548960 |
Short name | T146 |
Test name | |
Test status | |
Simulation time | 621611405 ps |
CPU time | 2.44 seconds |
Started | Jul 11 05:48:19 PM PDT 24 |
Finished | Jul 11 05:48:27 PM PDT 24 |
Peak memory | 211064 kb |
Host | smart-0fff9641-83e6-40f1-8335-1cd777d9ddf9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000548960 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 4.sram_ctrl_tl_intg_err.3000548960 |
Directory | /workspace/4.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2241064950 |
Short name | T966 |
Test name | |
Test status | |
Simulation time | 4874914766 ps |
CPU time | 3.78 seconds |
Started | Jul 11 05:47:59 PM PDT 24 |
Finished | Jul 11 05:48:08 PM PDT 24 |
Peak memory | 211236 kb |
Host | smart-f740e14f-63ce-4c7f-857d-c19b1c8e0c27 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241064950 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_rw_with_rand_reset.2241064950 |
Directory | /workspace/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3665653676 |
Short name | T980 |
Test name | |
Test status | |
Simulation time | 34213808 ps |
CPU time | 0.66 seconds |
Started | Jul 11 05:48:02 PM PDT 24 |
Finished | Jul 11 05:48:08 PM PDT 24 |
Peak memory | 202648 kb |
Host | smart-45773ab0-9e67-4b28-84ab-f15839a7dea6 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665653676 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 5.sram_ctrl_csr_rw.3665653676 |
Directory | /workspace/5.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2018226967 |
Short name | T97 |
Test name | |
Test status | |
Simulation time | 26345216478 ps |
CPU time | 28.53 seconds |
Started | Jul 11 05:48:02 PM PDT 24 |
Finished | Jul 11 05:48:35 PM PDT 24 |
Peak memory | 203116 kb |
Host | smart-89fe0f53-fee3-4548-a725-288cfab030f1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018226967 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 5.sram_ctrl_passthru_mem_tl_intg_err.2018226967 |
Directory | /workspace/5.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1789509639 |
Short name | T111 |
Test name | |
Test status | |
Simulation time | 24031635 ps |
CPU time | 0.85 seconds |
Started | Jul 11 05:48:09 PM PDT 24 |
Finished | Jul 11 05:48:16 PM PDT 24 |
Peak memory | 202712 kb |
Host | smart-f3e49726-1ded-48c8-8ce7-f32256061053 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789509639 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 5.sram_ctrl_same_csr_outstanding.1789509639 |
Directory | /workspace/5.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.4021468806 |
Short name | T1004 |
Test name | |
Test status | |
Simulation time | 152586214 ps |
CPU time | 2.54 seconds |
Started | Jul 11 05:48:01 PM PDT 24 |
Finished | Jul 11 05:48:09 PM PDT 24 |
Peak memory | 212324 kb |
Host | smart-3204800d-5327-495b-83c8-1e679043cffa |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021468806 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 5.sram_ctrl_tl_errors.4021468806 |
Directory | /workspace/5.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3334376767 |
Short name | T991 |
Test name | |
Test status | |
Simulation time | 461120592 ps |
CPU time | 1.57 seconds |
Started | Jul 11 05:47:58 PM PDT 24 |
Finished | Jul 11 05:48:05 PM PDT 24 |
Peak memory | 211148 kb |
Host | smart-f88dd1e6-c39c-40a3-8bf6-21ea34483592 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334376767 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 5.sram_ctrl_tl_intg_err.3334376767 |
Directory | /workspace/5.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2991465593 |
Short name | T959 |
Test name | |
Test status | |
Simulation time | 1357681577 ps |
CPU time | 3.22 seconds |
Started | Jul 11 05:48:09 PM PDT 24 |
Finished | Jul 11 05:48:19 PM PDT 24 |
Peak memory | 210896 kb |
Host | smart-2818b5cc-865e-4e99-af8f-92be3cbca690 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991465593 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_mem_rw_with_rand_reset.2991465593 |
Directory | /workspace/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.742776719 |
Short name | T961 |
Test name | |
Test status | |
Simulation time | 43774882 ps |
CPU time | 0.64 seconds |
Started | Jul 11 05:48:03 PM PDT 24 |
Finished | Jul 11 05:48:09 PM PDT 24 |
Peak memory | 202564 kb |
Host | smart-2728a6f4-6fa1-41ba-a60e-0b186dbe406e |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742776719 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 6.sram_ctrl_csr_rw.742776719 |
Directory | /workspace/6.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1388134499 |
Short name | T1020 |
Test name | |
Test status | |
Simulation time | 3704970424 ps |
CPU time | 28.41 seconds |
Started | Jul 11 05:48:03 PM PDT 24 |
Finished | Jul 11 05:48:37 PM PDT 24 |
Peak memory | 202936 kb |
Host | smart-60332624-3565-4769-95d0-27f58a4d1151 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388134499 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 6.sram_ctrl_passthru_mem_tl_intg_err.1388134499 |
Directory | /workspace/6.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.2256762405 |
Short name | T1001 |
Test name | |
Test status | |
Simulation time | 53864884 ps |
CPU time | 0.79 seconds |
Started | Jul 11 05:48:20 PM PDT 24 |
Finished | Jul 11 05:48:26 PM PDT 24 |
Peak memory | 202760 kb |
Host | smart-3ec8d785-290b-47e0-961b-bb3d66e9bae2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256762405 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 6.sram_ctrl_same_csr_outstanding.2256762405 |
Directory | /workspace/6.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3272780975 |
Short name | T975 |
Test name | |
Test status | |
Simulation time | 83219210 ps |
CPU time | 2.86 seconds |
Started | Jul 11 05:48:09 PM PDT 24 |
Finished | Jul 11 05:48:18 PM PDT 24 |
Peak memory | 211096 kb |
Host | smart-a4440f6f-8abd-4b59-bc64-db9251348fa2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272780975 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 6.sram_ctrl_tl_errors.3272780975 |
Directory | /workspace/6.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1459750209 |
Short name | T155 |
Test name | |
Test status | |
Simulation time | 205342821 ps |
CPU time | 1.47 seconds |
Started | Jul 11 05:48:10 PM PDT 24 |
Finished | Jul 11 05:48:18 PM PDT 24 |
Peak memory | 211284 kb |
Host | smart-3b3864c9-36a2-4f11-9f87-4e15f70d7246 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459750209 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 6.sram_ctrl_tl_intg_err.1459750209 |
Directory | /workspace/6.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3965447644 |
Short name | T1002 |
Test name | |
Test status | |
Simulation time | 3126898871 ps |
CPU time | 4.43 seconds |
Started | Jul 11 05:48:09 PM PDT 24 |
Finished | Jul 11 05:48:19 PM PDT 24 |
Peak memory | 212752 kb |
Host | smart-99ffca59-84bb-44e4-96dc-261f057c686e |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965447644 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_mem_rw_with_rand_reset.3965447644 |
Directory | /workspace/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2947210310 |
Short name | T114 |
Test name | |
Test status | |
Simulation time | 26094266 ps |
CPU time | 0.69 seconds |
Started | Jul 11 05:47:58 PM PDT 24 |
Finished | Jul 11 05:48:04 PM PDT 24 |
Peak memory | 202712 kb |
Host | smart-d5e0ee1f-0c55-4f21-b45c-49ec66d74c5d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947210310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 7.sram_ctrl_csr_rw.2947210310 |
Directory | /workspace/7.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3426019841 |
Short name | T983 |
Test name | |
Test status | |
Simulation time | 7791268321 ps |
CPU time | 49.42 seconds |
Started | Jul 11 05:48:00 PM PDT 24 |
Finished | Jul 11 05:48:55 PM PDT 24 |
Peak memory | 203072 kb |
Host | smart-9935060c-4f9a-457a-85ef-4c94efab6531 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426019841 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 7.sram_ctrl_passthru_mem_tl_intg_err.3426019841 |
Directory | /workspace/7.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3552252514 |
Short name | T113 |
Test name | |
Test status | |
Simulation time | 31520303 ps |
CPU time | 0.79 seconds |
Started | Jul 11 05:48:09 PM PDT 24 |
Finished | Jul 11 05:48:16 PM PDT 24 |
Peak memory | 202660 kb |
Host | smart-14a7a348-1536-4792-95dc-ec113cab0e8d |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552252514 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 7.sram_ctrl_same_csr_outstanding.3552252514 |
Directory | /workspace/7.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3408519969 |
Short name | T949 |
Test name | |
Test status | |
Simulation time | 470403214 ps |
CPU time | 4.12 seconds |
Started | Jul 11 05:48:09 PM PDT 24 |
Finished | Jul 11 05:48:20 PM PDT 24 |
Peak memory | 211084 kb |
Host | smart-f4260b1f-cf29-4cbf-aa47-0beafe446c1b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408519969 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 7.sram_ctrl_tl_errors.3408519969 |
Directory | /workspace/7.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.365320710 |
Short name | T154 |
Test name | |
Test status | |
Simulation time | 790842296 ps |
CPU time | 3.53 seconds |
Started | Jul 11 05:48:19 PM PDT 24 |
Finished | Jul 11 05:48:28 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-e9e7ee1b-962d-410e-aa90-b0747a0fbfd7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365320710 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 7.sram_ctrl_tl_intg_err.365320710 |
Directory | /workspace/7.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1877886522 |
Short name | T957 |
Test name | |
Test status | |
Simulation time | 362982454 ps |
CPU time | 3.2 seconds |
Started | Jul 11 05:47:59 PM PDT 24 |
Finished | Jul 11 05:48:08 PM PDT 24 |
Peak memory | 202692 kb |
Host | smart-f89cd3db-b474-4afb-bc9e-66465cbc5f6e |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877886522 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_rw_with_rand_reset.1877886522 |
Directory | /workspace/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.335071937 |
Short name | T1009 |
Test name | |
Test status | |
Simulation time | 14338929 ps |
CPU time | 0.68 seconds |
Started | Jul 11 05:48:00 PM PDT 24 |
Finished | Jul 11 05:48:06 PM PDT 24 |
Peak memory | 202668 kb |
Host | smart-318d8dfe-155d-4fe7-9a08-65e366bc4d1c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335071937 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 8.sram_ctrl_csr_rw.335071937 |
Directory | /workspace/8.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1616436655 |
Short name | T98 |
Test name | |
Test status | |
Simulation time | 7041396563 ps |
CPU time | 51.09 seconds |
Started | Jul 11 05:48:02 PM PDT 24 |
Finished | Jul 11 05:48:59 PM PDT 24 |
Peak memory | 203144 kb |
Host | smart-54bf244b-58e7-469c-94b2-31a8b0d6fb66 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616436655 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 8.sram_ctrl_passthru_mem_tl_intg_err.1616436655 |
Directory | /workspace/8.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.895628229 |
Short name | T1030 |
Test name | |
Test status | |
Simulation time | 18271249 ps |
CPU time | 0.76 seconds |
Started | Jul 11 05:48:02 PM PDT 24 |
Finished | Jul 11 05:48:09 PM PDT 24 |
Peak memory | 202696 kb |
Host | smart-6ec998c1-94af-4704-9036-05db1cb01973 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895628229 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 8.sram_ctrl_same_csr_outstanding.895628229 |
Directory | /workspace/8.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2987736541 |
Short name | T984 |
Test name | |
Test status | |
Simulation time | 362086423 ps |
CPU time | 4.65 seconds |
Started | Jul 11 05:48:00 PM PDT 24 |
Finished | Jul 11 05:48:11 PM PDT 24 |
Peak memory | 211340 kb |
Host | smart-67f677fd-3ada-43db-8725-b1819a764e65 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987736541 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 8.sram_ctrl_tl_errors.2987736541 |
Directory | /workspace/8.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3369767927 |
Short name | T979 |
Test name | |
Test status | |
Simulation time | 145765373 ps |
CPU time | 1.59 seconds |
Started | Jul 11 05:48:05 PM PDT 24 |
Finished | Jul 11 05:48:12 PM PDT 24 |
Peak memory | 211200 kb |
Host | smart-0fffb716-8780-4bc7-b304-af6d20887a3c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369767927 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 8.sram_ctrl_tl_intg_err.3369767927 |
Directory | /workspace/8.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2207564055 |
Short name | T1008 |
Test name | |
Test status | |
Simulation time | 2832391389 ps |
CPU time | 3.48 seconds |
Started | Jul 11 05:48:17 PM PDT 24 |
Finished | Jul 11 05:48:26 PM PDT 24 |
Peak memory | 210984 kb |
Host | smart-b03865f4-2257-4729-876b-67d05194ab1c |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207564055 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_mem_rw_with_rand_reset.2207564055 |
Directory | /workspace/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2208029964 |
Short name | T978 |
Test name | |
Test status | |
Simulation time | 78309636 ps |
CPU time | 0.64 seconds |
Started | Jul 11 05:48:19 PM PDT 24 |
Finished | Jul 11 05:48:25 PM PDT 24 |
Peak memory | 202604 kb |
Host | smart-a19111ea-bbd8-476d-9318-65cd39fa16a9 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208029964 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 9.sram_ctrl_csr_rw.2208029964 |
Directory | /workspace/9.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1496750751 |
Short name | T92 |
Test name | |
Test status | |
Simulation time | 28346720770 ps |
CPU time | 27.99 seconds |
Started | Jul 11 05:48:01 PM PDT 24 |
Finished | Jul 11 05:48:35 PM PDT 24 |
Peak memory | 203060 kb |
Host | smart-f5a399ca-1621-4457-b445-3cfe3ca7862f |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496750751 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 9.sram_ctrl_passthru_mem_tl_intg_err.1496750751 |
Directory | /workspace/9.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2918070991 |
Short name | T982 |
Test name | |
Test status | |
Simulation time | 14449294 ps |
CPU time | 0.72 seconds |
Started | Jul 11 05:48:02 PM PDT 24 |
Finished | Jul 11 05:48:08 PM PDT 24 |
Peak memory | 202688 kb |
Host | smart-b465cbb7-083a-401b-b3a2-7c18f1fe539e |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918070991 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 9.sram_ctrl_same_csr_outstanding.2918070991 |
Directory | /workspace/9.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1315366656 |
Short name | T1015 |
Test name | |
Test status | |
Simulation time | 241551056 ps |
CPU time | 2.49 seconds |
Started | Jul 11 05:48:06 PM PDT 24 |
Finished | Jul 11 05:48:15 PM PDT 24 |
Peak memory | 211064 kb |
Host | smart-ec08a363-0bb2-48f5-b6bf-c530be24bc44 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315366656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 9.sram_ctrl_tl_errors.1315366656 |
Directory | /workspace/9.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2387413842 |
Short name | T150 |
Test name | |
Test status | |
Simulation time | 336713188 ps |
CPU time | 2.38 seconds |
Started | Jul 11 05:48:03 PM PDT 24 |
Finished | Jul 11 05:48:11 PM PDT 24 |
Peak memory | 211180 kb |
Host | smart-bddad7a0-040a-47c7-9279-6e174a217ebd |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387413842 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 9.sram_ctrl_tl_intg_err.2387413842 |
Directory | /workspace/9.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_access_during_key_req.3953589759 |
Short name | T782 |
Test name | |
Test status | |
Simulation time | 11167486243 ps |
CPU time | 784.55 seconds |
Started | Jul 11 06:02:54 PM PDT 24 |
Finished | Jul 11 06:16:18 PM PDT 24 |
Peak memory | 379772 kb |
Host | smart-3eec41c9-37ff-4f42-9b2a-114fff75be5c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953589759 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.sram_ctrl_access_during_key_req.3953589759 |
Directory | /workspace/0.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_alert_test.3556137046 |
Short name | T690 |
Test name | |
Test status | |
Simulation time | 89113243 ps |
CPU time | 0.66 seconds |
Started | Jul 11 06:03:00 PM PDT 24 |
Finished | Jul 11 06:03:20 PM PDT 24 |
Peak memory | 202436 kb |
Host | smart-f3a5dd95-11f8-4c8f-8e54-d9da6e504e62 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556137046 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_alert_test.3556137046 |
Directory | /workspace/0.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_bijection.3283973449 |
Short name | T536 |
Test name | |
Test status | |
Simulation time | 9617932878 ps |
CPU time | 643.53 seconds |
Started | Jul 11 06:02:53 PM PDT 24 |
Finished | Jul 11 06:13:56 PM PDT 24 |
Peak memory | 203708 kb |
Host | smart-e66bb839-2a0f-4223-b524-ebf12fabfa00 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283973449 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection. 3283973449 |
Directory | /workspace/0.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_executable.2847743720 |
Short name | T390 |
Test name | |
Test status | |
Simulation time | 12095964968 ps |
CPU time | 689.88 seconds |
Started | Jul 11 06:02:55 PM PDT 24 |
Finished | Jul 11 06:14:45 PM PDT 24 |
Peak memory | 365424 kb |
Host | smart-9e2f964c-8fe1-4789-834b-7dc3527ee7e1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847743720 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_executabl e.2847743720 |
Directory | /workspace/0.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_lc_escalation.3880376400 |
Short name | T870 |
Test name | |
Test status | |
Simulation time | 14380376029 ps |
CPU time | 22.5 seconds |
Started | Jul 11 06:03:01 PM PDT 24 |
Finished | Jul 11 06:03:42 PM PDT 24 |
Peak memory | 202872 kb |
Host | smart-a3b82266-3178-4893-9ba2-59161e072e93 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880376400 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_esc alation.3880376400 |
Directory | /workspace/0.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_max_throughput.827006674 |
Short name | T285 |
Test name | |
Test status | |
Simulation time | 3044095074 ps |
CPU time | 45.7 seconds |
Started | Jul 11 06:02:51 PM PDT 24 |
Finished | Jul 11 06:03:57 PM PDT 24 |
Peak memory | 307472 kb |
Host | smart-bf71573e-038a-440f-abad-fa437df772c7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827006674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.sram_ctrl_max_throughput.827006674 |
Directory | /workspace/0.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_mem_partial_access.231587843 |
Short name | T59 |
Test name | |
Test status | |
Simulation time | 11623657404 ps |
CPU time | 147.48 seconds |
Started | Jul 11 06:02:58 PM PDT 24 |
Finished | Jul 11 06:05:44 PM PDT 24 |
Peak memory | 211100 kb |
Host | smart-2e882689-d995-4649-ac5c-edecaf2652b7 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231587843 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0. sram_ctrl_mem_partial_access.231587843 |
Directory | /workspace/0.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_mem_walk.2843329223 |
Short name | T740 |
Test name | |
Test status | |
Simulation time | 24364842980 ps |
CPU time | 348.72 seconds |
Started | Jul 11 06:02:51 PM PDT 24 |
Finished | Jul 11 06:09:00 PM PDT 24 |
Peak memory | 211072 kb |
Host | smart-6e48212b-d20b-4340-94ff-1ea5148b2aa7 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843329223 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl _mem_walk.2843329223 |
Directory | /workspace/0.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_multiple_keys.2562123285 |
Short name | T708 |
Test name | |
Test status | |
Simulation time | 55526532127 ps |
CPU time | 992.23 seconds |
Started | Jul 11 06:02:44 PM PDT 24 |
Finished | Jul 11 06:19:36 PM PDT 24 |
Peak memory | 376632 kb |
Host | smart-99fc2a49-8eba-4e7f-8cf1-fbb595742207 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562123285 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multip le_keys.2562123285 |
Directory | /workspace/0.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_partial_access.788924704 |
Short name | T468 |
Test name | |
Test status | |
Simulation time | 16590769179 ps |
CPU time | 26.48 seconds |
Started | Jul 11 06:02:55 PM PDT 24 |
Finished | Jul 11 06:03:42 PM PDT 24 |
Peak memory | 202844 kb |
Host | smart-0b11fbd2-d6e9-44fc-b5a9-84abdfa19274 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788924704 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sr am_ctrl_partial_access.788924704 |
Directory | /workspace/0.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.1342105291 |
Short name | T677 |
Test name | |
Test status | |
Simulation time | 16013563583 ps |
CPU time | 387.92 seconds |
Started | Jul 11 06:02:57 PM PDT 24 |
Finished | Jul 11 06:09:45 PM PDT 24 |
Peak memory | 202852 kb |
Host | smart-e3bb9d60-7aef-4bfb-92e7-b3ec1c80b517 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342105291 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 0.sram_ctrl_partial_access_b2b.1342105291 |
Directory | /workspace/0.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_ram_cfg.4121608566 |
Short name | T733 |
Test name | |
Test status | |
Simulation time | 359552211 ps |
CPU time | 3.32 seconds |
Started | Jul 11 06:02:58 PM PDT 24 |
Finished | Jul 11 06:03:20 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-f43fe7f3-3633-429a-832f-9dbeb2bc93fb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121608566 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.4121608566 |
Directory | /workspace/0.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_regwen.831917623 |
Short name | T427 |
Test name | |
Test status | |
Simulation time | 23652139048 ps |
CPU time | 966.08 seconds |
Started | Jul 11 06:02:56 PM PDT 24 |
Finished | Jul 11 06:19:22 PM PDT 24 |
Peak memory | 379748 kb |
Host | smart-f2cbbc6c-766f-4cd0-b451-f165510199f4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831917623 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.831917623 |
Directory | /workspace/0.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_smoke.3134987348 |
Short name | T180 |
Test name | |
Test status | |
Simulation time | 884939863 ps |
CPU time | 15.71 seconds |
Started | Jul 11 06:02:50 PM PDT 24 |
Finished | Jul 11 06:03:26 PM PDT 24 |
Peak memory | 202788 kb |
Host | smart-3e1c64f3-f69d-49f2-984c-72ad1b9e714d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134987348 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.3134987348 |
Directory | /workspace/0.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_stress_all.459597988 |
Short name | T875 |
Test name | |
Test status | |
Simulation time | 240317643151 ps |
CPU time | 2833.72 seconds |
Started | Jul 11 06:02:53 PM PDT 24 |
Finished | Jul 11 06:50:27 PM PDT 24 |
Peak memory | 378704 kb |
Host | smart-d81d9f30-a9ad-4b88-8712-9555cef87471 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459597988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 0.sram_ctrl_stress_all.459597988 |
Directory | /workspace/0.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1924811582 |
Short name | T652 |
Test name | |
Test status | |
Simulation time | 8745512512 ps |
CPU time | 65 seconds |
Started | Jul 11 06:02:52 PM PDT 24 |
Finished | Jul 11 06:04:18 PM PDT 24 |
Peak memory | 252560 kb |
Host | smart-48a0acd1-c1a6-445a-aa2b-1a584dc5782c |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1924811582 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all_with_rand_reset.1924811582 |
Directory | /workspace/0.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_stress_pipeline.1237223439 |
Short name | T426 |
Test name | |
Test status | |
Simulation time | 14357962287 ps |
CPU time | 439.64 seconds |
Started | Jul 11 06:02:58 PM PDT 24 |
Finished | Jul 11 06:10:36 PM PDT 24 |
Peak memory | 202868 kb |
Host | smart-dd230c9c-0d10-4f4a-9d61-85dd9ee5f86e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237223439 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .sram_ctrl_stress_pipeline.1237223439 |
Directory | /workspace/0.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.1079325942 |
Short name | T540 |
Test name | |
Test status | |
Simulation time | 714993067 ps |
CPU time | 10.95 seconds |
Started | Jul 11 06:02:55 PM PDT 24 |
Finished | Jul 11 06:03:26 PM PDT 24 |
Peak memory | 235520 kb |
Host | smart-3a28d83a-46a2-4a68-ad83-c0035427588d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079325942 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.sram_ctrl_throughput_w_partial_write.1079325942 |
Directory | /workspace/0.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_access_during_key_req.133968352 |
Short name | T309 |
Test name | |
Test status | |
Simulation time | 12685899654 ps |
CPU time | 696.28 seconds |
Started | Jul 11 06:03:01 PM PDT 24 |
Finished | Jul 11 06:14:56 PM PDT 24 |
Peak memory | 377508 kb |
Host | smart-c7ecf371-3d6a-4cfa-882f-5e171268fd47 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133968352 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 1.sram_ctrl_access_during_key_req.133968352 |
Directory | /workspace/1.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_bijection.1947335430 |
Short name | T437 |
Test name | |
Test status | |
Simulation time | 73185395930 ps |
CPU time | 654.79 seconds |
Started | Jul 11 06:02:57 PM PDT 24 |
Finished | Jul 11 06:14:12 PM PDT 24 |
Peak memory | 203440 kb |
Host | smart-bd0b65d3-2f88-49f4-af5f-17a62d569bde |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947335430 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection. 1947335430 |
Directory | /workspace/1.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_executable.4022431657 |
Short name | T478 |
Test name | |
Test status | |
Simulation time | 211935634120 ps |
CPU time | 824.61 seconds |
Started | Jul 11 06:02:59 PM PDT 24 |
Finished | Jul 11 06:17:02 PM PDT 24 |
Peak memory | 372556 kb |
Host | smart-7d4e5553-da4b-40f8-b252-168794cdb11c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022431657 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executabl e.4022431657 |
Directory | /workspace/1.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_lc_escalation.1443596058 |
Short name | T260 |
Test name | |
Test status | |
Simulation time | 11111031978 ps |
CPU time | 32.42 seconds |
Started | Jul 11 06:02:59 PM PDT 24 |
Finished | Jul 11 06:03:50 PM PDT 24 |
Peak memory | 202852 kb |
Host | smart-ab6a29a3-d377-480b-8389-21b3f92d97e7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443596058 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_esc alation.1443596058 |
Directory | /workspace/1.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_max_throughput.1686471128 |
Short name | T138 |
Test name | |
Test status | |
Simulation time | 780598929 ps |
CPU time | 76.4 seconds |
Started | Jul 11 06:02:52 PM PDT 24 |
Finished | Jul 11 06:04:29 PM PDT 24 |
Peak memory | 335672 kb |
Host | smart-6d892e93-1c50-4007-a586-8d3ffe83fc6e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686471128 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.sram_ctrl_max_throughput.1686471128 |
Directory | /workspace/1.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_mem_partial_access.2615828040 |
Short name | T768 |
Test name | |
Test status | |
Simulation time | 2742323448 ps |
CPU time | 84.1 seconds |
Started | Jul 11 06:02:57 PM PDT 24 |
Finished | Jul 11 06:04:41 PM PDT 24 |
Peak memory | 211024 kb |
Host | smart-d6c72ae7-ab60-4cc7-9c73-11ca5a9ccd48 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615828040 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .sram_ctrl_mem_partial_access.2615828040 |
Directory | /workspace/1.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_mem_walk.4046501738 |
Short name | T49 |
Test name | |
Test status | |
Simulation time | 172327143148 ps |
CPU time | 353.38 seconds |
Started | Jul 11 06:02:58 PM PDT 24 |
Finished | Jul 11 06:09:10 PM PDT 24 |
Peak memory | 210992 kb |
Host | smart-9126a61a-bd8b-4389-a6c2-52481bcf37eb |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046501738 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl _mem_walk.4046501738 |
Directory | /workspace/1.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_multiple_keys.3673265168 |
Short name | T736 |
Test name | |
Test status | |
Simulation time | 130890299620 ps |
CPU time | 1538.87 seconds |
Started | Jul 11 06:02:56 PM PDT 24 |
Finished | Jul 11 06:28:55 PM PDT 24 |
Peak memory | 371592 kb |
Host | smart-5fb35f49-d456-4e77-bae1-a35a6950a0c3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673265168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multip le_keys.3673265168 |
Directory | /workspace/1.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_partial_access.3348856204 |
Short name | T78 |
Test name | |
Test status | |
Simulation time | 6043068582 ps |
CPU time | 20.66 seconds |
Started | Jul 11 06:02:58 PM PDT 24 |
Finished | Jul 11 06:03:37 PM PDT 24 |
Peak memory | 202808 kb |
Host | smart-17f38502-37e1-43d1-b2ae-582e544387b4 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348856204 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.s ram_ctrl_partial_access.3348856204 |
Directory | /workspace/1.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.1007464095 |
Short name | T817 |
Test name | |
Test status | |
Simulation time | 39667629348 ps |
CPU time | 380.63 seconds |
Started | Jul 11 06:02:52 PM PDT 24 |
Finished | Jul 11 06:09:34 PM PDT 24 |
Peak memory | 202856 kb |
Host | smart-eb0e3f19-91f0-4f27-8e5f-7869ed5d3ae2 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007464095 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 1.sram_ctrl_partial_access_b2b.1007464095 |
Directory | /workspace/1.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_ram_cfg.2491322042 |
Short name | T462 |
Test name | |
Test status | |
Simulation time | 355738712 ps |
CPU time | 3.45 seconds |
Started | Jul 11 06:03:01 PM PDT 24 |
Finished | Jul 11 06:03:23 PM PDT 24 |
Peak memory | 202856 kb |
Host | smart-db9b5381-af63-4428-bff8-6704a3100d75 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491322042 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.2491322042 |
Directory | /workspace/1.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_regwen.2383976642 |
Short name | T140 |
Test name | |
Test status | |
Simulation time | 2719519665 ps |
CPU time | 928.33 seconds |
Started | Jul 11 06:02:59 PM PDT 24 |
Finished | Jul 11 06:18:46 PM PDT 24 |
Peak memory | 378748 kb |
Host | smart-364772dd-28d9-42b5-ad76-b9224a843a5a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383976642 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.2383976642 |
Directory | /workspace/1.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_sec_cm.418218061 |
Short name | T18 |
Test name | |
Test status | |
Simulation time | 1320156877 ps |
CPU time | 2.19 seconds |
Started | Jul 11 06:03:04 PM PDT 24 |
Finished | Jul 11 06:03:24 PM PDT 24 |
Peak memory | 222280 kb |
Host | smart-e988678d-ce02-451f-8c41-21539d2fc008 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418218061 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .sram_ctrl_sec_cm.418218061 |
Directory | /workspace/1.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_smoke.3250242346 |
Short name | T239 |
Test name | |
Test status | |
Simulation time | 1530223167 ps |
CPU time | 20.25 seconds |
Started | Jul 11 06:02:55 PM PDT 24 |
Finished | Jul 11 06:03:35 PM PDT 24 |
Peak memory | 202820 kb |
Host | smart-1680a6c0-81a3-45fa-bd1a-3b3fe91a10eb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250242346 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.3250242346 |
Directory | /workspace/1.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_stress_all.644747733 |
Short name | T614 |
Test name | |
Test status | |
Simulation time | 26982211176 ps |
CPU time | 3414.67 seconds |
Started | Jul 11 06:02:58 PM PDT 24 |
Finished | Jul 11 07:00:12 PM PDT 24 |
Peak memory | 381840 kb |
Host | smart-b543f5d5-2e51-4e29-95d3-d8faaede85e6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644747733 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 1.sram_ctrl_stress_all.644747733 |
Directory | /workspace/1.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.1552167641 |
Short name | T72 |
Test name | |
Test status | |
Simulation time | 3956835989 ps |
CPU time | 31.31 seconds |
Started | Jul 11 06:03:03 PM PDT 24 |
Finished | Jul 11 06:03:52 PM PDT 24 |
Peak memory | 211200 kb |
Host | smart-94ea748f-cbcb-488e-ad88-fd6158e96485 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1552167641 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all_with_rand_reset.1552167641 |
Directory | /workspace/1.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_stress_pipeline.2403140134 |
Short name | T860 |
Test name | |
Test status | |
Simulation time | 13722395001 ps |
CPU time | 178.42 seconds |
Started | Jul 11 06:02:53 PM PDT 24 |
Finished | Jul 11 06:06:11 PM PDT 24 |
Peak memory | 202908 kb |
Host | smart-f361f7ba-5955-4ef1-8ba4-398aeadc2d42 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403140134 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .sram_ctrl_stress_pipeline.2403140134 |
Directory | /workspace/1.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.1025119534 |
Short name | T637 |
Test name | |
Test status | |
Simulation time | 733101948 ps |
CPU time | 14.78 seconds |
Started | Jul 11 06:03:00 PM PDT 24 |
Finished | Jul 11 06:03:34 PM PDT 24 |
Peak memory | 251832 kb |
Host | smart-cdbf8c4e-eb29-4469-8d89-4ee938755e1d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025119534 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.sram_ctrl_throughput_w_partial_write.1025119534 |
Directory | /workspace/1.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_access_during_key_req.739153388 |
Short name | T660 |
Test name | |
Test status | |
Simulation time | 35849547556 ps |
CPU time | 639.07 seconds |
Started | Jul 11 06:03:27 PM PDT 24 |
Finished | Jul 11 06:14:19 PM PDT 24 |
Peak memory | 376040 kb |
Host | smart-35a98d4a-1143-4e4e-abcf-52bd884c1259 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739153388 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 10.sram_ctrl_access_during_key_req.739153388 |
Directory | /workspace/10.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_alert_test.1617305012 |
Short name | T632 |
Test name | |
Test status | |
Simulation time | 20308112 ps |
CPU time | 0.66 seconds |
Started | Jul 11 06:03:20 PM PDT 24 |
Finished | Jul 11 06:03:35 PM PDT 24 |
Peak memory | 202600 kb |
Host | smart-b9de883b-6543-4317-a134-59e62765a2bf |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617305012 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_alert_test.1617305012 |
Directory | /workspace/10.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_bijection.2137027006 |
Short name | T186 |
Test name | |
Test status | |
Simulation time | 46284438870 ps |
CPU time | 1731.62 seconds |
Started | Jul 11 06:03:15 PM PDT 24 |
Finished | Jul 11 06:32:22 PM PDT 24 |
Peak memory | 203540 kb |
Host | smart-1aa6b4e0-dc75-4fab-a015-56c3dae4b729 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137027006 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection .2137027006 |
Directory | /workspace/10.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_executable.4119423970 |
Short name | T162 |
Test name | |
Test status | |
Simulation time | 14091305806 ps |
CPU time | 1124.74 seconds |
Started | Jul 11 06:03:18 PM PDT 24 |
Finished | Jul 11 06:22:18 PM PDT 24 |
Peak memory | 376848 kb |
Host | smart-485ab783-a6d2-4b7d-9370-201df1ccef3f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119423970 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executab le.4119423970 |
Directory | /workspace/10.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_lc_escalation.383680540 |
Short name | T487 |
Test name | |
Test status | |
Simulation time | 19993125092 ps |
CPU time | 20.77 seconds |
Started | Jul 11 06:03:17 PM PDT 24 |
Finished | Jul 11 06:03:53 PM PDT 24 |
Peak memory | 202932 kb |
Host | smart-763c83ad-173d-41a0-83c8-1ee753ca77e1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383680540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_esc alation.383680540 |
Directory | /workspace/10.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_max_throughput.1242215480 |
Short name | T275 |
Test name | |
Test status | |
Simulation time | 3573388940 ps |
CPU time | 27.5 seconds |
Started | Jul 11 06:03:21 PM PDT 24 |
Finished | Jul 11 06:04:02 PM PDT 24 |
Peak memory | 285652 kb |
Host | smart-70c69c1a-bfd2-4f5f-b4e1-b2288d5cc41a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242215480 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 10.sram_ctrl_max_throughput.1242215480 |
Directory | /workspace/10.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_mem_partial_access.2390998177 |
Short name | T277 |
Test name | |
Test status | |
Simulation time | 2554141696 ps |
CPU time | 74.05 seconds |
Started | Jul 11 06:03:20 PM PDT 24 |
Finished | Jul 11 06:04:48 PM PDT 24 |
Peak memory | 211068 kb |
Host | smart-27954134-2f39-495e-a12b-4a8a415ad5ea |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390998177 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 0.sram_ctrl_mem_partial_access.2390998177 |
Directory | /workspace/10.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_mem_walk.1089107681 |
Short name | T201 |
Test name | |
Test status | |
Simulation time | 12341539859 ps |
CPU time | 127.37 seconds |
Started | Jul 11 06:03:24 PM PDT 24 |
Finished | Jul 11 06:05:44 PM PDT 24 |
Peak memory | 211036 kb |
Host | smart-ba06766a-dfcf-45b5-a07d-1e548ce29f01 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089107681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctr l_mem_walk.1089107681 |
Directory | /workspace/10.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_multiple_keys.2451102310 |
Short name | T480 |
Test name | |
Test status | |
Simulation time | 26375348346 ps |
CPU time | 485.13 seconds |
Started | Jul 11 06:03:13 PM PDT 24 |
Finished | Jul 11 06:11:33 PM PDT 24 |
Peak memory | 375612 kb |
Host | smart-763ffd09-7df5-46db-9eb0-79b34d6aa834 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451102310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multi ple_keys.2451102310 |
Directory | /workspace/10.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_partial_access.2244264001 |
Short name | T56 |
Test name | |
Test status | |
Simulation time | 1932589143 ps |
CPU time | 12.39 seconds |
Started | Jul 11 06:03:19 PM PDT 24 |
Finished | Jul 11 06:03:47 PM PDT 24 |
Peak memory | 202784 kb |
Host | smart-c5aa1398-b619-4609-b051-1fa87f220c47 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244264001 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10. sram_ctrl_partial_access.2244264001 |
Directory | /workspace/10.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.1849438620 |
Short name | T203 |
Test name | |
Test status | |
Simulation time | 11541957741 ps |
CPU time | 289.7 seconds |
Started | Jul 11 06:03:22 PM PDT 24 |
Finished | Jul 11 06:08:26 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-36e7d001-7cf6-418e-b7a5-f1039bb25567 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849438620 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 10.sram_ctrl_partial_access_b2b.1849438620 |
Directory | /workspace/10.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_ram_cfg.356454092 |
Short name | T608 |
Test name | |
Test status | |
Simulation time | 1353451896 ps |
CPU time | 3.38 seconds |
Started | Jul 11 06:03:25 PM PDT 24 |
Finished | Jul 11 06:03:41 PM PDT 24 |
Peak memory | 202840 kb |
Host | smart-1a2ec9f9-6836-4929-ab1b-a790415d54c3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356454092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.356454092 |
Directory | /workspace/10.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_regwen.1531818199 |
Short name | T573 |
Test name | |
Test status | |
Simulation time | 8562097527 ps |
CPU time | 237.08 seconds |
Started | Jul 11 06:03:19 PM PDT 24 |
Finished | Jul 11 06:07:30 PM PDT 24 |
Peak memory | 336436 kb |
Host | smart-7ca83c7c-82ab-4706-bc46-f90c03984a8d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531818199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.1531818199 |
Directory | /workspace/10.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_smoke.1123810716 |
Short name | T676 |
Test name | |
Test status | |
Simulation time | 2120009549 ps |
CPU time | 17.36 seconds |
Started | Jul 11 06:03:14 PM PDT 24 |
Finished | Jul 11 06:03:47 PM PDT 24 |
Peak memory | 202780 kb |
Host | smart-1d263de7-43d9-4c65-a3bf-ac8e872ec317 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123810716 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.1123810716 |
Directory | /workspace/10.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_stress_all.1560219619 |
Short name | T914 |
Test name | |
Test status | |
Simulation time | 100314053900 ps |
CPU time | 2431.01 seconds |
Started | Jul 11 06:03:18 PM PDT 24 |
Finished | Jul 11 06:44:04 PM PDT 24 |
Peak memory | 381864 kb |
Host | smart-34242fb3-622e-4040-ae5a-c10d1d772f52 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560219619 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 10.sram_ctrl_stress_all.1560219619 |
Directory | /workspace/10.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3879995962 |
Short name | T363 |
Test name | |
Test status | |
Simulation time | 4642645841 ps |
CPU time | 31.08 seconds |
Started | Jul 11 06:03:19 PM PDT 24 |
Finished | Jul 11 06:04:04 PM PDT 24 |
Peak memory | 211104 kb |
Host | smart-4669804f-d1f3-4f1c-a098-9f578bf641c7 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3879995962 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all_with_rand_reset.3879995962 |
Directory | /workspace/10.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_stress_pipeline.3636342958 |
Short name | T489 |
Test name | |
Test status | |
Simulation time | 5175699026 ps |
CPU time | 293.29 seconds |
Started | Jul 11 06:03:28 PM PDT 24 |
Finished | Jul 11 06:08:33 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-23893e74-24d4-456e-919e-3b69a7bdc9fd |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636342958 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 0.sram_ctrl_stress_pipeline.3636342958 |
Directory | /workspace/10.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.4164841326 |
Short name | T176 |
Test name | |
Test status | |
Simulation time | 926406944 ps |
CPU time | 36.37 seconds |
Started | Jul 11 06:03:28 PM PDT 24 |
Finished | Jul 11 06:04:17 PM PDT 24 |
Peak memory | 293760 kb |
Host | smart-5a1dce2a-b75a-43a2-ab46-3e84bbe0f04a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164841326 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 10.sram_ctrl_throughput_w_partial_write.4164841326 |
Directory | /workspace/10.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_access_during_key_req.2032984658 |
Short name | T687 |
Test name | |
Test status | |
Simulation time | 6018999949 ps |
CPU time | 270.48 seconds |
Started | Jul 11 06:03:17 PM PDT 24 |
Finished | Jul 11 06:08:03 PM PDT 24 |
Peak memory | 350800 kb |
Host | smart-ff0e3406-7cb5-4f42-be8d-5cf545f8aa79 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032984658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 11.sram_ctrl_access_during_key_req.2032984658 |
Directory | /workspace/11.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_alert_test.3987434837 |
Short name | T716 |
Test name | |
Test status | |
Simulation time | 21934954 ps |
CPU time | 0.65 seconds |
Started | Jul 11 06:03:31 PM PDT 24 |
Finished | Jul 11 06:03:43 PM PDT 24 |
Peak memory | 202620 kb |
Host | smart-3acc5290-a058-4825-9af7-d2f9a809a09f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987434837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_alert_test.3987434837 |
Directory | /workspace/11.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_bijection.1079152575 |
Short name | T181 |
Test name | |
Test status | |
Simulation time | 19816408811 ps |
CPU time | 675.24 seconds |
Started | Jul 11 06:03:25 PM PDT 24 |
Finished | Jul 11 06:14:53 PM PDT 24 |
Peak memory | 203472 kb |
Host | smart-6e7d6615-3432-4eab-960a-6b66e8108bcb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079152575 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection .1079152575 |
Directory | /workspace/11.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_executable.3453183620 |
Short name | T634 |
Test name | |
Test status | |
Simulation time | 9556929389 ps |
CPU time | 896.52 seconds |
Started | Jul 11 06:03:38 PM PDT 24 |
Finished | Jul 11 06:18:45 PM PDT 24 |
Peak memory | 379812 kb |
Host | smart-8cebebe3-b2b6-4b2e-894d-ae8961355684 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453183620 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executab le.3453183620 |
Directory | /workspace/11.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_lc_escalation.4245370988 |
Short name | T667 |
Test name | |
Test status | |
Simulation time | 93503481827 ps |
CPU time | 43.69 seconds |
Started | Jul 11 06:03:21 PM PDT 24 |
Finished | Jul 11 06:04:19 PM PDT 24 |
Peak memory | 202940 kb |
Host | smart-c51f7378-ec49-4216-814c-55713a094403 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245370988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_es calation.4245370988 |
Directory | /workspace/11.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_max_throughput.653585110 |
Short name | T375 |
Test name | |
Test status | |
Simulation time | 669015886 ps |
CPU time | 6 seconds |
Started | Jul 11 06:03:19 PM PDT 24 |
Finished | Jul 11 06:03:40 PM PDT 24 |
Peak memory | 210868 kb |
Host | smart-67b93dcf-65a6-460d-9b96-6875af1effed |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653585110 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 11.sram_ctrl_max_throughput.653585110 |
Directory | /workspace/11.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_mem_partial_access.2792288097 |
Short name | T738 |
Test name | |
Test status | |
Simulation time | 50534862747 ps |
CPU time | 173.23 seconds |
Started | Jul 11 06:03:32 PM PDT 24 |
Finished | Jul 11 06:06:36 PM PDT 24 |
Peak memory | 214988 kb |
Host | smart-9851adce-c659-4b4b-992e-51b7b77bc793 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792288097 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 1.sram_ctrl_mem_partial_access.2792288097 |
Directory | /workspace/11.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_mem_walk.1765044460 |
Short name | T525 |
Test name | |
Test status | |
Simulation time | 86170736571 ps |
CPU time | 339.73 seconds |
Started | Jul 11 06:03:29 PM PDT 24 |
Finished | Jul 11 06:09:20 PM PDT 24 |
Peak memory | 210984 kb |
Host | smart-5a0662d2-1c3c-4670-9244-f75c038c5a2d |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765044460 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctr l_mem_walk.1765044460 |
Directory | /workspace/11.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_multiple_keys.2140492469 |
Short name | T767 |
Test name | |
Test status | |
Simulation time | 6248824377 ps |
CPU time | 375.05 seconds |
Started | Jul 11 06:03:14 PM PDT 24 |
Finished | Jul 11 06:09:44 PM PDT 24 |
Peak memory | 374680 kb |
Host | smart-9a5af7b0-fb95-4902-9ceb-cfa0f3518979 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140492469 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multi ple_keys.2140492469 |
Directory | /workspace/11.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_partial_access.4018303042 |
Short name | T831 |
Test name | |
Test status | |
Simulation time | 434842381 ps |
CPU time | 24.81 seconds |
Started | Jul 11 06:03:19 PM PDT 24 |
Finished | Jul 11 06:03:59 PM PDT 24 |
Peak memory | 277428 kb |
Host | smart-da1ef47e-726a-49cd-a367-3ec77d2ee239 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018303042 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11. sram_ctrl_partial_access.4018303042 |
Directory | /workspace/11.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.2129816838 |
Short name | T453 |
Test name | |
Test status | |
Simulation time | 19496334593 ps |
CPU time | 260.45 seconds |
Started | Jul 11 06:03:18 PM PDT 24 |
Finished | Jul 11 06:07:53 PM PDT 24 |
Peak memory | 202876 kb |
Host | smart-f06447fa-f7cf-4ed8-b2e3-f778c190183b |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129816838 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 11.sram_ctrl_partial_access_b2b.2129816838 |
Directory | /workspace/11.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_ram_cfg.1598747498 |
Short name | T672 |
Test name | |
Test status | |
Simulation time | 363951985 ps |
CPU time | 3.16 seconds |
Started | Jul 11 06:03:31 PM PDT 24 |
Finished | Jul 11 06:03:45 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-9f60da3c-2af7-4e48-a847-6d4c5cd34dd7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598747498 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.1598747498 |
Directory | /workspace/11.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_regwen.2877575130 |
Short name | T911 |
Test name | |
Test status | |
Simulation time | 15564414359 ps |
CPU time | 873.85 seconds |
Started | Jul 11 06:03:30 PM PDT 24 |
Finished | Jul 11 06:18:14 PM PDT 24 |
Peak memory | 379760 kb |
Host | smart-5b281bca-5f8e-40f8-b824-bdf69d3130f5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877575130 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.2877575130 |
Directory | /workspace/11.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_smoke.2801893310 |
Short name | T446 |
Test name | |
Test status | |
Simulation time | 816987801 ps |
CPU time | 7.98 seconds |
Started | Jul 11 06:03:19 PM PDT 24 |
Finished | Jul 11 06:03:42 PM PDT 24 |
Peak memory | 202696 kb |
Host | smart-76826945-1ade-49f4-b552-b50eae086701 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801893310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.2801893310 |
Directory | /workspace/11.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_stress_all.2958102133 |
Short name | T642 |
Test name | |
Test status | |
Simulation time | 72523683743 ps |
CPU time | 5230.39 seconds |
Started | Jul 11 06:03:29 PM PDT 24 |
Finished | Jul 11 07:30:51 PM PDT 24 |
Peak memory | 381836 kb |
Host | smart-754719b1-15e4-4249-bb35-8627260295ab |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958102133 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 11.sram_ctrl_stress_all.2958102133 |
Directory | /workspace/11.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.2454591703 |
Short name | T924 |
Test name | |
Test status | |
Simulation time | 1067315767 ps |
CPU time | 19.2 seconds |
Started | Jul 11 06:03:30 PM PDT 24 |
Finished | Jul 11 06:04:01 PM PDT 24 |
Peak memory | 211276 kb |
Host | smart-3307ea4d-ff52-4044-8984-0975b7b7736c |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2454591703 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all_with_rand_reset.2454591703 |
Directory | /workspace/11.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_stress_pipeline.3192116260 |
Short name | T524 |
Test name | |
Test status | |
Simulation time | 6090310902 ps |
CPU time | 372.18 seconds |
Started | Jul 11 06:03:19 PM PDT 24 |
Finished | Jul 11 06:09:45 PM PDT 24 |
Peak memory | 202832 kb |
Host | smart-45737aee-caa2-49c2-bb35-043e3b7ba2aa |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192116260 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 1.sram_ctrl_stress_pipeline.3192116260 |
Directory | /workspace/11.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.325871692 |
Short name | T311 |
Test name | |
Test status | |
Simulation time | 3268427319 ps |
CPU time | 115.63 seconds |
Started | Jul 11 06:03:16 PM PDT 24 |
Finished | Jul 11 06:05:26 PM PDT 24 |
Peak memory | 371508 kb |
Host | smart-70345ab9-b1ff-4e23-b3cd-8d371291bff5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325871692 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 11.sram_ctrl_throughput_w_partial_write.325871692 |
Directory | /workspace/11.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_access_during_key_req.2537843869 |
Short name | T444 |
Test name | |
Test status | |
Simulation time | 9352803115 ps |
CPU time | 699.97 seconds |
Started | Jul 11 06:03:30 PM PDT 24 |
Finished | Jul 11 06:15:22 PM PDT 24 |
Peak memory | 379780 kb |
Host | smart-79766820-0368-4edf-9caf-8adf09c5beda |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537843869 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 12.sram_ctrl_access_during_key_req.2537843869 |
Directory | /workspace/12.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_alert_test.755931006 |
Short name | T383 |
Test name | |
Test status | |
Simulation time | 14974235 ps |
CPU time | 0.66 seconds |
Started | Jul 11 06:03:33 PM PDT 24 |
Finished | Jul 11 06:03:45 PM PDT 24 |
Peak memory | 202428 kb |
Host | smart-d72a10e4-b43d-41ef-929d-4cca7c5cf49e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755931006 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_alert_test.755931006 |
Directory | /workspace/12.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_bijection.3524917926 |
Short name | T939 |
Test name | |
Test status | |
Simulation time | 496931551260 ps |
CPU time | 2027.08 seconds |
Started | Jul 11 06:03:30 PM PDT 24 |
Finished | Jul 11 06:37:28 PM PDT 24 |
Peak memory | 203584 kb |
Host | smart-646aa59d-78cf-4905-b9ff-a6f4a484953a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524917926 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection .3524917926 |
Directory | /workspace/12.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_executable.1518230820 |
Short name | T531 |
Test name | |
Test status | |
Simulation time | 142349540791 ps |
CPU time | 2335.48 seconds |
Started | Jul 11 06:03:31 PM PDT 24 |
Finished | Jul 11 06:42:38 PM PDT 24 |
Peak memory | 379776 kb |
Host | smart-b6b0fc5d-ce5d-4a11-99f4-a810fd433736 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518230820 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executab le.1518230820 |
Directory | /workspace/12.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_lc_escalation.1423574877 |
Short name | T316 |
Test name | |
Test status | |
Simulation time | 179781953743 ps |
CPU time | 137 seconds |
Started | Jul 11 06:03:35 PM PDT 24 |
Finished | Jul 11 06:06:02 PM PDT 24 |
Peak memory | 211148 kb |
Host | smart-c1c8083b-94d6-4ae8-ac12-351271820f45 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423574877 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_es calation.1423574877 |
Directory | /workspace/12.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_max_throughput.3019126246 |
Short name | T753 |
Test name | |
Test status | |
Simulation time | 3059033658 ps |
CPU time | 38.9 seconds |
Started | Jul 11 06:03:30 PM PDT 24 |
Finished | Jul 11 06:04:20 PM PDT 24 |
Peak memory | 300968 kb |
Host | smart-ffff79bb-71c4-41ff-8438-a02f38838eae |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019126246 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 12.sram_ctrl_max_throughput.3019126246 |
Directory | /workspace/12.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_mem_partial_access.3360785338 |
Short name | T656 |
Test name | |
Test status | |
Simulation time | 18222653659 ps |
CPU time | 156.73 seconds |
Started | Jul 11 06:03:29 PM PDT 24 |
Finished | Jul 11 06:06:17 PM PDT 24 |
Peak memory | 219120 kb |
Host | smart-0c3f6b1d-dd5b-414c-81e2-3a404d274655 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360785338 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 2.sram_ctrl_mem_partial_access.3360785338 |
Directory | /workspace/12.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_mem_walk.2359057955 |
Short name | T533 |
Test name | |
Test status | |
Simulation time | 18711064880 ps |
CPU time | 342.4 seconds |
Started | Jul 11 06:03:37 PM PDT 24 |
Finished | Jul 11 06:09:30 PM PDT 24 |
Peak memory | 211016 kb |
Host | smart-280ab75f-3b8d-41b2-969c-dbde544a7a8b |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359057955 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctr l_mem_walk.2359057955 |
Directory | /workspace/12.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_multiple_keys.4280683069 |
Short name | T842 |
Test name | |
Test status | |
Simulation time | 1721179576 ps |
CPU time | 107.99 seconds |
Started | Jul 11 06:03:28 PM PDT 24 |
Finished | Jul 11 06:05:28 PM PDT 24 |
Peak memory | 342756 kb |
Host | smart-5fd73cc1-1221-415f-a016-e88dccbdb18f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280683069 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multi ple_keys.4280683069 |
Directory | /workspace/12.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_partial_access.1189547598 |
Short name | T321 |
Test name | |
Test status | |
Simulation time | 1005147213 ps |
CPU time | 16.55 seconds |
Started | Jul 11 06:03:29 PM PDT 24 |
Finished | Jul 11 06:03:57 PM PDT 24 |
Peak memory | 202744 kb |
Host | smart-54a076b1-a218-4347-8d75-9a26132c4912 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189547598 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12. sram_ctrl_partial_access.1189547598 |
Directory | /workspace/12.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.2379339587 |
Short name | T228 |
Test name | |
Test status | |
Simulation time | 372280949908 ps |
CPU time | 602.19 seconds |
Started | Jul 11 06:03:30 PM PDT 24 |
Finished | Jul 11 06:13:44 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-c7950245-324c-46e9-a57a-31aae3b81c78 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379339587 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 12.sram_ctrl_partial_access_b2b.2379339587 |
Directory | /workspace/12.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_ram_cfg.1744445805 |
Short name | T303 |
Test name | |
Test status | |
Simulation time | 1305844367 ps |
CPU time | 3.47 seconds |
Started | Jul 11 06:03:32 PM PDT 24 |
Finished | Jul 11 06:03:46 PM PDT 24 |
Peak memory | 202868 kb |
Host | smart-a8586005-b1a8-49f9-bd45-fbe304e8fdc6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744445805 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.1744445805 |
Directory | /workspace/12.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_regwen.2521634701 |
Short name | T520 |
Test name | |
Test status | |
Simulation time | 27927151476 ps |
CPU time | 896.42 seconds |
Started | Jul 11 06:03:38 PM PDT 24 |
Finished | Jul 11 06:18:45 PM PDT 24 |
Peak memory | 374572 kb |
Host | smart-c6fb79b5-1d29-4e0d-b455-5a27ada98286 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521634701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.2521634701 |
Directory | /workspace/12.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_smoke.2634125653 |
Short name | T184 |
Test name | |
Test status | |
Simulation time | 1465003652 ps |
CPU time | 23.15 seconds |
Started | Jul 11 06:03:35 PM PDT 24 |
Finished | Jul 11 06:04:08 PM PDT 24 |
Peak memory | 202744 kb |
Host | smart-bebad225-7a2a-42f2-bcce-e9c1e1ad5a10 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634125653 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.2634125653 |
Directory | /workspace/12.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_stress_all.790175655 |
Short name | T32 |
Test name | |
Test status | |
Simulation time | 147399137504 ps |
CPU time | 5933.85 seconds |
Started | Jul 11 06:03:37 PM PDT 24 |
Finished | Jul 11 07:42:41 PM PDT 24 |
Peak memory | 389004 kb |
Host | smart-20a57758-18e4-44bc-98ef-88f2149bfbd7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790175655 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 12.sram_ctrl_stress_all.790175655 |
Directory | /workspace/12.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.3139080549 |
Short name | T264 |
Test name | |
Test status | |
Simulation time | 500328539 ps |
CPU time | 9.92 seconds |
Started | Jul 11 06:03:31 PM PDT 24 |
Finished | Jul 11 06:03:52 PM PDT 24 |
Peak memory | 211024 kb |
Host | smart-499ea7dd-3ef5-4cc9-995e-4ddbfcc711a4 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3139080549 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all_with_rand_reset.3139080549 |
Directory | /workspace/12.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_stress_pipeline.2712957209 |
Short name | T460 |
Test name | |
Test status | |
Simulation time | 38162258378 ps |
CPU time | 345.81 seconds |
Started | Jul 11 06:03:27 PM PDT 24 |
Finished | Jul 11 06:09:25 PM PDT 24 |
Peak memory | 202876 kb |
Host | smart-e9dd6ac2-546a-4a02-a1bd-87a77bc19ebd |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712957209 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 2.sram_ctrl_stress_pipeline.2712957209 |
Directory | /workspace/12.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.1405079938 |
Short name | T11 |
Test name | |
Test status | |
Simulation time | 708758075 ps |
CPU time | 9.2 seconds |
Started | Jul 11 06:03:31 PM PDT 24 |
Finished | Jul 11 06:03:51 PM PDT 24 |
Peak memory | 225636 kb |
Host | smart-afd91ac2-09d8-41b0-808d-ae7a5a150621 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405079938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 12.sram_ctrl_throughput_w_partial_write.1405079938 |
Directory | /workspace/12.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_access_during_key_req.566113379 |
Short name | T215 |
Test name | |
Test status | |
Simulation time | 34058813749 ps |
CPU time | 1409.14 seconds |
Started | Jul 11 06:03:41 PM PDT 24 |
Finished | Jul 11 06:27:20 PM PDT 24 |
Peak memory | 380796 kb |
Host | smart-e4536a62-c150-4d46-aee1-d1af069bdaf8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566113379 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 13.sram_ctrl_access_during_key_req.566113379 |
Directory | /workspace/13.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_alert_test.2047452004 |
Short name | T424 |
Test name | |
Test status | |
Simulation time | 12959223 ps |
CPU time | 0.66 seconds |
Started | Jul 11 06:03:44 PM PDT 24 |
Finished | Jul 11 06:03:55 PM PDT 24 |
Peak memory | 202372 kb |
Host | smart-a1edd0bc-a47e-4793-bd91-957ec72fd636 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047452004 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_alert_test.2047452004 |
Directory | /workspace/13.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_bijection.1081640426 |
Short name | T166 |
Test name | |
Test status | |
Simulation time | 99715037010 ps |
CPU time | 1868.34 seconds |
Started | Jul 11 06:03:35 PM PDT 24 |
Finished | Jul 11 06:34:54 PM PDT 24 |
Peak memory | 203208 kb |
Host | smart-003e41fc-efd5-4eaf-83bd-470efd8355c8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081640426 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection .1081640426 |
Directory | /workspace/13.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_executable.3377072324 |
Short name | T499 |
Test name | |
Test status | |
Simulation time | 35193369814 ps |
CPU time | 810.85 seconds |
Started | Jul 11 06:03:40 PM PDT 24 |
Finished | Jul 11 06:17:21 PM PDT 24 |
Peak memory | 371636 kb |
Host | smart-bca440da-043c-4ede-8379-47744d552bb8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377072324 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_executab le.3377072324 |
Directory | /workspace/13.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_lc_escalation.2002227234 |
Short name | T715 |
Test name | |
Test status | |
Simulation time | 26534244405 ps |
CPU time | 39.06 seconds |
Started | Jul 11 06:03:42 PM PDT 24 |
Finished | Jul 11 06:04:31 PM PDT 24 |
Peak memory | 202872 kb |
Host | smart-9e3eb57b-0775-4c4d-a64d-9c1882c5ccc2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002227234 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_es calation.2002227234 |
Directory | /workspace/13.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_max_throughput.1506016509 |
Short name | T770 |
Test name | |
Test status | |
Simulation time | 3093548910 ps |
CPU time | 53.92 seconds |
Started | Jul 11 06:03:37 PM PDT 24 |
Finished | Jul 11 06:04:41 PM PDT 24 |
Peak memory | 332596 kb |
Host | smart-27b793f3-7d38-400a-b298-25ea35dbc4e7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506016509 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 13.sram_ctrl_max_throughput.1506016509 |
Directory | /workspace/13.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_mem_partial_access.3566300128 |
Short name | T469 |
Test name | |
Test status | |
Simulation time | 3882338698 ps |
CPU time | 136.76 seconds |
Started | Jul 11 06:03:38 PM PDT 24 |
Finished | Jul 11 06:06:04 PM PDT 24 |
Peak memory | 219168 kb |
Host | smart-353ea6d4-8779-4cb8-b23c-077ca54a33d0 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566300128 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 3.sram_ctrl_mem_partial_access.3566300128 |
Directory | /workspace/13.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_mem_walk.1881159870 |
Short name | T712 |
Test name | |
Test status | |
Simulation time | 72037349739 ps |
CPU time | 361.22 seconds |
Started | Jul 11 06:03:39 PM PDT 24 |
Finished | Jul 11 06:09:50 PM PDT 24 |
Peak memory | 210988 kb |
Host | smart-aa9ffaec-510e-40e4-af4e-85d730b0bc14 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881159870 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctr l_mem_walk.1881159870 |
Directory | /workspace/13.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_multiple_keys.1372330578 |
Short name | T454 |
Test name | |
Test status | |
Simulation time | 8444431129 ps |
CPU time | 979.32 seconds |
Started | Jul 11 06:03:36 PM PDT 24 |
Finished | Jul 11 06:20:05 PM PDT 24 |
Peak memory | 377760 kb |
Host | smart-cd14fa68-1228-491d-ac9c-0dce6ea923ee |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372330578 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multi ple_keys.1372330578 |
Directory | /workspace/13.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_partial_access.2028752737 |
Short name | T590 |
Test name | |
Test status | |
Simulation time | 783636363 ps |
CPU time | 10 seconds |
Started | Jul 11 06:03:40 PM PDT 24 |
Finished | Jul 11 06:04:00 PM PDT 24 |
Peak memory | 236688 kb |
Host | smart-8317bbea-7fea-4116-ad05-bb7762bfb770 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028752737 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13. sram_ctrl_partial_access.2028752737 |
Directory | /workspace/13.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.2396048317 |
Short name | T916 |
Test name | |
Test status | |
Simulation time | 319342873120 ps |
CPU time | 563.44 seconds |
Started | Jul 11 06:03:42 PM PDT 24 |
Finished | Jul 11 06:13:15 PM PDT 24 |
Peak memory | 202984 kb |
Host | smart-d77ff350-c089-48c0-a694-d112cf0ca5ae |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396048317 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 13.sram_ctrl_partial_access_b2b.2396048317 |
Directory | /workspace/13.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_ram_cfg.2380028006 |
Short name | T310 |
Test name | |
Test status | |
Simulation time | 1342956687 ps |
CPU time | 3.55 seconds |
Started | Jul 11 06:03:37 PM PDT 24 |
Finished | Jul 11 06:03:50 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-cb37d5e4-bb75-496c-aed4-03d74400b700 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380028006 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.2380028006 |
Directory | /workspace/13.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_regwen.2800729744 |
Short name | T431 |
Test name | |
Test status | |
Simulation time | 14808897020 ps |
CPU time | 1414.58 seconds |
Started | Jul 11 06:03:42 PM PDT 24 |
Finished | Jul 11 06:27:26 PM PDT 24 |
Peak memory | 379724 kb |
Host | smart-cddd630d-9c32-4892-896c-012fb2bc5cf5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800729744 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.2800729744 |
Directory | /workspace/13.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_smoke.3601761992 |
Short name | T734 |
Test name | |
Test status | |
Simulation time | 847639214 ps |
CPU time | 17.63 seconds |
Started | Jul 11 06:03:40 PM PDT 24 |
Finished | Jul 11 06:04:07 PM PDT 24 |
Peak memory | 202748 kb |
Host | smart-65ea3bc9-5cc7-45d0-af8e-e2c81d860263 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601761992 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.3601761992 |
Directory | /workspace/13.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_stress_pipeline.3785910444 |
Short name | T815 |
Test name | |
Test status | |
Simulation time | 21756528336 ps |
CPU time | 373.01 seconds |
Started | Jul 11 06:03:44 PM PDT 24 |
Finished | Jul 11 06:10:07 PM PDT 24 |
Peak memory | 202800 kb |
Host | smart-f8277839-9ebd-4d7a-aca9-109b9459a28d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785910444 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 3.sram_ctrl_stress_pipeline.3785910444 |
Directory | /workspace/13.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.47025674 |
Short name | T584 |
Test name | |
Test status | |
Simulation time | 2544919057 ps |
CPU time | 54.6 seconds |
Started | Jul 11 06:03:40 PM PDT 24 |
Finished | Jul 11 06:04:44 PM PDT 24 |
Peak memory | 304112 kb |
Host | smart-1fe8fcec-bbb6-45fe-945f-d3281a6ec57e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47025674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 13.sram_ctrl_throughput_w_partial_write.47025674 |
Directory | /workspace/13.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_access_during_key_req.662617086 |
Short name | T909 |
Test name | |
Test status | |
Simulation time | 50149010298 ps |
CPU time | 903.02 seconds |
Started | Jul 11 06:03:40 PM PDT 24 |
Finished | Jul 11 06:18:54 PM PDT 24 |
Peak memory | 378884 kb |
Host | smart-47e71112-93aa-49a5-b0b2-ba562183cf13 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662617086 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 14.sram_ctrl_access_during_key_req.662617086 |
Directory | /workspace/14.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_alert_test.1451748587 |
Short name | T621 |
Test name | |
Test status | |
Simulation time | 35926525 ps |
CPU time | 0.67 seconds |
Started | Jul 11 06:03:38 PM PDT 24 |
Finished | Jul 11 06:03:49 PM PDT 24 |
Peak memory | 202692 kb |
Host | smart-6de32bdb-1920-4f44-b72d-171816973b8d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451748587 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_alert_test.1451748587 |
Directory | /workspace/14.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_bijection.3773517171 |
Short name | T743 |
Test name | |
Test status | |
Simulation time | 32159103533 ps |
CPU time | 1148.5 seconds |
Started | Jul 11 06:03:40 PM PDT 24 |
Finished | Jul 11 06:22:59 PM PDT 24 |
Peak memory | 203668 kb |
Host | smart-d9b9761e-97fa-4283-84b9-1f2976c5d988 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773517171 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection .3773517171 |
Directory | /workspace/14.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_executable.810271925 |
Short name | T556 |
Test name | |
Test status | |
Simulation time | 16956067092 ps |
CPU time | 1036.51 seconds |
Started | Jul 11 06:03:36 PM PDT 24 |
Finished | Jul 11 06:21:02 PM PDT 24 |
Peak memory | 377716 kb |
Host | smart-9399ebe8-c470-4e07-99a5-90bf3c6d2bb9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810271925 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executabl e.810271925 |
Directory | /workspace/14.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_max_throughput.4183197823 |
Short name | T347 |
Test name | |
Test status | |
Simulation time | 761513452 ps |
CPU time | 88.2 seconds |
Started | Jul 11 06:03:34 PM PDT 24 |
Finished | Jul 11 06:05:12 PM PDT 24 |
Peak memory | 332912 kb |
Host | smart-de88e9bb-fa7a-4f5c-9ab8-2987226031dd |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183197823 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 14.sram_ctrl_max_throughput.4183197823 |
Directory | /workspace/14.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_mem_partial_access.2401053854 |
Short name | T529 |
Test name | |
Test status | |
Simulation time | 12070819055 ps |
CPU time | 68.38 seconds |
Started | Jul 11 06:03:39 PM PDT 24 |
Finished | Jul 11 06:04:57 PM PDT 24 |
Peak memory | 211512 kb |
Host | smart-dc990abb-c7ff-4ce8-b237-667f72bd8238 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401053854 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 4.sram_ctrl_mem_partial_access.2401053854 |
Directory | /workspace/14.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_mem_walk.2816829960 |
Short name | T472 |
Test name | |
Test status | |
Simulation time | 14415003475 ps |
CPU time | 323.18 seconds |
Started | Jul 11 06:03:38 PM PDT 24 |
Finished | Jul 11 06:09:11 PM PDT 24 |
Peak memory | 210964 kb |
Host | smart-63e504e2-bc50-4175-8bdd-c691992ecc2d |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816829960 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctr l_mem_walk.2816829960 |
Directory | /workspace/14.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_multiple_keys.2952446000 |
Short name | T217 |
Test name | |
Test status | |
Simulation time | 21241260353 ps |
CPU time | 630.28 seconds |
Started | Jul 11 06:03:43 PM PDT 24 |
Finished | Jul 11 06:14:23 PM PDT 24 |
Peak memory | 377760 kb |
Host | smart-a6c7d36e-2d44-4773-9fc2-46645470c1f8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952446000 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multi ple_keys.2952446000 |
Directory | /workspace/14.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_partial_access.147266003 |
Short name | T554 |
Test name | |
Test status | |
Simulation time | 826134819 ps |
CPU time | 54.5 seconds |
Started | Jul 11 06:03:46 PM PDT 24 |
Finished | Jul 11 06:04:51 PM PDT 24 |
Peak memory | 324348 kb |
Host | smart-537b9904-9d18-4bcb-9cd8-9aa7e0d5786e |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147266003 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.s ram_ctrl_partial_access.147266003 |
Directory | /workspace/14.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.639554466 |
Short name | T5 |
Test name | |
Test status | |
Simulation time | 15420394800 ps |
CPU time | 428.88 seconds |
Started | Jul 11 06:03:41 PM PDT 24 |
Finished | Jul 11 06:11:00 PM PDT 24 |
Peak memory | 202868 kb |
Host | smart-219bf567-6e26-46c8-8cbc-391ad7222042 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639554466 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 14.sram_ctrl_partial_access_b2b.639554466 |
Directory | /workspace/14.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_ram_cfg.3724557550 |
Short name | T900 |
Test name | |
Test status | |
Simulation time | 793187408 ps |
CPU time | 3.57 seconds |
Started | Jul 11 06:03:37 PM PDT 24 |
Finished | Jul 11 06:03:50 PM PDT 24 |
Peak memory | 202844 kb |
Host | smart-40ed96c6-71f0-4194-83ec-221143b56227 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724557550 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.3724557550 |
Directory | /workspace/14.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_regwen.3810483421 |
Short name | T886 |
Test name | |
Test status | |
Simulation time | 34556305213 ps |
CPU time | 669.98 seconds |
Started | Jul 11 06:03:40 PM PDT 24 |
Finished | Jul 11 06:15:00 PM PDT 24 |
Peak memory | 371780 kb |
Host | smart-ff93f786-8d15-43f7-9014-1d3471dec75c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810483421 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.3810483421 |
Directory | /workspace/14.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_smoke.2788851044 |
Short name | T945 |
Test name | |
Test status | |
Simulation time | 689948797 ps |
CPU time | 6.89 seconds |
Started | Jul 11 06:03:37 PM PDT 24 |
Finished | Jul 11 06:03:53 PM PDT 24 |
Peak memory | 202788 kb |
Host | smart-875fc1f6-3fb7-4688-914d-b08d81240d1f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788851044 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.2788851044 |
Directory | /workspace/14.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_stress_all.3121626431 |
Short name | T68 |
Test name | |
Test status | |
Simulation time | 232675004459 ps |
CPU time | 2657.08 seconds |
Started | Jul 11 06:03:38 PM PDT 24 |
Finished | Jul 11 06:48:06 PM PDT 24 |
Peak memory | 375800 kb |
Host | smart-d536b3d1-76df-4d90-b73c-e2b830605436 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121626431 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 14.sram_ctrl_stress_all.3121626431 |
Directory | /workspace/14.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_stress_pipeline.2466020772 |
Short name | T358 |
Test name | |
Test status | |
Simulation time | 16523875143 ps |
CPU time | 257.51 seconds |
Started | Jul 11 06:03:46 PM PDT 24 |
Finished | Jul 11 06:08:13 PM PDT 24 |
Peak memory | 202832 kb |
Host | smart-7117cb6b-945c-4b4c-a639-d694b9e5f718 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466020772 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 4.sram_ctrl_stress_pipeline.2466020772 |
Directory | /workspace/14.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.2106611845 |
Short name | T23 |
Test name | |
Test status | |
Simulation time | 794951637 ps |
CPU time | 79.16 seconds |
Started | Jul 11 06:03:41 PM PDT 24 |
Finished | Jul 11 06:05:10 PM PDT 24 |
Peak memory | 336716 kb |
Host | smart-6d4b854e-8b8f-4793-a7af-33424b4bb032 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106611845 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 14.sram_ctrl_throughput_w_partial_write.2106611845 |
Directory | /workspace/14.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_access_during_key_req.2421550190 |
Short name | T120 |
Test name | |
Test status | |
Simulation time | 11187622468 ps |
CPU time | 397.77 seconds |
Started | Jul 11 06:03:43 PM PDT 24 |
Finished | Jul 11 06:10:31 PM PDT 24 |
Peak memory | 359236 kb |
Host | smart-f90440d8-5c97-49eb-a12f-96eb891864f2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421550190 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 15.sram_ctrl_access_during_key_req.2421550190 |
Directory | /workspace/15.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_alert_test.517773300 |
Short name | T38 |
Test name | |
Test status | |
Simulation time | 18222434 ps |
CPU time | 0.66 seconds |
Started | Jul 11 06:03:42 PM PDT 24 |
Finished | Jul 11 06:03:53 PM PDT 24 |
Peak memory | 202584 kb |
Host | smart-858ca2d7-dd25-4e59-95f9-a96c120a54b7 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517773300 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_alert_test.517773300 |
Directory | /workspace/15.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_bijection.3528651165 |
Short name | T675 |
Test name | |
Test status | |
Simulation time | 159534365674 ps |
CPU time | 1119.4 seconds |
Started | Jul 11 06:03:44 PM PDT 24 |
Finished | Jul 11 06:22:33 PM PDT 24 |
Peak memory | 203352 kb |
Host | smart-84b74ab6-e10a-4dc6-ba54-1cd0442ad0cf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528651165 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection .3528651165 |
Directory | /workspace/15.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_executable.4231945601 |
Short name | T307 |
Test name | |
Test status | |
Simulation time | 17308686935 ps |
CPU time | 512.01 seconds |
Started | Jul 11 06:03:42 PM PDT 24 |
Finished | Jul 11 06:12:24 PM PDT 24 |
Peak memory | 378336 kb |
Host | smart-03862d90-577f-4bd2-bd7f-54e5acc0f3ce |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231945601 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_executab le.4231945601 |
Directory | /workspace/15.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_lc_escalation.2179137410 |
Short name | T488 |
Test name | |
Test status | |
Simulation time | 13546069337 ps |
CPU time | 81.15 seconds |
Started | Jul 11 06:03:41 PM PDT 24 |
Finished | Jul 11 06:05:12 PM PDT 24 |
Peak memory | 211084 kb |
Host | smart-9e675df7-3012-4b71-8db8-6acd755a168a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179137410 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_es calation.2179137410 |
Directory | /workspace/15.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_max_throughput.795379203 |
Short name | T403 |
Test name | |
Test status | |
Simulation time | 735658360 ps |
CPU time | 22.36 seconds |
Started | Jul 11 06:03:42 PM PDT 24 |
Finished | Jul 11 06:04:14 PM PDT 24 |
Peak memory | 275908 kb |
Host | smart-a27bddc1-fdbd-4d2e-92ed-46319c07adfb |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795379203 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 15.sram_ctrl_max_throughput.795379203 |
Directory | /workspace/15.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_mem_partial_access.743275822 |
Short name | T103 |
Test name | |
Test status | |
Simulation time | 2896920998 ps |
CPU time | 78.35 seconds |
Started | Jul 11 06:03:43 PM PDT 24 |
Finished | Jul 11 06:05:11 PM PDT 24 |
Peak memory | 210940 kb |
Host | smart-6969533d-e387-458d-9dac-19bd173531fb |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743275822 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15 .sram_ctrl_mem_partial_access.743275822 |
Directory | /workspace/15.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_mem_walk.136898742 |
Short name | T369 |
Test name | |
Test status | |
Simulation time | 8050516570 ps |
CPU time | 169.12 seconds |
Started | Jul 11 06:03:46 PM PDT 24 |
Finished | Jul 11 06:06:46 PM PDT 24 |
Peak memory | 202840 kb |
Host | smart-cbef28ba-0189-4c8c-bcbe-5bd84835ecd7 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136898742 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl _mem_walk.136898742 |
Directory | /workspace/15.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_multiple_keys.4146304372 |
Short name | T257 |
Test name | |
Test status | |
Simulation time | 12063503346 ps |
CPU time | 1083.22 seconds |
Started | Jul 11 06:03:44 PM PDT 24 |
Finished | Jul 11 06:21:58 PM PDT 24 |
Peak memory | 378744 kb |
Host | smart-47160f21-806e-4f79-985c-34548a6f6fda |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146304372 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multi ple_keys.4146304372 |
Directory | /workspace/15.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_partial_access.4195571436 |
Short name | T247 |
Test name | |
Test status | |
Simulation time | 1276597930 ps |
CPU time | 15.81 seconds |
Started | Jul 11 06:03:50 PM PDT 24 |
Finished | Jul 11 06:04:16 PM PDT 24 |
Peak memory | 202716 kb |
Host | smart-15b883d7-a809-4036-abd1-cf49549b68e2 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195571436 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15. sram_ctrl_partial_access.4195571436 |
Directory | /workspace/15.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.2121636496 |
Short name | T278 |
Test name | |
Test status | |
Simulation time | 6834162168 ps |
CPU time | 374.63 seconds |
Started | Jul 11 06:03:46 PM PDT 24 |
Finished | Jul 11 06:10:11 PM PDT 24 |
Peak memory | 202816 kb |
Host | smart-73994f57-36a4-4da8-ba10-176725da022c |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121636496 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 15.sram_ctrl_partial_access_b2b.2121636496 |
Directory | /workspace/15.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_regwen.2423904681 |
Short name | T82 |
Test name | |
Test status | |
Simulation time | 6408348388 ps |
CPU time | 133.83 seconds |
Started | Jul 11 06:03:42 PM PDT 24 |
Finished | Jul 11 06:06:06 PM PDT 24 |
Peak memory | 281616 kb |
Host | smart-09e7c59f-f3e5-4264-a8ad-717fd1b38ef7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423904681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.2423904681 |
Directory | /workspace/15.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_smoke.1704094088 |
Short name | T569 |
Test name | |
Test status | |
Simulation time | 1675059124 ps |
CPU time | 75.51 seconds |
Started | Jul 11 06:03:36 PM PDT 24 |
Finished | Jul 11 06:05:01 PM PDT 24 |
Peak memory | 331532 kb |
Host | smart-3f06cec7-b08e-4351-9cbf-ddcddb0b723c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704094088 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.1704094088 |
Directory | /workspace/15.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_stress_all.1372580494 |
Short name | T588 |
Test name | |
Test status | |
Simulation time | 214498576454 ps |
CPU time | 4014.93 seconds |
Started | Jul 11 06:03:46 PM PDT 24 |
Finished | Jul 11 07:10:52 PM PDT 24 |
Peak memory | 379796 kb |
Host | smart-f80aaa07-65ee-4028-9474-452f31e3513f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372580494 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 15.sram_ctrl_stress_all.1372580494 |
Directory | /workspace/15.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.409928749 |
Short name | T135 |
Test name | |
Test status | |
Simulation time | 1725188466 ps |
CPU time | 22.12 seconds |
Started | Jul 11 06:03:43 PM PDT 24 |
Finished | Jul 11 06:04:15 PM PDT 24 |
Peak memory | 218584 kb |
Host | smart-9d65c455-a846-4347-8858-1448f0e31332 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=409928749 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all_with_rand_reset.409928749 |
Directory | /workspace/15.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_stress_pipeline.4173991598 |
Short name | T256 |
Test name | |
Test status | |
Simulation time | 15420585150 ps |
CPU time | 258.54 seconds |
Started | Jul 11 06:03:41 PM PDT 24 |
Finished | Jul 11 06:08:09 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-45268b7e-d65e-4d81-b026-40d6df93e6c7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173991598 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 5.sram_ctrl_stress_pipeline.4173991598 |
Directory | /workspace/15.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.2805751548 |
Short name | T230 |
Test name | |
Test status | |
Simulation time | 2910090185 ps |
CPU time | 41.73 seconds |
Started | Jul 11 06:03:41 PM PDT 24 |
Finished | Jul 11 06:04:33 PM PDT 24 |
Peak memory | 291028 kb |
Host | smart-20177e1d-6d4b-4ec0-8460-cea4cead8796 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805751548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 15.sram_ctrl_throughput_w_partial_write.2805751548 |
Directory | /workspace/15.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_access_during_key_req.1259464702 |
Short name | T343 |
Test name | |
Test status | |
Simulation time | 28156534338 ps |
CPU time | 579.4 seconds |
Started | Jul 11 06:03:40 PM PDT 24 |
Finished | Jul 11 06:13:30 PM PDT 24 |
Peak memory | 364316 kb |
Host | smart-4270eea5-bda2-46f1-88b9-46091fa4ec83 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259464702 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 16.sram_ctrl_access_during_key_req.1259464702 |
Directory | /workspace/16.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_alert_test.835355832 |
Short name | T618 |
Test name | |
Test status | |
Simulation time | 13132676 ps |
CPU time | 0.65 seconds |
Started | Jul 11 06:03:44 PM PDT 24 |
Finished | Jul 11 06:03:55 PM PDT 24 |
Peak memory | 202384 kb |
Host | smart-2f601319-c63d-4735-b38f-aa7528ce53f2 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835355832 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_alert_test.835355832 |
Directory | /workspace/16.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_bijection.1138620623 |
Short name | T485 |
Test name | |
Test status | |
Simulation time | 12694987021 ps |
CPU time | 868.75 seconds |
Started | Jul 11 06:03:42 PM PDT 24 |
Finished | Jul 11 06:18:21 PM PDT 24 |
Peak memory | 203452 kb |
Host | smart-6ab2863d-d072-4802-a2ed-3bf788ba6ad9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138620623 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection .1138620623 |
Directory | /workspace/16.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_executable.155218513 |
Short name | T39 |
Test name | |
Test status | |
Simulation time | 85936353995 ps |
CPU time | 742.37 seconds |
Started | Jul 11 06:03:42 PM PDT 24 |
Finished | Jul 11 06:16:14 PM PDT 24 |
Peak memory | 343136 kb |
Host | smart-4cfaea51-f9f8-44f0-87be-a3c34f641c19 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155218513 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_executabl e.155218513 |
Directory | /workspace/16.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_lc_escalation.4137756622 |
Short name | T354 |
Test name | |
Test status | |
Simulation time | 17278771666 ps |
CPU time | 34.4 seconds |
Started | Jul 11 06:03:42 PM PDT 24 |
Finished | Jul 11 06:04:26 PM PDT 24 |
Peak memory | 202904 kb |
Host | smart-cd7a0593-e84d-43fc-a494-f74cfdbb7689 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137756622 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_es calation.4137756622 |
Directory | /workspace/16.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_max_throughput.1787899222 |
Short name | T413 |
Test name | |
Test status | |
Simulation time | 688647642 ps |
CPU time | 6.16 seconds |
Started | Jul 11 06:03:41 PM PDT 24 |
Finished | Jul 11 06:03:57 PM PDT 24 |
Peak memory | 210964 kb |
Host | smart-d7dfa1df-b265-4978-8a3a-03242d3583e3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787899222 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 16.sram_ctrl_max_throughput.1787899222 |
Directory | /workspace/16.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_mem_partial_access.2088680706 |
Short name | T3 |
Test name | |
Test status | |
Simulation time | 2431517484 ps |
CPU time | 139.02 seconds |
Started | Jul 11 06:03:42 PM PDT 24 |
Finished | Jul 11 06:06:11 PM PDT 24 |
Peak memory | 211060 kb |
Host | smart-4121f680-18f4-4d95-9330-8fe66c261906 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088680706 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 6.sram_ctrl_mem_partial_access.2088680706 |
Directory | /workspace/16.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_mem_walk.1679834837 |
Short name | T772 |
Test name | |
Test status | |
Simulation time | 24687275723 ps |
CPU time | 124.26 seconds |
Started | Jul 11 06:03:43 PM PDT 24 |
Finished | Jul 11 06:05:58 PM PDT 24 |
Peak memory | 211032 kb |
Host | smart-5a249c3a-f76a-4f40-b76e-b6d60409cd12 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679834837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctr l_mem_walk.1679834837 |
Directory | /workspace/16.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_multiple_keys.1530494935 |
Short name | T837 |
Test name | |
Test status | |
Simulation time | 97383386319 ps |
CPU time | 1374.71 seconds |
Started | Jul 11 06:03:39 PM PDT 24 |
Finished | Jul 11 06:26:44 PM PDT 24 |
Peak memory | 378712 kb |
Host | smart-c4a2739b-2f8b-4cf5-9863-5e42f6aa0dc5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530494935 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multi ple_keys.1530494935 |
Directory | /workspace/16.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_partial_access.741620378 |
Short name | T594 |
Test name | |
Test status | |
Simulation time | 981851800 ps |
CPU time | 11.11 seconds |
Started | Jul 11 06:03:42 PM PDT 24 |
Finished | Jul 11 06:04:03 PM PDT 24 |
Peak memory | 202524 kb |
Host | smart-2b6570e7-3552-4ab9-a30d-bd118d2cd9b5 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741620378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.s ram_ctrl_partial_access.741620378 |
Directory | /workspace/16.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.902815582 |
Short name | T858 |
Test name | |
Test status | |
Simulation time | 66029137527 ps |
CPU time | 458.82 seconds |
Started | Jul 11 06:03:40 PM PDT 24 |
Finished | Jul 11 06:11:29 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-d90de2cc-f0b6-41de-ae99-3478f8548004 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902815582 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 16.sram_ctrl_partial_access_b2b.902815582 |
Directory | /workspace/16.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_ram_cfg.3794043428 |
Short name | T852 |
Test name | |
Test status | |
Simulation time | 345690875 ps |
CPU time | 3.38 seconds |
Started | Jul 11 06:03:46 PM PDT 24 |
Finished | Jul 11 06:04:00 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-014ad045-3726-4aa6-94a0-aba5a6d7ac68 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794043428 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.3794043428 |
Directory | /workspace/16.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_regwen.2178906095 |
Short name | T595 |
Test name | |
Test status | |
Simulation time | 29689219935 ps |
CPU time | 607.53 seconds |
Started | Jul 11 06:03:43 PM PDT 24 |
Finished | Jul 11 06:14:01 PM PDT 24 |
Peak memory | 360328 kb |
Host | smart-c414fa70-9cd1-450e-bafb-b3424b9a960e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178906095 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.2178906095 |
Directory | /workspace/16.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_smoke.3813871208 |
Short name | T893 |
Test name | |
Test status | |
Simulation time | 4848385369 ps |
CPU time | 84.86 seconds |
Started | Jul 11 06:03:46 PM PDT 24 |
Finished | Jul 11 06:05:22 PM PDT 24 |
Peak memory | 343912 kb |
Host | smart-958b8ad7-609d-4074-8a95-7d1d4a420131 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813871208 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.3813871208 |
Directory | /workspace/16.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_stress_all.3730429127 |
Short name | T379 |
Test name | |
Test status | |
Simulation time | 82477155338 ps |
CPU time | 5157.82 seconds |
Started | Jul 11 06:03:43 PM PDT 24 |
Finished | Jul 11 07:29:51 PM PDT 24 |
Peak memory | 357004 kb |
Host | smart-a6d5eeb8-0e23-4135-956c-e4561e3e0f3a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730429127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 16.sram_ctrl_stress_all.3730429127 |
Directory | /workspace/16.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.1245670178 |
Short name | T843 |
Test name | |
Test status | |
Simulation time | 27440827106 ps |
CPU time | 126.05 seconds |
Started | Jul 11 06:03:45 PM PDT 24 |
Finished | Jul 11 06:06:01 PM PDT 24 |
Peak memory | 331776 kb |
Host | smart-95a7e3d1-6896-48d6-b6a4-3059f72bd506 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1245670178 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all_with_rand_reset.1245670178 |
Directory | /workspace/16.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_stress_pipeline.2043284297 |
Short name | T553 |
Test name | |
Test status | |
Simulation time | 3205099568 ps |
CPU time | 164.62 seconds |
Started | Jul 11 06:03:43 PM PDT 24 |
Finished | Jul 11 06:06:38 PM PDT 24 |
Peak memory | 202836 kb |
Host | smart-2412b98d-623f-40c7-a20c-219b72eb26be |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043284297 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 6.sram_ctrl_stress_pipeline.2043284297 |
Directory | /workspace/16.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.2798606309 |
Short name | T821 |
Test name | |
Test status | |
Simulation time | 767104106 ps |
CPU time | 97.09 seconds |
Started | Jul 11 06:03:43 PM PDT 24 |
Finished | Jul 11 06:05:30 PM PDT 24 |
Peak memory | 344812 kb |
Host | smart-0f81bf4a-44dc-4cdc-8df5-a675ddf10c17 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798606309 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 16.sram_ctrl_throughput_w_partial_write.2798606309 |
Directory | /workspace/16.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_access_during_key_req.2076884833 |
Short name | T739 |
Test name | |
Test status | |
Simulation time | 2498757457 ps |
CPU time | 456.13 seconds |
Started | Jul 11 06:03:46 PM PDT 24 |
Finished | Jul 11 06:11:33 PM PDT 24 |
Peak memory | 373604 kb |
Host | smart-f74c3594-4599-4e28-8fbd-3708b299afc2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076884833 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 17.sram_ctrl_access_during_key_req.2076884833 |
Directory | /workspace/17.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_alert_test.1806332643 |
Short name | T731 |
Test name | |
Test status | |
Simulation time | 15799924 ps |
CPU time | 0.69 seconds |
Started | Jul 11 06:03:51 PM PDT 24 |
Finished | Jul 11 06:04:01 PM PDT 24 |
Peak memory | 202368 kb |
Host | smart-5c650c6e-0ca3-4a16-ab83-24d9cbb7453b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806332643 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_alert_test.1806332643 |
Directory | /workspace/17.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_bijection.3599559084 |
Short name | T650 |
Test name | |
Test status | |
Simulation time | 147515716247 ps |
CPU time | 1979.01 seconds |
Started | Jul 11 06:03:50 PM PDT 24 |
Finished | Jul 11 06:36:59 PM PDT 24 |
Peak memory | 203520 kb |
Host | smart-ef9a7e91-d0aa-4967-b25d-b6e4ec1c175c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599559084 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection .3599559084 |
Directory | /workspace/17.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_executable.4048660366 |
Short name | T357 |
Test name | |
Test status | |
Simulation time | 18188070188 ps |
CPU time | 916.34 seconds |
Started | Jul 11 06:03:52 PM PDT 24 |
Finished | Jul 11 06:19:18 PM PDT 24 |
Peak memory | 379796 kb |
Host | smart-aebf0bc6-4ba6-45bd-a057-9e647d574d9c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048660366 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executab le.4048660366 |
Directory | /workspace/17.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_lc_escalation.1880782319 |
Short name | T500 |
Test name | |
Test status | |
Simulation time | 23191154159 ps |
CPU time | 75.13 seconds |
Started | Jul 11 06:03:46 PM PDT 24 |
Finished | Jul 11 06:05:12 PM PDT 24 |
Peak memory | 202844 kb |
Host | smart-722f2911-b59d-4a70-81b5-3288f38e7098 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880782319 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_es calation.1880782319 |
Directory | /workspace/17.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_max_throughput.246213172 |
Short name | T560 |
Test name | |
Test status | |
Simulation time | 3369466904 ps |
CPU time | 7.54 seconds |
Started | Jul 11 06:03:44 PM PDT 24 |
Finished | Jul 11 06:04:01 PM PDT 24 |
Peak memory | 218928 kb |
Host | smart-df9c0311-afb7-42f0-9972-ddcffc808425 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246213172 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 17.sram_ctrl_max_throughput.246213172 |
Directory | /workspace/17.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_mem_partial_access.1610269696 |
Short name | T412 |
Test name | |
Test status | |
Simulation time | 1612508365 ps |
CPU time | 128.23 seconds |
Started | Jul 11 06:08:37 PM PDT 24 |
Finished | Jul 11 06:10:47 PM PDT 24 |
Peak memory | 219088 kb |
Host | smart-e887e6d6-51e3-46f3-956c-d960b3d1f7d4 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610269696 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 7.sram_ctrl_mem_partial_access.1610269696 |
Directory | /workspace/17.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_mem_walk.3458020576 |
Short name | T433 |
Test name | |
Test status | |
Simulation time | 3511797480 ps |
CPU time | 155.16 seconds |
Started | Jul 11 06:03:52 PM PDT 24 |
Finished | Jul 11 06:06:36 PM PDT 24 |
Peak memory | 211016 kb |
Host | smart-865a4764-a193-45eb-8b07-1bf7435e075c |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458020576 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctr l_mem_walk.3458020576 |
Directory | /workspace/17.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_multiple_keys.3280679438 |
Short name | T925 |
Test name | |
Test status | |
Simulation time | 12382605057 ps |
CPU time | 429.68 seconds |
Started | Jul 11 06:03:51 PM PDT 24 |
Finished | Jul 11 06:11:10 PM PDT 24 |
Peak memory | 372760 kb |
Host | smart-ac741d3b-3034-4008-ba77-218ada3aed0a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280679438 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multi ple_keys.3280679438 |
Directory | /workspace/17.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_partial_access.84083830 |
Short name | T638 |
Test name | |
Test status | |
Simulation time | 5765567066 ps |
CPU time | 22 seconds |
Started | Jul 11 06:03:44 PM PDT 24 |
Finished | Jul 11 06:04:16 PM PDT 24 |
Peak memory | 202760 kb |
Host | smart-7c444eea-a00f-402c-95d3-ddd96fbaac07 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84083830 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sr am_ctrl_partial_access.84083830 |
Directory | /workspace/17.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.1163719428 |
Short name | T678 |
Test name | |
Test status | |
Simulation time | 94613434119 ps |
CPU time | 592.91 seconds |
Started | Jul 11 06:03:51 PM PDT 24 |
Finished | Jul 11 06:13:54 PM PDT 24 |
Peak memory | 202872 kb |
Host | smart-6fea4328-6bff-4d32-9dc0-7d430604f11b |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163719428 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 17.sram_ctrl_partial_access_b2b.1163719428 |
Directory | /workspace/17.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_ram_cfg.1010950952 |
Short name | T297 |
Test name | |
Test status | |
Simulation time | 1679568745 ps |
CPU time | 3.84 seconds |
Started | Jul 11 06:03:51 PM PDT 24 |
Finished | Jul 11 06:04:04 PM PDT 24 |
Peak memory | 202880 kb |
Host | smart-205d98a8-8f4f-4e79-9261-4844a7b794b3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010950952 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.1010950952 |
Directory | /workspace/17.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_regwen.2824077234 |
Short name | T352 |
Test name | |
Test status | |
Simulation time | 43102673190 ps |
CPU time | 618.5 seconds |
Started | Jul 11 06:03:49 PM PDT 24 |
Finished | Jul 11 06:14:17 PM PDT 24 |
Peak memory | 374624 kb |
Host | smart-c901c9e5-803c-4bde-bc9e-109b3d5b8a68 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824077234 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.2824077234 |
Directory | /workspace/17.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_smoke.2078578452 |
Short name | T825 |
Test name | |
Test status | |
Simulation time | 1476196882 ps |
CPU time | 14.53 seconds |
Started | Jul 11 06:03:44 PM PDT 24 |
Finished | Jul 11 06:04:08 PM PDT 24 |
Peak memory | 242420 kb |
Host | smart-2744b13e-01df-46a8-bb77-5fb5cd703f4e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078578452 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.2078578452 |
Directory | /workspace/17.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.1152377570 |
Short name | T575 |
Test name | |
Test status | |
Simulation time | 1930622682 ps |
CPU time | 106.29 seconds |
Started | Jul 11 06:03:45 PM PDT 24 |
Finished | Jul 11 06:05:41 PM PDT 24 |
Peak memory | 324132 kb |
Host | smart-530c27d0-daaf-43a7-ab22-e3feaae511e4 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1152377570 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all_with_rand_reset.1152377570 |
Directory | /workspace/17.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_stress_pipeline.4029625112 |
Short name | T603 |
Test name | |
Test status | |
Simulation time | 10317297388 ps |
CPU time | 328.6 seconds |
Started | Jul 11 06:03:53 PM PDT 24 |
Finished | Jul 11 06:09:31 PM PDT 24 |
Peak memory | 202836 kb |
Host | smart-4f2ffddd-8474-49da-a6d2-39be53a105e6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029625112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 7.sram_ctrl_stress_pipeline.4029625112 |
Directory | /workspace/17.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.2796232246 |
Short name | T417 |
Test name | |
Test status | |
Simulation time | 3261813465 ps |
CPU time | 107.85 seconds |
Started | Jul 11 06:03:47 PM PDT 24 |
Finished | Jul 11 06:05:44 PM PDT 24 |
Peak memory | 371472 kb |
Host | smart-e30ea2ee-1955-461c-8a0f-bdbb36777cf6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796232246 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 17.sram_ctrl_throughput_w_partial_write.2796232246 |
Directory | /workspace/17.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_access_during_key_req.4055048367 |
Short name | T495 |
Test name | |
Test status | |
Simulation time | 59435812328 ps |
CPU time | 1251.5 seconds |
Started | Jul 11 06:03:53 PM PDT 24 |
Finished | Jul 11 06:24:53 PM PDT 24 |
Peak memory | 379804 kb |
Host | smart-c413693b-43c0-442c-96f6-820f9adb8a6c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055048367 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 18.sram_ctrl_access_during_key_req.4055048367 |
Directory | /workspace/18.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_alert_test.741378949 |
Short name | T395 |
Test name | |
Test status | |
Simulation time | 47461270 ps |
CPU time | 0.67 seconds |
Started | Jul 11 06:03:56 PM PDT 24 |
Finished | Jul 11 06:04:05 PM PDT 24 |
Peak memory | 202372 kb |
Host | smart-3c40509f-8f81-4503-bb9a-044a243f7044 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741378949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_alert_test.741378949 |
Directory | /workspace/18.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_bijection.2511888992 |
Short name | T612 |
Test name | |
Test status | |
Simulation time | 230678311075 ps |
CPU time | 987.15 seconds |
Started | Jul 11 06:03:46 PM PDT 24 |
Finished | Jul 11 06:20:24 PM PDT 24 |
Peak memory | 202992 kb |
Host | smart-9f4cdedb-cbf5-4fef-9370-3c1464b5cea1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511888992 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection .2511888992 |
Directory | /workspace/18.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_executable.3522880844 |
Short name | T674 |
Test name | |
Test status | |
Simulation time | 154034197305 ps |
CPU time | 218.68 seconds |
Started | Jul 11 06:03:57 PM PDT 24 |
Finished | Jul 11 06:07:44 PM PDT 24 |
Peak memory | 304164 kb |
Host | smart-2ca6b0d9-c037-48a2-a35d-69e94303acae |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522880844 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executab le.3522880844 |
Directory | /workspace/18.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_lc_escalation.862603203 |
Short name | T878 |
Test name | |
Test status | |
Simulation time | 94594253828 ps |
CPU time | 63.47 seconds |
Started | Jul 11 06:03:54 PM PDT 24 |
Finished | Jul 11 06:05:06 PM PDT 24 |
Peak memory | 211104 kb |
Host | smart-0d28bd6b-e5f9-4b3e-b2aa-7f1ccfd9f081 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862603203 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_esc alation.862603203 |
Directory | /workspace/18.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_max_throughput.4097956707 |
Short name | T76 |
Test name | |
Test status | |
Simulation time | 2980571152 ps |
CPU time | 56.65 seconds |
Started | Jul 11 06:03:44 PM PDT 24 |
Finished | Jul 11 06:04:50 PM PDT 24 |
Peak memory | 337744 kb |
Host | smart-6662bd8a-889c-4873-8252-727a3c9e7fc6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097956707 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 18.sram_ctrl_max_throughput.4097956707 |
Directory | /workspace/18.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_mem_partial_access.518899552 |
Short name | T53 |
Test name | |
Test status | |
Simulation time | 9880335236 ps |
CPU time | 84.44 seconds |
Started | Jul 11 06:03:57 PM PDT 24 |
Finished | Jul 11 06:05:29 PM PDT 24 |
Peak memory | 211256 kb |
Host | smart-f1710996-bdf0-46c5-bba1-0001c362f844 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518899552 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18 .sram_ctrl_mem_partial_access.518899552 |
Directory | /workspace/18.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_mem_walk.4273947947 |
Short name | T141 |
Test name | |
Test status | |
Simulation time | 43081896807 ps |
CPU time | 351.96 seconds |
Started | Jul 11 06:03:52 PM PDT 24 |
Finished | Jul 11 06:09:53 PM PDT 24 |
Peak memory | 211020 kb |
Host | smart-cc42b19e-85d4-4a5f-a99f-70275e36867b |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273947947 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctr l_mem_walk.4273947947 |
Directory | /workspace/18.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_multiple_keys.2308530691 |
Short name | T806 |
Test name | |
Test status | |
Simulation time | 6930833766 ps |
CPU time | 811.78 seconds |
Started | Jul 11 06:03:42 PM PDT 24 |
Finished | Jul 11 06:17:24 PM PDT 24 |
Peak memory | 377716 kb |
Host | smart-918207c4-6474-4e89-bef0-c0028fa65d06 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308530691 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multi ple_keys.2308530691 |
Directory | /workspace/18.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_partial_access.543919553 |
Short name | T269 |
Test name | |
Test status | |
Simulation time | 1637520287 ps |
CPU time | 73.21 seconds |
Started | Jul 11 06:03:52 PM PDT 24 |
Finished | Jul 11 06:05:14 PM PDT 24 |
Peak memory | 325796 kb |
Host | smart-13fd0261-e16b-4c0f-a3b0-844f9dd1ea40 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543919553 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.s ram_ctrl_partial_access.543919553 |
Directory | /workspace/18.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.2618219652 |
Short name | T219 |
Test name | |
Test status | |
Simulation time | 8083567850 ps |
CPU time | 172.21 seconds |
Started | Jul 11 06:03:45 PM PDT 24 |
Finished | Jul 11 06:06:47 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-2f48dfbd-456a-4b94-9b4e-6b6e0dcd5b30 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618219652 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 18.sram_ctrl_partial_access_b2b.2618219652 |
Directory | /workspace/18.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_ram_cfg.4131182099 |
Short name | T838 |
Test name | |
Test status | |
Simulation time | 807871742 ps |
CPU time | 3.76 seconds |
Started | Jul 11 06:03:56 PM PDT 24 |
Finished | Jul 11 06:04:08 PM PDT 24 |
Peak memory | 202880 kb |
Host | smart-87c696a1-5f13-46b9-86b9-a50be60c64f9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131182099 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.4131182099 |
Directory | /workspace/18.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_regwen.1497705123 |
Short name | T325 |
Test name | |
Test status | |
Simulation time | 80377520097 ps |
CPU time | 874.12 seconds |
Started | Jul 11 06:03:53 PM PDT 24 |
Finished | Jul 11 06:18:36 PM PDT 24 |
Peak memory | 355208 kb |
Host | smart-c6a700d7-cd5c-4a9a-996d-e64cfb8b8bcb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497705123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.1497705123 |
Directory | /workspace/18.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_smoke.1218258203 |
Short name | T216 |
Test name | |
Test status | |
Simulation time | 3727238636 ps |
CPU time | 17.63 seconds |
Started | Jul 11 06:03:45 PM PDT 24 |
Finished | Jul 11 06:04:13 PM PDT 24 |
Peak memory | 202848 kb |
Host | smart-00c15be6-e1f7-49c9-8c14-9801eb17f30c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218258203 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.1218258203 |
Directory | /workspace/18.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_stress_all.550970212 |
Short name | T833 |
Test name | |
Test status | |
Simulation time | 352520866305 ps |
CPU time | 7056.32 seconds |
Started | Jul 11 06:03:52 PM PDT 24 |
Finished | Jul 11 08:01:38 PM PDT 24 |
Peak memory | 381860 kb |
Host | smart-335b6053-018f-494e-b1c2-10000c414ec4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550970212 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 18.sram_ctrl_stress_all.550970212 |
Directory | /workspace/18.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.2114004671 |
Short name | T131 |
Test name | |
Test status | |
Simulation time | 4745240609 ps |
CPU time | 37.73 seconds |
Started | Jul 11 06:03:51 PM PDT 24 |
Finished | Jul 11 06:04:39 PM PDT 24 |
Peak memory | 213016 kb |
Host | smart-6fcb48d8-8cce-42cd-bf3d-edcbbc4bdc93 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2114004671 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all_with_rand_reset.2114004671 |
Directory | /workspace/18.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_stress_pipeline.1579806734 |
Short name | T565 |
Test name | |
Test status | |
Simulation time | 20612496665 ps |
CPU time | 252.56 seconds |
Started | Jul 11 06:03:47 PM PDT 24 |
Finished | Jul 11 06:08:09 PM PDT 24 |
Peak memory | 202872 kb |
Host | smart-706cfb64-8227-4b45-892a-b4aae2aed56c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579806734 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 8.sram_ctrl_stress_pipeline.1579806734 |
Directory | /workspace/18.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.3327311167 |
Short name | T254 |
Test name | |
Test status | |
Simulation time | 3563114606 ps |
CPU time | 129.35 seconds |
Started | Jul 11 06:03:45 PM PDT 24 |
Finished | Jul 11 06:06:05 PM PDT 24 |
Peak memory | 371516 kb |
Host | smart-a0b9a4c5-34b2-4ccc-97fa-a2f9b47787c2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327311167 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 18.sram_ctrl_throughput_w_partial_write.3327311167 |
Directory | /workspace/18.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_access_during_key_req.919569836 |
Short name | T123 |
Test name | |
Test status | |
Simulation time | 14800309510 ps |
CPU time | 394.9 seconds |
Started | Jul 11 06:03:56 PM PDT 24 |
Finished | Jul 11 06:10:39 PM PDT 24 |
Peak memory | 370520 kb |
Host | smart-82e7f6d1-2248-4acf-ae4f-3d33640048c9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919569836 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 19.sram_ctrl_access_during_key_req.919569836 |
Directory | /workspace/19.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_alert_test.3532747447 |
Short name | T15 |
Test name | |
Test status | |
Simulation time | 15671377 ps |
CPU time | 0.69 seconds |
Started | Jul 11 06:03:53 PM PDT 24 |
Finished | Jul 11 06:04:02 PM PDT 24 |
Peak memory | 202424 kb |
Host | smart-8d1e671f-0f08-4af9-a274-ac9296ee8f6c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532747447 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_alert_test.3532747447 |
Directory | /workspace/19.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_bijection.1778861872 |
Short name | T574 |
Test name | |
Test status | |
Simulation time | 19706229922 ps |
CPU time | 1385.98 seconds |
Started | Jul 11 06:03:58 PM PDT 24 |
Finished | Jul 11 06:27:12 PM PDT 24 |
Peak memory | 203772 kb |
Host | smart-535021bf-e2d3-4466-b454-389915fc8e31 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778861872 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection .1778861872 |
Directory | /workspace/19.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_executable.947802945 |
Short name | T338 |
Test name | |
Test status | |
Simulation time | 47130791681 ps |
CPU time | 1219.4 seconds |
Started | Jul 11 06:03:55 PM PDT 24 |
Finished | Jul 11 06:24:22 PM PDT 24 |
Peak memory | 373676 kb |
Host | smart-9d5246d9-65c6-42c9-ab34-5d373d82d958 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947802945 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executabl e.947802945 |
Directory | /workspace/19.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_lc_escalation.82784295 |
Short name | T503 |
Test name | |
Test status | |
Simulation time | 45541500369 ps |
CPU time | 78.46 seconds |
Started | Jul 11 06:03:53 PM PDT 24 |
Finished | Jul 11 06:05:20 PM PDT 24 |
Peak memory | 211104 kb |
Host | smart-dc41825c-3a21-4215-a7ee-7091e7566d7d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82784295 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_esc alation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_esca lation.82784295 |
Directory | /workspace/19.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_max_throughput.417319282 |
Short name | T333 |
Test name | |
Test status | |
Simulation time | 3366567296 ps |
CPU time | 7.72 seconds |
Started | Jul 11 06:04:08 PM PDT 24 |
Finished | Jul 11 06:04:25 PM PDT 24 |
Peak memory | 219172 kb |
Host | smart-0b828dc0-1fcd-45c8-b9a3-2051ade5255e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417319282 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 19.sram_ctrl_max_throughput.417319282 |
Directory | /workspace/19.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_mem_partial_access.4144871036 |
Short name | T408 |
Test name | |
Test status | |
Simulation time | 9858432159 ps |
CPU time | 78.77 seconds |
Started | Jul 11 06:03:53 PM PDT 24 |
Finished | Jul 11 06:05:20 PM PDT 24 |
Peak memory | 211060 kb |
Host | smart-40e98c34-6840-4139-8d63-0908fb60012b |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144871036 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 9.sram_ctrl_mem_partial_access.4144871036 |
Directory | /workspace/19.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_mem_walk.2089376966 |
Short name | T169 |
Test name | |
Test status | |
Simulation time | 2747686329 ps |
CPU time | 148.51 seconds |
Started | Jul 11 06:04:02 PM PDT 24 |
Finished | Jul 11 06:06:40 PM PDT 24 |
Peak memory | 211020 kb |
Host | smart-1cdf7c50-8480-4cad-8b0c-4b007b1086f3 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089376966 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctr l_mem_walk.2089376966 |
Directory | /workspace/19.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_multiple_keys.2269675777 |
Short name | T703 |
Test name | |
Test status | |
Simulation time | 3386280241 ps |
CPU time | 176.44 seconds |
Started | Jul 11 06:03:57 PM PDT 24 |
Finished | Jul 11 06:07:02 PM PDT 24 |
Peak memory | 318360 kb |
Host | smart-29a5a149-1f6c-47a3-8f2c-75ce9c186a21 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269675777 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multi ple_keys.2269675777 |
Directory | /workspace/19.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_partial_access.3110339327 |
Short name | T748 |
Test name | |
Test status | |
Simulation time | 6802461205 ps |
CPU time | 41.26 seconds |
Started | Jul 11 06:03:52 PM PDT 24 |
Finished | Jul 11 06:04:43 PM PDT 24 |
Peak memory | 290896 kb |
Host | smart-bfabce89-49cf-47fc-be88-b2f13b8ada54 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110339327 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19. sram_ctrl_partial_access.3110339327 |
Directory | /workspace/19.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.822800807 |
Short name | T620 |
Test name | |
Test status | |
Simulation time | 45730331010 ps |
CPU time | 563.8 seconds |
Started | Jul 11 06:03:57 PM PDT 24 |
Finished | Jul 11 06:13:29 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-b404d891-927f-48b6-82db-232c9f399cb5 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822800807 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 19.sram_ctrl_partial_access_b2b.822800807 |
Directory | /workspace/19.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_ram_cfg.1954376154 |
Short name | T195 |
Test name | |
Test status | |
Simulation time | 354599189 ps |
CPU time | 3.25 seconds |
Started | Jul 11 06:03:56 PM PDT 24 |
Finished | Jul 11 06:04:07 PM PDT 24 |
Peak memory | 202308 kb |
Host | smart-0806ade2-53f9-4678-961e-8d77b78dc35e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954376154 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.1954376154 |
Directory | /workspace/19.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_regwen.2879226881 |
Short name | T613 |
Test name | |
Test status | |
Simulation time | 18044452845 ps |
CPU time | 509.67 seconds |
Started | Jul 11 06:03:56 PM PDT 24 |
Finished | Jul 11 06:12:34 PM PDT 24 |
Peak memory | 376080 kb |
Host | smart-15010d43-805b-4927-9c6e-82b12123e5fe |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879226881 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.2879226881 |
Directory | /workspace/19.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_smoke.388033990 |
Short name | T915 |
Test name | |
Test status | |
Simulation time | 1407162610 ps |
CPU time | 21.71 seconds |
Started | Jul 11 06:03:54 PM PDT 24 |
Finished | Jul 11 06:04:25 PM PDT 24 |
Peak memory | 202736 kb |
Host | smart-9a40fdf9-9fb0-4df8-99e5-6cf891b31648 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388033990 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.388033990 |
Directory | /workspace/19.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_stress_all.3307519030 |
Short name | T930 |
Test name | |
Test status | |
Simulation time | 360022701976 ps |
CPU time | 10172.7 seconds |
Started | Jul 11 06:03:59 PM PDT 24 |
Finished | Jul 11 08:53:42 PM PDT 24 |
Peak memory | 380872 kb |
Host | smart-ce76fd6f-fffe-44d0-acb6-f0e40a0608ef |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307519030 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 19.sram_ctrl_stress_all.3307519030 |
Directory | /workspace/19.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.536962775 |
Short name | T830 |
Test name | |
Test status | |
Simulation time | 526246924 ps |
CPU time | 12.21 seconds |
Started | Jul 11 06:03:58 PM PDT 24 |
Finished | Jul 11 06:04:18 PM PDT 24 |
Peak memory | 211148 kb |
Host | smart-4e292806-ea4d-44e0-80ce-808403a86ccf |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=536962775 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all_with_rand_reset.536962775 |
Directory | /workspace/19.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_stress_pipeline.82228700 |
Short name | T404 |
Test name | |
Test status | |
Simulation time | 3374552547 ps |
CPU time | 210.66 seconds |
Started | Jul 11 06:03:55 PM PDT 24 |
Finished | Jul 11 06:07:34 PM PDT 24 |
Peak memory | 202804 kb |
Host | smart-149b92b0-d71a-4796-a4dc-59e7f49a70a7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82228700 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19. sram_ctrl_stress_pipeline.82228700 |
Directory | /workspace/19.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.3583879140 |
Short name | T439 |
Test name | |
Test status | |
Simulation time | 5275301814 ps |
CPU time | 52.39 seconds |
Started | Jul 11 06:03:56 PM PDT 24 |
Finished | Jul 11 06:04:57 PM PDT 24 |
Peak memory | 304108 kb |
Host | smart-40a351e3-6b26-40c8-8d19-0fdb00f39bb7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583879140 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 19.sram_ctrl_throughput_w_partial_write.3583879140 |
Directory | /workspace/19.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_access_during_key_req.421458932 |
Short name | T856 |
Test name | |
Test status | |
Simulation time | 2888876930 ps |
CPU time | 403.06 seconds |
Started | Jul 11 06:02:58 PM PDT 24 |
Finished | Jul 11 06:10:00 PM PDT 24 |
Peak memory | 376720 kb |
Host | smart-bb9fb2c1-c1bc-4449-92f2-58a20e80968a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421458932 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 2.sram_ctrl_access_during_key_req.421458932 |
Directory | /workspace/2.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_alert_test.3612917893 |
Short name | T482 |
Test name | |
Test status | |
Simulation time | 45721356 ps |
CPU time | 0.71 seconds |
Started | Jul 11 06:03:03 PM PDT 24 |
Finished | Jul 11 06:03:22 PM PDT 24 |
Peak memory | 202572 kb |
Host | smart-391cab42-d718-4a68-a4d1-970bb3992e39 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612917893 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_alert_test.3612917893 |
Directory | /workspace/2.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_bijection.451633790 |
Short name | T850 |
Test name | |
Test status | |
Simulation time | 33459401906 ps |
CPU time | 2389.15 seconds |
Started | Jul 11 06:02:57 PM PDT 24 |
Finished | Jul 11 06:43:06 PM PDT 24 |
Peak memory | 203524 kb |
Host | smart-2f4c327e-d994-449c-b907-7589355732d5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451633790 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection.451633790 |
Directory | /workspace/2.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_executable.4034338916 |
Short name | T809 |
Test name | |
Test status | |
Simulation time | 23717879011 ps |
CPU time | 355.1 seconds |
Started | Jul 11 06:03:04 PM PDT 24 |
Finished | Jul 11 06:09:17 PM PDT 24 |
Peak memory | 326632 kb |
Host | smart-c19ed61e-8473-46fd-9415-6e22a0d8884a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034338916 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executabl e.4034338916 |
Directory | /workspace/2.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_lc_escalation.3542571800 |
Short name | T527 |
Test name | |
Test status | |
Simulation time | 114990315965 ps |
CPU time | 67.18 seconds |
Started | Jul 11 06:02:57 PM PDT 24 |
Finished | Jul 11 06:04:24 PM PDT 24 |
Peak memory | 202868 kb |
Host | smart-ef6a7a8c-449b-466f-a5db-93d1ea1c69f3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542571800 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_esc alation.3542571800 |
Directory | /workspace/2.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_max_throughput.1880528297 |
Short name | T839 |
Test name | |
Test status | |
Simulation time | 686599364 ps |
CPU time | 7.51 seconds |
Started | Jul 11 06:03:13 PM PDT 24 |
Finished | Jul 11 06:03:36 PM PDT 24 |
Peak memory | 219032 kb |
Host | smart-c9c37ccf-6468-413a-b5ce-8de5e76f74a7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880528297 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.sram_ctrl_max_throughput.1880528297 |
Directory | /workspace/2.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_mem_partial_access.1655686687 |
Short name | T807 |
Test name | |
Test status | |
Simulation time | 83647164409 ps |
CPU time | 177.02 seconds |
Started | Jul 11 06:03:02 PM PDT 24 |
Finished | Jul 11 06:06:18 PM PDT 24 |
Peak memory | 211320 kb |
Host | smart-dfe2a2eb-999a-4a48-a0b9-e2de1297c926 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655686687 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .sram_ctrl_mem_partial_access.1655686687 |
Directory | /workspace/2.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_mem_walk.4111134818 |
Short name | T936 |
Test name | |
Test status | |
Simulation time | 1983045113 ps |
CPU time | 128.54 seconds |
Started | Jul 11 06:02:58 PM PDT 24 |
Finished | Jul 11 06:05:25 PM PDT 24 |
Peak memory | 210860 kb |
Host | smart-523406e8-cf49-4387-8908-522bd8649fec |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111134818 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl _mem_walk.4111134818 |
Directory | /workspace/2.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_multiple_keys.1627707651 |
Short name | T79 |
Test name | |
Test status | |
Simulation time | 104769535998 ps |
CPU time | 840.81 seconds |
Started | Jul 11 06:03:04 PM PDT 24 |
Finished | Jul 11 06:17:23 PM PDT 24 |
Peak memory | 369516 kb |
Host | smart-613088e1-e9aa-4976-ac0b-ffe65249fea3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627707651 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multip le_keys.1627707651 |
Directory | /workspace/2.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_partial_access.2165949509 |
Short name | T511 |
Test name | |
Test status | |
Simulation time | 560256378 ps |
CPU time | 106.43 seconds |
Started | Jul 11 06:02:59 PM PDT 24 |
Finished | Jul 11 06:05:04 PM PDT 24 |
Peak memory | 362216 kb |
Host | smart-ede8abea-f4c1-488f-920d-09c5f0df6bf8 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165949509 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.s ram_ctrl_partial_access.2165949509 |
Directory | /workspace/2.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.2795114099 |
Short name | T648 |
Test name | |
Test status | |
Simulation time | 51760105399 ps |
CPU time | 345.02 seconds |
Started | Jul 11 06:03:18 PM PDT 24 |
Finished | Jul 11 06:09:18 PM PDT 24 |
Peak memory | 202840 kb |
Host | smart-22a85e1b-f73c-4e2b-b5b0-bab1d66883f5 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795114099 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.sram_ctrl_partial_access_b2b.2795114099 |
Directory | /workspace/2.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_ram_cfg.3412072524 |
Short name | T282 |
Test name | |
Test status | |
Simulation time | 1435242375 ps |
CPU time | 3.17 seconds |
Started | Jul 11 06:02:58 PM PDT 24 |
Finished | Jul 11 06:03:20 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-db8fa890-1fe0-4394-aad8-ba1a76bcc04e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412072524 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.3412072524 |
Directory | /workspace/2.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_regwen.131495205 |
Short name | T869 |
Test name | |
Test status | |
Simulation time | 95258545679 ps |
CPU time | 696.85 seconds |
Started | Jul 11 06:02:59 PM PDT 24 |
Finished | Jul 11 06:14:55 PM PDT 24 |
Peak memory | 379784 kb |
Host | smart-8380abdf-1b63-4fad-b132-af313935788c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131495205 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.131495205 |
Directory | /workspace/2.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_sec_cm.2350164995 |
Short name | T31 |
Test name | |
Test status | |
Simulation time | 94084484 ps |
CPU time | 1.76 seconds |
Started | Jul 11 06:03:04 PM PDT 24 |
Finished | Jul 11 06:03:24 PM PDT 24 |
Peak memory | 222860 kb |
Host | smart-58aafb46-cf31-4374-901f-98f3bfc47a41 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350164995 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_sec_cm.2350164995 |
Directory | /workspace/2.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_smoke.459410611 |
Short name | T137 |
Test name | |
Test status | |
Simulation time | 436856725 ps |
CPU time | 55.56 seconds |
Started | Jul 11 06:02:59 PM PDT 24 |
Finished | Jul 11 06:04:13 PM PDT 24 |
Peak memory | 332548 kb |
Host | smart-9dd9d43c-c105-41e3-8fef-fd536a2b75fa |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459410611 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.459410611 |
Directory | /workspace/2.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.3467729473 |
Short name | T428 |
Test name | |
Test status | |
Simulation time | 1825068784 ps |
CPU time | 19.47 seconds |
Started | Jul 11 06:03:01 PM PDT 24 |
Finished | Jul 11 06:03:39 PM PDT 24 |
Peak memory | 210988 kb |
Host | smart-7c2ff4f7-c15f-4ff6-8e00-1e6ef9c531f2 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3467729473 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all_with_rand_reset.3467729473 |
Directory | /workspace/2.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_stress_pipeline.978227352 |
Short name | T908 |
Test name | |
Test status | |
Simulation time | 21994523489 ps |
CPU time | 313.94 seconds |
Started | Jul 11 06:03:02 PM PDT 24 |
Finished | Jul 11 06:08:35 PM PDT 24 |
Peak memory | 202900 kb |
Host | smart-f4cdc9a0-c677-4b6e-b134-285907385369 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978227352 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2. sram_ctrl_stress_pipeline.978227352 |
Directory | /workspace/2.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.315997061 |
Short name | T940 |
Test name | |
Test status | |
Simulation time | 2895110493 ps |
CPU time | 123.61 seconds |
Started | Jul 11 06:03:00 PM PDT 24 |
Finished | Jul 11 06:05:23 PM PDT 24 |
Peak memory | 370428 kb |
Host | smart-c358a5b8-45ff-48db-9e74-d27e2ce68bd8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315997061 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.sram_ctrl_throughput_w_partial_write.315997061 |
Directory | /workspace/2.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_access_during_key_req.785094946 |
Short name | T877 |
Test name | |
Test status | |
Simulation time | 22484224721 ps |
CPU time | 733.93 seconds |
Started | Jul 11 06:03:55 PM PDT 24 |
Finished | Jul 11 06:16:18 PM PDT 24 |
Peak memory | 379768 kb |
Host | smart-c4c87054-b6b1-4896-87c6-14d8205558cf |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785094946 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 20.sram_ctrl_access_during_key_req.785094946 |
Directory | /workspace/20.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_alert_test.1231677453 |
Short name | T440 |
Test name | |
Test status | |
Simulation time | 31043251 ps |
CPU time | 0.62 seconds |
Started | Jul 11 06:04:02 PM PDT 24 |
Finished | Jul 11 06:04:12 PM PDT 24 |
Peak memory | 202492 kb |
Host | smart-fc237415-4890-495a-9ffd-fa03af34cfc3 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231677453 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_alert_test.1231677453 |
Directory | /workspace/20.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_bijection.797379105 |
Short name | T890 |
Test name | |
Test status | |
Simulation time | 27669916225 ps |
CPU time | 1893.07 seconds |
Started | Jul 11 06:03:59 PM PDT 24 |
Finished | Jul 11 06:35:40 PM PDT 24 |
Peak memory | 203512 kb |
Host | smart-21ce4eb5-9dbb-49ac-b5e2-ba669cd17d1f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797379105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection. 797379105 |
Directory | /workspace/20.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_executable.1250100225 |
Short name | T518 |
Test name | |
Test status | |
Simulation time | 6969858506 ps |
CPU time | 87.59 seconds |
Started | Jul 11 06:03:59 PM PDT 24 |
Finished | Jul 11 06:05:35 PM PDT 24 |
Peak memory | 314252 kb |
Host | smart-fd9f9fbd-861f-4c78-9147-c63ee4b610b9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250100225 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executab le.1250100225 |
Directory | /workspace/20.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_lc_escalation.2338239748 |
Short name | T899 |
Test name | |
Test status | |
Simulation time | 26618996870 ps |
CPU time | 50.9 seconds |
Started | Jul 11 06:03:55 PM PDT 24 |
Finished | Jul 11 06:04:55 PM PDT 24 |
Peak memory | 211052 kb |
Host | smart-16915acd-7037-4a9a-933a-8f22935be1a1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338239748 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_es calation.2338239748 |
Directory | /workspace/20.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_max_throughput.4251727732 |
Short name | T418 |
Test name | |
Test status | |
Simulation time | 1495492352 ps |
CPU time | 72.96 seconds |
Started | Jul 11 06:04:08 PM PDT 24 |
Finished | Jul 11 06:05:30 PM PDT 24 |
Peak memory | 337620 kb |
Host | smart-bddad675-e14a-414c-a31d-eeae26dc9510 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251727732 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 20.sram_ctrl_max_throughput.4251727732 |
Directory | /workspace/20.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_mem_partial_access.2232376641 |
Short name | T102 |
Test name | |
Test status | |
Simulation time | 990007663 ps |
CPU time | 65.97 seconds |
Started | Jul 11 06:03:59 PM PDT 24 |
Finished | Jul 11 06:05:13 PM PDT 24 |
Peak memory | 211108 kb |
Host | smart-ce616117-2fa4-4ab6-9909-13dc878d18b1 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232376641 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 0.sram_ctrl_mem_partial_access.2232376641 |
Directory | /workspace/20.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_mem_walk.3770934918 |
Short name | T142 |
Test name | |
Test status | |
Simulation time | 54468481673 ps |
CPU time | 177.32 seconds |
Started | Jul 11 06:03:57 PM PDT 24 |
Finished | Jul 11 06:07:03 PM PDT 24 |
Peak memory | 210976 kb |
Host | smart-8d11e80a-e4ef-4ac3-b5d4-b6bc0701abc4 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770934918 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctr l_mem_walk.3770934918 |
Directory | /workspace/20.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_multiple_keys.215531976 |
Short name | T224 |
Test name | |
Test status | |
Simulation time | 23248320720 ps |
CPU time | 859.4 seconds |
Started | Jul 11 06:03:52 PM PDT 24 |
Finished | Jul 11 06:18:21 PM PDT 24 |
Peak memory | 363388 kb |
Host | smart-fb8913dd-dc34-42b7-be84-114df3d75189 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215531976 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multip le_keys.215531976 |
Directory | /workspace/20.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_partial_access.1072248799 |
Short name | T163 |
Test name | |
Test status | |
Simulation time | 819299161 ps |
CPU time | 37.53 seconds |
Started | Jul 11 06:03:54 PM PDT 24 |
Finished | Jul 11 06:04:40 PM PDT 24 |
Peak memory | 299932 kb |
Host | smart-3b415480-b977-481e-a83e-3fdee2bd2fc7 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072248799 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20. sram_ctrl_partial_access.1072248799 |
Directory | /workspace/20.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.1177624631 |
Short name | T420 |
Test name | |
Test status | |
Simulation time | 49105926602 ps |
CPU time | 306.47 seconds |
Started | Jul 11 06:03:52 PM PDT 24 |
Finished | Jul 11 06:09:08 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-440eac03-8b42-4d2a-8425-78892f67e700 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177624631 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 20.sram_ctrl_partial_access_b2b.1177624631 |
Directory | /workspace/20.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_ram_cfg.543138781 |
Short name | T330 |
Test name | |
Test status | |
Simulation time | 348202456 ps |
CPU time | 3.6 seconds |
Started | Jul 11 06:03:57 PM PDT 24 |
Finished | Jul 11 06:04:10 PM PDT 24 |
Peak memory | 203016 kb |
Host | smart-c0197a47-1eae-44e6-8c09-0daf8531e801 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543138781 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.543138781 |
Directory | /workspace/20.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_regwen.2116191159 |
Short name | T826 |
Test name | |
Test status | |
Simulation time | 10241741977 ps |
CPU time | 819.64 seconds |
Started | Jul 11 06:04:00 PM PDT 24 |
Finished | Jul 11 06:17:48 PM PDT 24 |
Peak memory | 379800 kb |
Host | smart-9bffc91b-56a6-4c65-8fab-9670bdfc362f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116191159 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.2116191159 |
Directory | /workspace/20.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_smoke.2292870917 |
Short name | T760 |
Test name | |
Test status | |
Simulation time | 3426415021 ps |
CPU time | 94.43 seconds |
Started | Jul 11 06:03:52 PM PDT 24 |
Finished | Jul 11 06:05:35 PM PDT 24 |
Peak memory | 368404 kb |
Host | smart-4ff3dd75-78b7-4984-a2d1-a24963f1d882 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292870917 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.2292870917 |
Directory | /workspace/20.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_stress_all.1296509903 |
Short name | T910 |
Test name | |
Test status | |
Simulation time | 39031514246 ps |
CPU time | 692.38 seconds |
Started | Jul 11 06:03:55 PM PDT 24 |
Finished | Jul 11 06:15:35 PM PDT 24 |
Peak memory | 381772 kb |
Host | smart-1cdb79c2-c879-47c9-80c9-d3e23b838077 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296509903 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 20.sram_ctrl_stress_all.1296509903 |
Directory | /workspace/20.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.258167877 |
Short name | T774 |
Test name | |
Test status | |
Simulation time | 2000639065 ps |
CPU time | 198.85 seconds |
Started | Jul 11 06:04:07 PM PDT 24 |
Finished | Jul 11 06:07:35 PM PDT 24 |
Peak memory | 376692 kb |
Host | smart-471a909f-ac5e-45cb-8d0a-c56c1b500c2c |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=258167877 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all_with_rand_reset.258167877 |
Directory | /workspace/20.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_stress_pipeline.3374248062 |
Short name | T728 |
Test name | |
Test status | |
Simulation time | 6087570951 ps |
CPU time | 321.76 seconds |
Started | Jul 11 06:03:51 PM PDT 24 |
Finished | Jul 11 06:09:22 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-edffd0b2-3ca8-4151-9809-23f136fc8332 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374248062 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 0.sram_ctrl_stress_pipeline.3374248062 |
Directory | /workspace/20.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.2882263954 |
Short name | T382 |
Test name | |
Test status | |
Simulation time | 1362214174 ps |
CPU time | 15.32 seconds |
Started | Jul 11 06:03:55 PM PDT 24 |
Finished | Jul 11 06:04:19 PM PDT 24 |
Peak memory | 240836 kb |
Host | smart-3a20f03a-cdb7-4fd7-a436-34663b2bb836 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882263954 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 20.sram_ctrl_throughput_w_partial_write.2882263954 |
Directory | /workspace/20.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_access_during_key_req.909121780 |
Short name | T349 |
Test name | |
Test status | |
Simulation time | 5249905623 ps |
CPU time | 300.43 seconds |
Started | Jul 11 06:03:54 PM PDT 24 |
Finished | Jul 11 06:09:03 PM PDT 24 |
Peak memory | 373220 kb |
Host | smart-16d30d12-091f-46c8-a441-98d34d3b7d8f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909121780 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 21.sram_ctrl_access_during_key_req.909121780 |
Directory | /workspace/21.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_alert_test.383659471 |
Short name | T658 |
Test name | |
Test status | |
Simulation time | 23136676 ps |
CPU time | 0.66 seconds |
Started | Jul 11 06:04:00 PM PDT 24 |
Finished | Jul 11 06:04:09 PM PDT 24 |
Peak memory | 202580 kb |
Host | smart-c862e1ad-244c-402e-a142-f4b3d146688d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383659471 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_alert_test.383659471 |
Directory | /workspace/21.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_bijection.915260042 |
Short name | T40 |
Test name | |
Test status | |
Simulation time | 440749125097 ps |
CPU time | 2581.14 seconds |
Started | Jul 11 06:04:02 PM PDT 24 |
Finished | Jul 11 06:47:13 PM PDT 24 |
Peak memory | 203504 kb |
Host | smart-b6e269fb-1820-40bf-be31-8c7a8981618f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915260042 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection. 915260042 |
Directory | /workspace/21.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_executable.3446144905 |
Short name | T1 |
Test name | |
Test status | |
Simulation time | 50200651727 ps |
CPU time | 208.41 seconds |
Started | Jul 11 06:04:04 PM PDT 24 |
Finished | Jul 11 06:07:42 PM PDT 24 |
Peak memory | 376380 kb |
Host | smart-b5c918fc-851a-4d63-b67d-2258c8195829 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446144905 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executab le.3446144905 |
Directory | /workspace/21.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_lc_escalation.3401843194 |
Short name | T592 |
Test name | |
Test status | |
Simulation time | 44885663222 ps |
CPU time | 74.42 seconds |
Started | Jul 11 06:03:56 PM PDT 24 |
Finished | Jul 11 06:05:19 PM PDT 24 |
Peak memory | 211124 kb |
Host | smart-294d65e4-d582-405a-a399-e904f3d02e4e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401843194 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_es calation.3401843194 |
Directory | /workspace/21.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_max_throughput.4279050437 |
Short name | T409 |
Test name | |
Test status | |
Simulation time | 728441314 ps |
CPU time | 8.41 seconds |
Started | Jul 11 06:03:55 PM PDT 24 |
Finished | Jul 11 06:04:12 PM PDT 24 |
Peak memory | 221204 kb |
Host | smart-06a46c68-c998-42a5-8eb8-75977e74fc13 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279050437 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 21.sram_ctrl_max_throughput.4279050437 |
Directory | /workspace/21.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_mem_partial_access.2379797356 |
Short name | T292 |
Test name | |
Test status | |
Simulation time | 1069915840 ps |
CPU time | 66.95 seconds |
Started | Jul 11 06:04:01 PM PDT 24 |
Finished | Jul 11 06:05:17 PM PDT 24 |
Peak memory | 210916 kb |
Host | smart-55e52dcd-04d3-4d91-9154-cd517e30e939 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379797356 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 1.sram_ctrl_mem_partial_access.2379797356 |
Directory | /workspace/21.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_mem_walk.1216543 |
Short name | T429 |
Test name | |
Test status | |
Simulation time | 9169207904 ps |
CPU time | 258.76 seconds |
Started | Jul 11 06:04:04 PM PDT 24 |
Finished | Jul 11 06:08:33 PM PDT 24 |
Peak memory | 212108 kb |
Host | smart-b89f5535-f211-4a84-9aea-f61b7f7e6e7a |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216543 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sra m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_m em_walk.1216543 |
Directory | /workspace/21.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_multiple_keys.2535152193 |
Short name | T286 |
Test name | |
Test status | |
Simulation time | 42140443355 ps |
CPU time | 1450.47 seconds |
Started | Jul 11 06:04:04 PM PDT 24 |
Finished | Jul 11 06:28:25 PM PDT 24 |
Peak memory | 377676 kb |
Host | smart-a164220d-8692-495e-9612-de3ecd6c7432 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535152193 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multi ple_keys.2535152193 |
Directory | /workspace/21.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_partial_access.4231188266 |
Short name | T570 |
Test name | |
Test status | |
Simulation time | 3269487560 ps |
CPU time | 52 seconds |
Started | Jul 11 06:04:11 PM PDT 24 |
Finished | Jul 11 06:05:11 PM PDT 24 |
Peak memory | 307932 kb |
Host | smart-ef30f8a9-0763-4634-a380-655c8f25f6fc |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231188266 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21. sram_ctrl_partial_access.4231188266 |
Directory | /workspace/21.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.1197388535 |
Short name | T585 |
Test name | |
Test status | |
Simulation time | 16950268361 ps |
CPU time | 109.89 seconds |
Started | Jul 11 06:03:54 PM PDT 24 |
Finished | Jul 11 06:05:52 PM PDT 24 |
Peak memory | 202896 kb |
Host | smart-a4e5e61d-ffe2-418f-9056-2e297c160995 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197388535 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 21.sram_ctrl_partial_access_b2b.1197388535 |
Directory | /workspace/21.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_ram_cfg.1490551883 |
Short name | T139 |
Test name | |
Test status | |
Simulation time | 1347977902 ps |
CPU time | 3.79 seconds |
Started | Jul 11 06:04:04 PM PDT 24 |
Finished | Jul 11 06:04:18 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-7c57d2ba-d83c-4981-b55b-975d466ac7c0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490551883 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.1490551883 |
Directory | /workspace/21.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_regwen.2052977049 |
Short name | T775 |
Test name | |
Test status | |
Simulation time | 75038332857 ps |
CPU time | 1915.71 seconds |
Started | Jul 11 06:03:59 PM PDT 24 |
Finished | Jul 11 06:36:03 PM PDT 24 |
Peak memory | 379936 kb |
Host | smart-52f79e5d-111b-4262-8615-de8bf92ab13b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052977049 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.2052977049 |
Directory | /workspace/21.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_smoke.2469109831 |
Short name | T778 |
Test name | |
Test status | |
Simulation time | 1312811025 ps |
CPU time | 10.2 seconds |
Started | Jul 11 06:04:05 PM PDT 24 |
Finished | Jul 11 06:04:25 PM PDT 24 |
Peak memory | 202800 kb |
Host | smart-a118be7b-7c3a-425d-b246-ef5ee773105a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469109831 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.2469109831 |
Directory | /workspace/21.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_stress_all.4080063811 |
Short name | T124 |
Test name | |
Test status | |
Simulation time | 339284392150 ps |
CPU time | 7647.29 seconds |
Started | Jul 11 06:04:00 PM PDT 24 |
Finished | Jul 11 08:11:36 PM PDT 24 |
Peak memory | 387916 kb |
Host | smart-4db2d246-fd8d-4d09-80f6-aef89d185b0b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080063811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 21.sram_ctrl_stress_all.4080063811 |
Directory | /workspace/21.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.3854427225 |
Short name | T903 |
Test name | |
Test status | |
Simulation time | 405272534 ps |
CPU time | 8.58 seconds |
Started | Jul 11 06:03:59 PM PDT 24 |
Finished | Jul 11 06:04:16 PM PDT 24 |
Peak memory | 211064 kb |
Host | smart-592260c2-2c8a-4abe-8578-50968d36e625 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3854427225 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all_with_rand_reset.3854427225 |
Directory | /workspace/21.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_stress_pipeline.2762165205 |
Short name | T698 |
Test name | |
Test status | |
Simulation time | 50546577693 ps |
CPU time | 332.13 seconds |
Started | Jul 11 06:04:04 PM PDT 24 |
Finished | Jul 11 06:09:45 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-4457f84d-e590-4067-88c9-4f2ddb875291 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762165205 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 1.sram_ctrl_stress_pipeline.2762165205 |
Directory | /workspace/21.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.2612881830 |
Short name | T263 |
Test name | |
Test status | |
Simulation time | 815535080 ps |
CPU time | 112.23 seconds |
Started | Jul 11 06:04:03 PM PDT 24 |
Finished | Jul 11 06:06:05 PM PDT 24 |
Peak memory | 368668 kb |
Host | smart-3ebb2c8f-b973-465c-879d-88f7c074760e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612881830 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 21.sram_ctrl_throughput_w_partial_write.2612881830 |
Directory | /workspace/21.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_access_during_key_req.4015519467 |
Short name | T557 |
Test name | |
Test status | |
Simulation time | 37422631488 ps |
CPU time | 571.46 seconds |
Started | Jul 11 06:04:07 PM PDT 24 |
Finished | Jul 11 06:13:48 PM PDT 24 |
Peak memory | 372468 kb |
Host | smart-8bb37a63-b5d4-4396-ad97-4eed559833d9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015519467 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 22.sram_ctrl_access_during_key_req.4015519467 |
Directory | /workspace/22.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_alert_test.3815755898 |
Short name | T235 |
Test name | |
Test status | |
Simulation time | 37341160 ps |
CPU time | 0.64 seconds |
Started | Jul 11 06:03:59 PM PDT 24 |
Finished | Jul 11 06:04:09 PM PDT 24 |
Peak memory | 202472 kb |
Host | smart-794de323-86bd-435d-99cf-08386cc3e511 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815755898 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_alert_test.3815755898 |
Directory | /workspace/22.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_bijection.2541633530 |
Short name | T722 |
Test name | |
Test status | |
Simulation time | 26312898744 ps |
CPU time | 1857.41 seconds |
Started | Jul 11 06:04:00 PM PDT 24 |
Finished | Jul 11 06:35:06 PM PDT 24 |
Peak memory | 203588 kb |
Host | smart-02f722dd-f90d-4e7a-8171-43c95a686fb6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541633530 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection .2541633530 |
Directory | /workspace/22.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_executable.2454024724 |
Short name | T483 |
Test name | |
Test status | |
Simulation time | 48423978606 ps |
CPU time | 2337.48 seconds |
Started | Jul 11 06:04:03 PM PDT 24 |
Finished | Jul 11 06:43:10 PM PDT 24 |
Peak memory | 380484 kb |
Host | smart-a9f3f88b-1c8d-46e7-9eba-49709df99207 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454024724 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_executab le.2454024724 |
Directory | /workspace/22.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_lc_escalation.418418253 |
Short name | T683 |
Test name | |
Test status | |
Simulation time | 14738566190 ps |
CPU time | 84.71 seconds |
Started | Jul 11 06:04:01 PM PDT 24 |
Finished | Jul 11 06:05:34 PM PDT 24 |
Peak memory | 202808 kb |
Host | smart-6e4f6b05-c2a3-4f1d-8777-d077e8517b01 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418418253 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_esc alation.418418253 |
Directory | /workspace/22.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_max_throughput.992844736 |
Short name | T792 |
Test name | |
Test status | |
Simulation time | 2848361837 ps |
CPU time | 31.11 seconds |
Started | Jul 11 06:04:04 PM PDT 24 |
Finished | Jul 11 06:04:44 PM PDT 24 |
Peak memory | 279204 kb |
Host | smart-bc71e0ba-9a58-4117-a1ec-bfb64caf2e98 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992844736 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 22.sram_ctrl_max_throughput.992844736 |
Directory | /workspace/22.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_mem_partial_access.4097023555 |
Short name | T99 |
Test name | |
Test status | |
Simulation time | 1007582306 ps |
CPU time | 66.35 seconds |
Started | Jul 11 06:04:11 PM PDT 24 |
Finished | Jul 11 06:05:25 PM PDT 24 |
Peak memory | 210980 kb |
Host | smart-56507acc-1ee3-4fa1-a792-7cc98fdba297 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097023555 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 2.sram_ctrl_mem_partial_access.4097023555 |
Directory | /workspace/22.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_mem_walk.1707821353 |
Short name | T919 |
Test name | |
Test status | |
Simulation time | 5060021043 ps |
CPU time | 131.98 seconds |
Started | Jul 11 06:04:00 PM PDT 24 |
Finished | Jul 11 06:06:22 PM PDT 24 |
Peak memory | 211048 kb |
Host | smart-a68cdf3e-ddc2-4902-ac83-187d50325988 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707821353 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctr l_mem_walk.1707821353 |
Directory | /workspace/22.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_multiple_keys.3169319345 |
Short name | T691 |
Test name | |
Test status | |
Simulation time | 11130594103 ps |
CPU time | 146.71 seconds |
Started | Jul 11 06:04:04 PM PDT 24 |
Finished | Jul 11 06:06:41 PM PDT 24 |
Peak memory | 326948 kb |
Host | smart-180940a7-eb52-4bac-9aa2-111f098a498b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169319345 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multi ple_keys.3169319345 |
Directory | /workspace/22.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_partial_access.3482192966 |
Short name | T901 |
Test name | |
Test status | |
Simulation time | 1396395713 ps |
CPU time | 126.22 seconds |
Started | Jul 11 06:03:59 PM PDT 24 |
Finished | Jul 11 06:06:14 PM PDT 24 |
Peak memory | 368340 kb |
Host | smart-266503df-5476-4a8b-a67f-4328b7417170 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482192966 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22. sram_ctrl_partial_access.3482192966 |
Directory | /workspace/22.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.775076851 |
Short name | T117 |
Test name | |
Test status | |
Simulation time | 27597807027 ps |
CPU time | 436.38 seconds |
Started | Jul 11 06:04:07 PM PDT 24 |
Finished | Jul 11 06:11:32 PM PDT 24 |
Peak memory | 202800 kb |
Host | smart-8ea3a388-7220-4ead-aaf2-1678dd690a3f |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775076851 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 22.sram_ctrl_partial_access_b2b.775076851 |
Directory | /workspace/22.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_ram_cfg.3310330884 |
Short name | T262 |
Test name | |
Test status | |
Simulation time | 360219983 ps |
CPU time | 3.38 seconds |
Started | Jul 11 06:04:03 PM PDT 24 |
Finished | Jul 11 06:04:16 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-fdb5e11c-e48e-49a5-89ea-88b1cf9624ef |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310330884 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.3310330884 |
Directory | /workspace/22.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_regwen.2815542278 |
Short name | T765 |
Test name | |
Test status | |
Simulation time | 11206535333 ps |
CPU time | 260.46 seconds |
Started | Jul 11 06:04:04 PM PDT 24 |
Finished | Jul 11 06:08:34 PM PDT 24 |
Peak memory | 368444 kb |
Host | smart-cdfcaa71-8003-488a-a54b-fae6b312508f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815542278 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.2815542278 |
Directory | /workspace/22.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_smoke.2021578152 |
Short name | T718 |
Test name | |
Test status | |
Simulation time | 4403705399 ps |
CPU time | 19.54 seconds |
Started | Jul 11 06:04:04 PM PDT 24 |
Finished | Jul 11 06:04:33 PM PDT 24 |
Peak memory | 258096 kb |
Host | smart-45927c24-1baf-4f92-b1c1-3fed283d0a30 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021578152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.2021578152 |
Directory | /workspace/22.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_stress_all.3998991134 |
Short name | T448 |
Test name | |
Test status | |
Simulation time | 96927824593 ps |
CPU time | 3591.86 seconds |
Started | Jul 11 06:04:07 PM PDT 24 |
Finished | Jul 11 07:04:08 PM PDT 24 |
Peak memory | 381804 kb |
Host | smart-6fea9bbb-6e4d-4acf-be8b-cb6663d9d0cb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998991134 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 22.sram_ctrl_stress_all.3998991134 |
Directory | /workspace/22.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.1547332095 |
Short name | T24 |
Test name | |
Test status | |
Simulation time | 6377159229 ps |
CPU time | 45.51 seconds |
Started | Jul 11 06:04:01 PM PDT 24 |
Finished | Jul 11 06:04:56 PM PDT 24 |
Peak memory | 218460 kb |
Host | smart-1580b3dd-abbc-4f24-be29-4077eaed5afd |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1547332095 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all_with_rand_reset.1547332095 |
Directory | /workspace/22.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_stress_pipeline.4193232091 |
Short name | T381 |
Test name | |
Test status | |
Simulation time | 19800742016 ps |
CPU time | 344.4 seconds |
Started | Jul 11 06:04:07 PM PDT 24 |
Finished | Jul 11 06:10:00 PM PDT 24 |
Peak memory | 202800 kb |
Host | smart-bf8e8d48-1599-4db7-a3d7-60c8e552563b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193232091 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 2.sram_ctrl_stress_pipeline.4193232091 |
Directory | /workspace/22.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.1540224774 |
Short name | T301 |
Test name | |
Test status | |
Simulation time | 759619188 ps |
CPU time | 32.95 seconds |
Started | Jul 11 06:04:01 PM PDT 24 |
Finished | Jul 11 06:04:43 PM PDT 24 |
Peak memory | 291724 kb |
Host | smart-6ad8e77c-9aa8-4370-8e9b-129dccf2d3a6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540224774 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 22.sram_ctrl_throughput_w_partial_write.1540224774 |
Directory | /workspace/22.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_access_during_key_req.216799964 |
Short name | T284 |
Test name | |
Test status | |
Simulation time | 16695795023 ps |
CPU time | 876.51 seconds |
Started | Jul 11 06:04:00 PM PDT 24 |
Finished | Jul 11 06:18:45 PM PDT 24 |
Peak memory | 379792 kb |
Host | smart-b11b3dc1-1fac-467c-83e6-bbd3177668e4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216799964 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 23.sram_ctrl_access_during_key_req.216799964 |
Directory | /workspace/23.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_alert_test.3009220615 |
Short name | T780 |
Test name | |
Test status | |
Simulation time | 48411584 ps |
CPU time | 0.65 seconds |
Started | Jul 11 06:04:08 PM PDT 24 |
Finished | Jul 11 06:04:18 PM PDT 24 |
Peak memory | 202580 kb |
Host | smart-0b854b2b-02d5-40be-85cc-908c05908dd4 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009220615 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_alert_test.3009220615 |
Directory | /workspace/23.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_bijection.2606723243 |
Short name | T599 |
Test name | |
Test status | |
Simulation time | 55152435833 ps |
CPU time | 881.68 seconds |
Started | Jul 11 06:04:07 PM PDT 24 |
Finished | Jul 11 06:18:58 PM PDT 24 |
Peak memory | 203472 kb |
Host | smart-f003ace5-283a-4de7-944e-1bd89f019601 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606723243 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection .2606723243 |
Directory | /workspace/23.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_executable.1507813551 |
Short name | T258 |
Test name | |
Test status | |
Simulation time | 22527633672 ps |
CPU time | 1091.33 seconds |
Started | Jul 11 06:04:06 PM PDT 24 |
Finished | Jul 11 06:22:26 PM PDT 24 |
Peak memory | 376624 kb |
Host | smart-e7b8c663-84d9-40de-b2a9-2f6a6276e1d3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507813551 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executab le.1507813551 |
Directory | /workspace/23.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_lc_escalation.2993722933 |
Short name | T145 |
Test name | |
Test status | |
Simulation time | 8190523707 ps |
CPU time | 49.72 seconds |
Started | Jul 11 06:04:00 PM PDT 24 |
Finished | Jul 11 06:04:58 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-8c273007-ebd2-4e47-bdcb-df68669b5573 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993722933 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_es calation.2993722933 |
Directory | /workspace/23.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_max_throughput.3375202753 |
Short name | T214 |
Test name | |
Test status | |
Simulation time | 1600657430 ps |
CPU time | 61.27 seconds |
Started | Jul 11 06:04:07 PM PDT 24 |
Finished | Jul 11 06:05:17 PM PDT 24 |
Peak memory | 320220 kb |
Host | smart-90c7f1c8-97aa-4ba6-93dc-c6ad345dc397 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375202753 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 23.sram_ctrl_max_throughput.3375202753 |
Directory | /workspace/23.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_mem_partial_access.3832796871 |
Short name | T46 |
Test name | |
Test status | |
Simulation time | 1444957051 ps |
CPU time | 73.72 seconds |
Started | Jul 11 06:04:00 PM PDT 24 |
Finished | Jul 11 06:05:22 PM PDT 24 |
Peak memory | 219140 kb |
Host | smart-0113ce4d-9244-4cd5-a4fb-8c6b0b637b5c |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832796871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 3.sram_ctrl_mem_partial_access.3832796871 |
Directory | /workspace/23.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_mem_walk.3769533620 |
Short name | T535 |
Test name | |
Test status | |
Simulation time | 21886544741 ps |
CPU time | 302.23 seconds |
Started | Jul 11 06:04:06 PM PDT 24 |
Finished | Jul 11 06:09:17 PM PDT 24 |
Peak memory | 211048 kb |
Host | smart-51485829-b69f-43ea-8bb0-e2794820eb3e |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769533620 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctr l_mem_walk.3769533620 |
Directory | /workspace/23.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_multiple_keys.3979478268 |
Short name | T265 |
Test name | |
Test status | |
Simulation time | 41678536952 ps |
CPU time | 941.21 seconds |
Started | Jul 11 06:04:10 PM PDT 24 |
Finished | Jul 11 06:20:00 PM PDT 24 |
Peak memory | 377700 kb |
Host | smart-3b7eac2a-2ed0-4630-980d-62e7474f7b3b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979478268 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multi ple_keys.3979478268 |
Directory | /workspace/23.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_partial_access.3412415286 |
Short name | T319 |
Test name | |
Test status | |
Simulation time | 1313782871 ps |
CPU time | 19.74 seconds |
Started | Jul 11 06:04:04 PM PDT 24 |
Finished | Jul 11 06:04:33 PM PDT 24 |
Peak memory | 202708 kb |
Host | smart-06f3d409-d88c-4bea-be7f-84f79047b38d |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412415286 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23. sram_ctrl_partial_access.3412415286 |
Directory | /workspace/23.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.125596285 |
Short name | T865 |
Test name | |
Test status | |
Simulation time | 38197930198 ps |
CPU time | 415.69 seconds |
Started | Jul 11 06:04:03 PM PDT 24 |
Finished | Jul 11 06:11:08 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-088a00c6-8ac2-4240-a7fe-f0e4069c1648 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125596285 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 23.sram_ctrl_partial_access_b2b.125596285 |
Directory | /workspace/23.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_ram_cfg.3888935868 |
Short name | T630 |
Test name | |
Test status | |
Simulation time | 2252651680 ps |
CPU time | 3.78 seconds |
Started | Jul 11 06:04:04 PM PDT 24 |
Finished | Jul 11 06:04:17 PM PDT 24 |
Peak memory | 202976 kb |
Host | smart-0c6362b8-0a32-4c83-821e-7efd9fc697a7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888935868 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.3888935868 |
Directory | /workspace/23.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_regwen.3503993234 |
Short name | T663 |
Test name | |
Test status | |
Simulation time | 20747627192 ps |
CPU time | 2063.43 seconds |
Started | Jul 11 06:04:04 PM PDT 24 |
Finished | Jul 11 06:38:37 PM PDT 24 |
Peak memory | 378752 kb |
Host | smart-7b158520-aca2-4363-b12c-efabd550da2c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503993234 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.3503993234 |
Directory | /workspace/23.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_smoke.2793389401 |
Short name | T889 |
Test name | |
Test status | |
Simulation time | 15492301833 ps |
CPU time | 20.32 seconds |
Started | Jul 11 06:04:06 PM PDT 24 |
Finished | Jul 11 06:04:35 PM PDT 24 |
Peak memory | 202880 kb |
Host | smart-b6db5362-8131-44c9-9e3a-65aa1073347b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793389401 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.2793389401 |
Directory | /workspace/23.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_stress_all.1393081259 |
Short name | T863 |
Test name | |
Test status | |
Simulation time | 291653066936 ps |
CPU time | 3033.14 seconds |
Started | Jul 11 06:03:58 PM PDT 24 |
Finished | Jul 11 06:54:40 PM PDT 24 |
Peak memory | 379808 kb |
Host | smart-7ad07b6c-9330-46e7-9303-b3188e25339a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393081259 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 23.sram_ctrl_stress_all.1393081259 |
Directory | /workspace/23.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.2079847468 |
Short name | T697 |
Test name | |
Test status | |
Simulation time | 6910715947 ps |
CPU time | 95.43 seconds |
Started | Jul 11 06:04:06 PM PDT 24 |
Finished | Jul 11 06:05:50 PM PDT 24 |
Peak memory | 315328 kb |
Host | smart-a5404533-a156-4d56-9674-079d4c206258 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2079847468 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all_with_rand_reset.2079847468 |
Directory | /workspace/23.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_stress_pipeline.2878036182 |
Short name | T561 |
Test name | |
Test status | |
Simulation time | 33690410790 ps |
CPU time | 331.4 seconds |
Started | Jul 11 06:04:02 PM PDT 24 |
Finished | Jul 11 06:09:42 PM PDT 24 |
Peak memory | 202812 kb |
Host | smart-65309ee5-3d8f-485f-9402-b57d339b65dc |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878036182 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 3.sram_ctrl_stress_pipeline.2878036182 |
Directory | /workspace/23.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.3284558218 |
Short name | T476 |
Test name | |
Test status | |
Simulation time | 1334829092 ps |
CPU time | 5.93 seconds |
Started | Jul 11 06:04:08 PM PDT 24 |
Finished | Jul 11 06:04:23 PM PDT 24 |
Peak memory | 202608 kb |
Host | smart-eef0fd9c-f691-49b7-aa2a-6572d7948014 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284558218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 23.sram_ctrl_throughput_w_partial_write.3284558218 |
Directory | /workspace/23.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_access_during_key_req.3244603593 |
Short name | T927 |
Test name | |
Test status | |
Simulation time | 80843450552 ps |
CPU time | 2095.99 seconds |
Started | Jul 11 06:04:07 PM PDT 24 |
Finished | Jul 11 06:39:13 PM PDT 24 |
Peak memory | 379772 kb |
Host | smart-ee610d29-9429-4406-9128-6b4f2788b5da |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244603593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 24.sram_ctrl_access_during_key_req.3244603593 |
Directory | /workspace/24.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_alert_test.1832746622 |
Short name | T237 |
Test name | |
Test status | |
Simulation time | 13133940 ps |
CPU time | 0.66 seconds |
Started | Jul 11 06:04:11 PM PDT 24 |
Finished | Jul 11 06:04:20 PM PDT 24 |
Peak memory | 202600 kb |
Host | smart-a67ae64c-72bd-479c-bd11-0bd9c2bc5448 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832746622 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_alert_test.1832746622 |
Directory | /workspace/24.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_bijection.1757346257 |
Short name | T666 |
Test name | |
Test status | |
Simulation time | 37122608337 ps |
CPU time | 880.96 seconds |
Started | Jul 11 06:04:05 PM PDT 24 |
Finished | Jul 11 06:18:55 PM PDT 24 |
Peak memory | 203464 kb |
Host | smart-502a0dbb-6be8-4744-9fe2-2c60cd40512f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757346257 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection .1757346257 |
Directory | /workspace/24.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_executable.1514048099 |
Short name | T938 |
Test name | |
Test status | |
Simulation time | 36471336247 ps |
CPU time | 1219.35 seconds |
Started | Jul 11 06:04:04 PM PDT 24 |
Finished | Jul 11 06:24:34 PM PDT 24 |
Peak memory | 379772 kb |
Host | smart-f9a44355-7b13-4e60-8812-ee0e8a9373b0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514048099 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executab le.1514048099 |
Directory | /workspace/24.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_lc_escalation.3674759586 |
Short name | T636 |
Test name | |
Test status | |
Simulation time | 18362417865 ps |
CPU time | 64.2 seconds |
Started | Jul 11 06:04:05 PM PDT 24 |
Finished | Jul 11 06:05:18 PM PDT 24 |
Peak memory | 202924 kb |
Host | smart-1cd5316b-397e-4a88-b345-ea64538aafe9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674759586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_es calation.3674759586 |
Directory | /workspace/24.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_max_throughput.3651139269 |
Short name | T514 |
Test name | |
Test status | |
Simulation time | 1452158388 ps |
CPU time | 17.32 seconds |
Started | Jul 11 06:04:11 PM PDT 24 |
Finished | Jul 11 06:04:36 PM PDT 24 |
Peak memory | 251884 kb |
Host | smart-4c9c7ddc-3f15-4198-962d-84f1c1f74935 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651139269 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 24.sram_ctrl_max_throughput.3651139269 |
Directory | /workspace/24.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_mem_partial_access.2787563878 |
Short name | T662 |
Test name | |
Test status | |
Simulation time | 5757700739 ps |
CPU time | 78.38 seconds |
Started | Jul 11 06:04:07 PM PDT 24 |
Finished | Jul 11 06:05:34 PM PDT 24 |
Peak memory | 211052 kb |
Host | smart-330ee62e-f756-40da-9c0d-55d2c8d829e6 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787563878 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 4.sram_ctrl_mem_partial_access.2787563878 |
Directory | /workspace/24.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_mem_walk.661844107 |
Short name | T45 |
Test name | |
Test status | |
Simulation time | 8078810580 ps |
CPU time | 304.66 seconds |
Started | Jul 11 06:04:10 PM PDT 24 |
Finished | Jul 11 06:09:24 PM PDT 24 |
Peak memory | 210980 kb |
Host | smart-4bb63b53-c288-4d90-b5b6-cac9e2aa8a36 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661844107 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl _mem_walk.661844107 |
Directory | /workspace/24.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_multiple_keys.3012687913 |
Short name | T781 |
Test name | |
Test status | |
Simulation time | 12164891868 ps |
CPU time | 608.51 seconds |
Started | Jul 11 06:04:07 PM PDT 24 |
Finished | Jul 11 06:14:25 PM PDT 24 |
Peak memory | 378592 kb |
Host | smart-55165750-e7bd-40cd-93ba-de9ce5905a58 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012687913 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multi ple_keys.3012687913 |
Directory | /workspace/24.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_partial_access.3311222508 |
Short name | T202 |
Test name | |
Test status | |
Simulation time | 1712808929 ps |
CPU time | 19.15 seconds |
Started | Jul 11 06:04:10 PM PDT 24 |
Finished | Jul 11 06:04:38 PM PDT 24 |
Peak memory | 262196 kb |
Host | smart-845a5e8e-159f-4b4c-b8ce-8edbf9a8b8a2 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311222508 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24. sram_ctrl_partial_access.3311222508 |
Directory | /workspace/24.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.160582423 |
Short name | T121 |
Test name | |
Test status | |
Simulation time | 4672172021 ps |
CPU time | 303.84 seconds |
Started | Jul 11 06:04:05 PM PDT 24 |
Finished | Jul 11 06:09:18 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-b21f785e-ca99-4c65-8ac3-e06b5a4459dc |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160582423 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 24.sram_ctrl_partial_access_b2b.160582423 |
Directory | /workspace/24.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_ram_cfg.2902782750 |
Short name | T902 |
Test name | |
Test status | |
Simulation time | 561938134 ps |
CPU time | 3.3 seconds |
Started | Jul 11 06:04:09 PM PDT 24 |
Finished | Jul 11 06:04:21 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-918e00bd-da15-468f-9ceb-b46c4338af20 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902782750 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.2902782750 |
Directory | /workspace/24.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_regwen.2968572143 |
Short name | T913 |
Test name | |
Test status | |
Simulation time | 2100892519 ps |
CPU time | 51.29 seconds |
Started | Jul 11 06:04:06 PM PDT 24 |
Finished | Jul 11 06:05:07 PM PDT 24 |
Peak memory | 270260 kb |
Host | smart-56ca331c-fabf-406f-87e7-9f4573295f7b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968572143 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.2968572143 |
Directory | /workspace/24.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_smoke.1176439076 |
Short name | T498 |
Test name | |
Test status | |
Simulation time | 767382681 ps |
CPU time | 7.16 seconds |
Started | Jul 11 06:04:02 PM PDT 24 |
Finished | Jul 11 06:04:18 PM PDT 24 |
Peak memory | 202752 kb |
Host | smart-b0ef182d-2f9c-4522-ac7c-a9a15d44da28 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176439076 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.1176439076 |
Directory | /workspace/24.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_stress_all.4171718620 |
Short name | T726 |
Test name | |
Test status | |
Simulation time | 99179728782 ps |
CPU time | 4170.26 seconds |
Started | Jul 11 06:04:06 PM PDT 24 |
Finished | Jul 11 07:13:45 PM PDT 24 |
Peak memory | 390068 kb |
Host | smart-893798d7-be8d-45c6-a53e-40feb58d161d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171718620 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 24.sram_ctrl_stress_all.4171718620 |
Directory | /workspace/24.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.4274665548 |
Short name | T287 |
Test name | |
Test status | |
Simulation time | 2300056978 ps |
CPU time | 28.68 seconds |
Started | Jul 11 06:04:07 PM PDT 24 |
Finished | Jul 11 06:04:45 PM PDT 24 |
Peak memory | 211164 kb |
Host | smart-7c561278-3e79-464e-9e88-b4e9d882d16f |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4274665548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all_with_rand_reset.4274665548 |
Directory | /workspace/24.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_stress_pipeline.491749007 |
Short name | T534 |
Test name | |
Test status | |
Simulation time | 27705532542 ps |
CPU time | 374.75 seconds |
Started | Jul 11 06:04:02 PM PDT 24 |
Finished | Jul 11 06:10:26 PM PDT 24 |
Peak memory | 202856 kb |
Host | smart-79c7605b-496c-469c-82a4-65c9550697c9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491749007 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24 .sram_ctrl_stress_pipeline.491749007 |
Directory | /workspace/24.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.2707096284 |
Short name | T512 |
Test name | |
Test status | |
Simulation time | 1604656900 ps |
CPU time | 77.52 seconds |
Started | Jul 11 06:04:08 PM PDT 24 |
Finished | Jul 11 06:05:35 PM PDT 24 |
Peak memory | 345960 kb |
Host | smart-7e9e3656-4d9f-4f15-bcfe-7ccd81b260f1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707096284 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 24.sram_ctrl_throughput_w_partial_write.2707096284 |
Directory | /workspace/24.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_access_during_key_req.4056253840 |
Short name | T380 |
Test name | |
Test status | |
Simulation time | 35447496096 ps |
CPU time | 820.51 seconds |
Started | Jul 11 06:04:08 PM PDT 24 |
Finished | Jul 11 06:17:58 PM PDT 24 |
Peak memory | 373560 kb |
Host | smart-05861d88-219c-4dc5-9259-df87e8a0d328 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056253840 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 25.sram_ctrl_access_during_key_req.4056253840 |
Directory | /workspace/25.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_alert_test.3528322943 |
Short name | T848 |
Test name | |
Test status | |
Simulation time | 35926373 ps |
CPU time | 0.64 seconds |
Started | Jul 11 06:04:05 PM PDT 24 |
Finished | Jul 11 06:04:15 PM PDT 24 |
Peak memory | 202616 kb |
Host | smart-87a3c0b5-4561-4f44-bdae-0c06a6339a09 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528322943 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_alert_test.3528322943 |
Directory | /workspace/25.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_bijection.3213970903 |
Short name | T481 |
Test name | |
Test status | |
Simulation time | 167064543863 ps |
CPU time | 2888.9 seconds |
Started | Jul 11 06:10:24 PM PDT 24 |
Finished | Jul 11 06:58:37 PM PDT 24 |
Peak memory | 203480 kb |
Host | smart-f49ae0f9-84d2-4360-842e-86ca5032f114 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213970903 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection .3213970903 |
Directory | /workspace/25.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_executable.3745206981 |
Short name | T458 |
Test name | |
Test status | |
Simulation time | 18093015986 ps |
CPU time | 1172.07 seconds |
Started | Jul 11 06:04:08 PM PDT 24 |
Finished | Jul 11 06:23:49 PM PDT 24 |
Peak memory | 371560 kb |
Host | smart-8a0c7b5b-4974-4f35-99ad-a35ec949acbe |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745206981 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executab le.3745206981 |
Directory | /workspace/25.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_lc_escalation.3977065276 |
Short name | T762 |
Test name | |
Test status | |
Simulation time | 18275565240 ps |
CPU time | 28.58 seconds |
Started | Jul 11 06:04:08 PM PDT 24 |
Finished | Jul 11 06:04:46 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-c88e5f20-ab8a-43f0-a37f-05e8e75d9edc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977065276 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_es calation.3977065276 |
Directory | /workspace/25.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_max_throughput.1493003744 |
Short name | T197 |
Test name | |
Test status | |
Simulation time | 690306287 ps |
CPU time | 6.66 seconds |
Started | Jul 11 06:04:08 PM PDT 24 |
Finished | Jul 11 06:04:24 PM PDT 24 |
Peak memory | 214392 kb |
Host | smart-c0b04107-b6a2-4973-85af-5b7cd8bf87ed |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493003744 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 25.sram_ctrl_max_throughput.1493003744 |
Directory | /workspace/25.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_mem_partial_access.2045013852 |
Short name | T932 |
Test name | |
Test status | |
Simulation time | 9834752357 ps |
CPU time | 78.63 seconds |
Started | Jul 11 06:04:10 PM PDT 24 |
Finished | Jul 11 06:05:38 PM PDT 24 |
Peak memory | 211076 kb |
Host | smart-473c7f79-79dc-468f-aa95-1c49e721d90c |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045013852 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 5.sram_ctrl_mem_partial_access.2045013852 |
Directory | /workspace/25.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_mem_walk.2894111169 |
Short name | T541 |
Test name | |
Test status | |
Simulation time | 21879210026 ps |
CPU time | 308.05 seconds |
Started | Jul 11 06:04:09 PM PDT 24 |
Finished | Jul 11 06:09:26 PM PDT 24 |
Peak memory | 211044 kb |
Host | smart-b9465e5b-3d3d-448d-aec4-fa6aeaa6a77f |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894111169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctr l_mem_walk.2894111169 |
Directory | /workspace/25.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_multiple_keys.3003026453 |
Short name | T846 |
Test name | |
Test status | |
Simulation time | 63829179707 ps |
CPU time | 936.99 seconds |
Started | Jul 11 06:04:07 PM PDT 24 |
Finished | Jul 11 06:19:53 PM PDT 24 |
Peak memory | 375224 kb |
Host | smart-18a18858-4752-463c-80ee-1f28c09c3e33 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003026453 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multi ple_keys.3003026453 |
Directory | /workspace/25.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_partial_access.555967150 |
Short name | T941 |
Test name | |
Test status | |
Simulation time | 3235620992 ps |
CPU time | 44.45 seconds |
Started | Jul 11 06:04:11 PM PDT 24 |
Finished | Jul 11 06:05:04 PM PDT 24 |
Peak memory | 295864 kb |
Host | smart-a1e60f83-04d4-49e0-82d3-5f6e4d982ae3 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555967150 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.s ram_ctrl_partial_access.555967150 |
Directory | /workspace/25.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.1418975787 |
Short name | T350 |
Test name | |
Test status | |
Simulation time | 89300863583 ps |
CPU time | 271.84 seconds |
Started | Jul 11 06:04:03 PM PDT 24 |
Finished | Jul 11 06:08:44 PM PDT 24 |
Peak memory | 202976 kb |
Host | smart-3afd57c6-badf-4cb8-a082-b5e9c571f1a4 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418975787 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 25.sram_ctrl_partial_access_b2b.1418975787 |
Directory | /workspace/25.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_ram_cfg.4277342217 |
Short name | T407 |
Test name | |
Test status | |
Simulation time | 679969735 ps |
CPU time | 3.43 seconds |
Started | Jul 11 06:04:11 PM PDT 24 |
Finished | Jul 11 06:04:23 PM PDT 24 |
Peak memory | 202880 kb |
Host | smart-1ba796f4-019f-480f-a32d-e0499786dbdd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277342217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.4277342217 |
Directory | /workspace/25.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_regwen.2586653986 |
Short name | T624 |
Test name | |
Test status | |
Simulation time | 66002337968 ps |
CPU time | 1691.98 seconds |
Started | Jul 11 06:04:08 PM PDT 24 |
Finished | Jul 11 06:32:29 PM PDT 24 |
Peak memory | 377688 kb |
Host | smart-d90d362f-6548-43cf-b913-e73d7b6ba3a0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586653986 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.2586653986 |
Directory | /workspace/25.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_smoke.2230561524 |
Short name | T243 |
Test name | |
Test status | |
Simulation time | 581981039 ps |
CPU time | 24.26 seconds |
Started | Jul 11 06:04:13 PM PDT 24 |
Finished | Jul 11 06:04:45 PM PDT 24 |
Peak memory | 262768 kb |
Host | smart-e0c17706-898b-4629-9129-610875c50e43 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230561524 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.2230561524 |
Directory | /workspace/25.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_stress_all.292382532 |
Short name | T917 |
Test name | |
Test status | |
Simulation time | 142276044779 ps |
CPU time | 4000.13 seconds |
Started | Jul 11 06:04:10 PM PDT 24 |
Finished | Jul 11 07:10:59 PM PDT 24 |
Peak memory | 373808 kb |
Host | smart-4072bafd-aff9-4dab-9691-d7da1a66768f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292382532 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 25.sram_ctrl_stress_all.292382532 |
Directory | /workspace/25.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.2023634078 |
Short name | T866 |
Test name | |
Test status | |
Simulation time | 316678935 ps |
CPU time | 9.62 seconds |
Started | Jul 11 06:04:08 PM PDT 24 |
Finished | Jul 11 06:04:27 PM PDT 24 |
Peak memory | 211176 kb |
Host | smart-ea0385b4-70f0-4fdb-b026-5231c8489b67 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2023634078 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all_with_rand_reset.2023634078 |
Directory | /workspace/25.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_stress_pipeline.666212155 |
Short name | T888 |
Test name | |
Test status | |
Simulation time | 15768117853 ps |
CPU time | 199.49 seconds |
Started | Jul 11 06:04:07 PM PDT 24 |
Finished | Jul 11 06:07:35 PM PDT 24 |
Peak memory | 202772 kb |
Host | smart-b581be9a-c8b1-4567-900c-c8ded10925e4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666212155 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25 .sram_ctrl_stress_pipeline.666212155 |
Directory | /workspace/25.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.1713660724 |
Short name | T845 |
Test name | |
Test status | |
Simulation time | 1622624905 ps |
CPU time | 97.82 seconds |
Started | Jul 11 06:04:11 PM PDT 24 |
Finished | Jul 11 06:05:57 PM PDT 24 |
Peak memory | 361228 kb |
Host | smart-57c85bc8-4cae-47c8-a48c-b57fdf888d63 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713660724 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 25.sram_ctrl_throughput_w_partial_write.1713660724 |
Directory | /workspace/25.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_access_during_key_req.3655265486 |
Short name | T475 |
Test name | |
Test status | |
Simulation time | 9744441412 ps |
CPU time | 497.24 seconds |
Started | Jul 11 06:04:19 PM PDT 24 |
Finished | Jul 11 06:12:39 PM PDT 24 |
Peak memory | 358936 kb |
Host | smart-78209031-0096-4623-8390-102dab4cc6bc |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655265486 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 26.sram_ctrl_access_during_key_req.3655265486 |
Directory | /workspace/26.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_alert_test.2989466760 |
Short name | T127 |
Test name | |
Test status | |
Simulation time | 12226427 ps |
CPU time | 0.61 seconds |
Started | Jul 11 06:04:20 PM PDT 24 |
Finished | Jul 11 06:04:24 PM PDT 24 |
Peak memory | 202100 kb |
Host | smart-70a3f553-d8ab-4dc4-87fd-ea4e01ddd15d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989466760 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_alert_test.2989466760 |
Directory | /workspace/26.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_bijection.4174780431 |
Short name | T207 |
Test name | |
Test status | |
Simulation time | 200043748685 ps |
CPU time | 937.84 seconds |
Started | Jul 11 06:04:10 PM PDT 24 |
Finished | Jul 11 06:19:57 PM PDT 24 |
Peak memory | 203812 kb |
Host | smart-f4c0a2e8-034a-4c38-982f-328a5cb83857 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174780431 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection .4174780431 |
Directory | /workspace/26.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_executable.2244044196 |
Short name | T36 |
Test name | |
Test status | |
Simulation time | 15198481918 ps |
CPU time | 574.19 seconds |
Started | Jul 11 06:04:18 PM PDT 24 |
Finished | Jul 11 06:13:56 PM PDT 24 |
Peak memory | 373372 kb |
Host | smart-1a13097b-ef2c-4592-90b8-f05ad4d742c5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244044196 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executab le.2244044196 |
Directory | /workspace/26.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_lc_escalation.892240135 |
Short name | T926 |
Test name | |
Test status | |
Simulation time | 25353039688 ps |
CPU time | 45.72 seconds |
Started | Jul 11 06:04:09 PM PDT 24 |
Finished | Jul 11 06:05:03 PM PDT 24 |
Peak memory | 211040 kb |
Host | smart-76503d4b-b45d-4b29-a3d2-fb0eab626d84 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892240135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_esc alation.892240135 |
Directory | /workspace/26.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_max_throughput.1476924800 |
Short name | T862 |
Test name | |
Test status | |
Simulation time | 704465354 ps |
CPU time | 6.95 seconds |
Started | Jul 11 06:04:12 PM PDT 24 |
Finished | Jul 11 06:04:27 PM PDT 24 |
Peak memory | 216472 kb |
Host | smart-4420567e-e64c-4917-b3da-d0ffdcc60dd8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476924800 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 26.sram_ctrl_max_throughput.1476924800 |
Directory | /workspace/26.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_mem_partial_access.4171287732 |
Short name | T549 |
Test name | |
Test status | |
Simulation time | 2826444125 ps |
CPU time | 74.92 seconds |
Started | Jul 11 06:04:15 PM PDT 24 |
Finished | Jul 11 06:05:36 PM PDT 24 |
Peak memory | 211004 kb |
Host | smart-1710c32d-ed9f-4d15-8b2c-e7a141ae72ef |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171287732 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 6.sram_ctrl_mem_partial_access.4171287732 |
Directory | /workspace/26.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_mem_walk.3633943048 |
Short name | T552 |
Test name | |
Test status | |
Simulation time | 36964609312 ps |
CPU time | 346.11 seconds |
Started | Jul 11 06:04:18 PM PDT 24 |
Finished | Jul 11 06:10:08 PM PDT 24 |
Peak memory | 211044 kb |
Host | smart-27f941c6-a636-4396-b9f7-9125d84969b1 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633943048 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctr l_mem_walk.3633943048 |
Directory | /workspace/26.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_multiple_keys.3946552657 |
Short name | T323 |
Test name | |
Test status | |
Simulation time | 11747347437 ps |
CPU time | 470.4 seconds |
Started | Jul 11 06:04:10 PM PDT 24 |
Finished | Jul 11 06:12:09 PM PDT 24 |
Peak memory | 375608 kb |
Host | smart-2b7f151b-7099-48b9-8b87-c9f5134ff188 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946552657 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multi ple_keys.3946552657 |
Directory | /workspace/26.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_partial_access.218615726 |
Short name | T187 |
Test name | |
Test status | |
Simulation time | 987902225 ps |
CPU time | 7.58 seconds |
Started | Jul 11 06:04:16 PM PDT 24 |
Finished | Jul 11 06:04:29 PM PDT 24 |
Peak memory | 202720 kb |
Host | smart-31742166-c1f7-42bb-8401-55136f1cb92f |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218615726 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.s ram_ctrl_partial_access.218615726 |
Directory | /workspace/26.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.3081667175 |
Short name | T189 |
Test name | |
Test status | |
Simulation time | 16012491669 ps |
CPU time | 383.04 seconds |
Started | Jul 11 06:04:11 PM PDT 24 |
Finished | Jul 11 06:10:42 PM PDT 24 |
Peak memory | 202784 kb |
Host | smart-b9b8a0b6-1cc9-4c13-9792-5b5e58d72443 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081667175 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 26.sram_ctrl_partial_access_b2b.3081667175 |
Directory | /workspace/26.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_ram_cfg.1624118711 |
Short name | T859 |
Test name | |
Test status | |
Simulation time | 357973629 ps |
CPU time | 3.39 seconds |
Started | Jul 11 06:04:11 PM PDT 24 |
Finished | Jul 11 06:04:23 PM PDT 24 |
Peak memory | 202848 kb |
Host | smart-9fa29755-8ba6-4cab-af8f-b27cd54a7d94 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624118711 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.1624118711 |
Directory | /workspace/26.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_regwen.1840774290 |
Short name | T193 |
Test name | |
Test status | |
Simulation time | 10923545635 ps |
CPU time | 535.3 seconds |
Started | Jul 11 06:04:13 PM PDT 24 |
Finished | Jul 11 06:13:15 PM PDT 24 |
Peak memory | 378768 kb |
Host | smart-6fb7c6e9-5ef8-4fca-91cd-fedaaac27e5f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840774290 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.1840774290 |
Directory | /workspace/26.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_smoke.2811799745 |
Short name | T510 |
Test name | |
Test status | |
Simulation time | 1575111166 ps |
CPU time | 11.48 seconds |
Started | Jul 11 06:04:07 PM PDT 24 |
Finished | Jul 11 06:04:28 PM PDT 24 |
Peak memory | 237720 kb |
Host | smart-c883e326-a0f4-4a98-a4d8-c9bc17e05611 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811799745 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.2811799745 |
Directory | /workspace/26.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_stress_all.2621310686 |
Short name | T912 |
Test name | |
Test status | |
Simulation time | 49639245373 ps |
CPU time | 3501.52 seconds |
Started | Jul 11 06:04:14 PM PDT 24 |
Finished | Jul 11 07:02:42 PM PDT 24 |
Peak memory | 382828 kb |
Host | smart-6770ab1c-e6ef-4dc0-ae8c-5e6ff0f2713a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621310686 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 26.sram_ctrl_stress_all.2621310686 |
Directory | /workspace/26.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.3741767236 |
Short name | T126 |
Test name | |
Test status | |
Simulation time | 3344125527 ps |
CPU time | 25.59 seconds |
Started | Jul 11 06:04:18 PM PDT 24 |
Finished | Jul 11 06:04:48 PM PDT 24 |
Peak memory | 211216 kb |
Host | smart-8c47ff86-8262-4b90-8a1c-a325d3e04c0a |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3741767236 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all_with_rand_reset.3741767236 |
Directory | /workspace/26.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_stress_pipeline.2183561117 |
Short name | T757 |
Test name | |
Test status | |
Simulation time | 4557906618 ps |
CPU time | 241.77 seconds |
Started | Jul 11 06:04:15 PM PDT 24 |
Finished | Jul 11 06:08:23 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-d720ac9d-3ac6-45ba-82b7-e5cd9ee94676 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183561117 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 6.sram_ctrl_stress_pipeline.2183561117 |
Directory | /workspace/26.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.3164860050 |
Short name | T175 |
Test name | |
Test status | |
Simulation time | 3049226291 ps |
CPU time | 40 seconds |
Started | Jul 11 06:04:11 PM PDT 24 |
Finished | Jul 11 06:04:59 PM PDT 24 |
Peak memory | 294604 kb |
Host | smart-d59771dd-541b-42b4-b546-49c4a2a986d1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164860050 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 26.sram_ctrl_throughput_w_partial_write.3164860050 |
Directory | /workspace/26.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_access_during_key_req.3811883517 |
Short name | T470 |
Test name | |
Test status | |
Simulation time | 39721198605 ps |
CPU time | 775.82 seconds |
Started | Jul 11 06:04:18 PM PDT 24 |
Finished | Jul 11 06:17:18 PM PDT 24 |
Peak memory | 375684 kb |
Host | smart-7cbaa6f1-de07-48a8-881f-09fbc30bf1e6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811883517 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 27.sram_ctrl_access_during_key_req.3811883517 |
Directory | /workspace/27.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_alert_test.1065063062 |
Short name | T364 |
Test name | |
Test status | |
Simulation time | 13195555 ps |
CPU time | 0.65 seconds |
Started | Jul 11 06:04:19 PM PDT 24 |
Finished | Jul 11 06:04:23 PM PDT 24 |
Peak memory | 202440 kb |
Host | smart-d5383248-cdc9-422a-a72e-2d009b6ceb72 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065063062 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_alert_test.1065063062 |
Directory | /workspace/27.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_bijection.1032861671 |
Short name | T366 |
Test name | |
Test status | |
Simulation time | 150459727884 ps |
CPU time | 721.31 seconds |
Started | Jul 11 06:04:13 PM PDT 24 |
Finished | Jul 11 06:16:21 PM PDT 24 |
Peak memory | 203436 kb |
Host | smart-94623368-ec85-48c9-ab53-69a19488370f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032861671 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection .1032861671 |
Directory | /workspace/27.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_executable.1550851992 |
Short name | T532 |
Test name | |
Test status | |
Simulation time | 44171123768 ps |
CPU time | 1161.05 seconds |
Started | Jul 11 06:04:17 PM PDT 24 |
Finished | Jul 11 06:23:43 PM PDT 24 |
Peak memory | 370580 kb |
Host | smart-526aa73c-f38d-4a33-8ea0-07fe129c7a58 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550851992 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executab le.1550851992 |
Directory | /workspace/27.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_lc_escalation.1985000148 |
Short name | T336 |
Test name | |
Test status | |
Simulation time | 11266328378 ps |
CPU time | 66.62 seconds |
Started | Jul 11 06:04:18 PM PDT 24 |
Finished | Jul 11 06:05:29 PM PDT 24 |
Peak memory | 202880 kb |
Host | smart-b5fddbeb-fd64-4852-9b90-719baca858ac |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985000148 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_es calation.1985000148 |
Directory | /workspace/27.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_max_throughput.1795671945 |
Short name | T168 |
Test name | |
Test status | |
Simulation time | 736564911 ps |
CPU time | 45.55 seconds |
Started | Jul 11 06:04:13 PM PDT 24 |
Finished | Jul 11 06:05:06 PM PDT 24 |
Peak memory | 301056 kb |
Host | smart-27dd0459-33b3-483f-a60e-6b51b120edad |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795671945 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 27.sram_ctrl_max_throughput.1795671945 |
Directory | /workspace/27.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_mem_partial_access.484409872 |
Short name | T766 |
Test name | |
Test status | |
Simulation time | 4498469399 ps |
CPU time | 151.43 seconds |
Started | Jul 11 06:04:22 PM PDT 24 |
Finished | Jul 11 06:06:55 PM PDT 24 |
Peak memory | 211076 kb |
Host | smart-5d96853c-d8f7-4365-8541-7f24ed205a85 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484409872 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27 .sram_ctrl_mem_partial_access.484409872 |
Directory | /workspace/27.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_mem_walk.3899902913 |
Short name | T787 |
Test name | |
Test status | |
Simulation time | 57551822224 ps |
CPU time | 335.75 seconds |
Started | Jul 11 06:04:16 PM PDT 24 |
Finished | Jul 11 06:09:57 PM PDT 24 |
Peak memory | 211552 kb |
Host | smart-c4dba8be-f033-42de-add3-1b302dbc6851 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899902913 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctr l_mem_walk.3899902913 |
Directory | /workspace/27.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_multiple_keys.2403101482 |
Short name | T414 |
Test name | |
Test status | |
Simulation time | 12222359657 ps |
CPU time | 485.99 seconds |
Started | Jul 11 06:04:17 PM PDT 24 |
Finished | Jul 11 06:12:27 PM PDT 24 |
Peak memory | 376712 kb |
Host | smart-44b4858a-459a-47c1-8a89-7b7a442be832 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403101482 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multi ple_keys.2403101482 |
Directory | /workspace/27.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_partial_access.878148053 |
Short name | T225 |
Test name | |
Test status | |
Simulation time | 476271887 ps |
CPU time | 11.54 seconds |
Started | Jul 11 06:04:18 PM PDT 24 |
Finished | Jul 11 06:04:34 PM PDT 24 |
Peak memory | 202728 kb |
Host | smart-1a74baf9-a3a3-4823-9a26-de50450d7b09 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878148053 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.s ram_ctrl_partial_access.878148053 |
Directory | /workspace/27.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.3528738827 |
Short name | T360 |
Test name | |
Test status | |
Simulation time | 68703845939 ps |
CPU time | 420.22 seconds |
Started | Jul 11 06:04:14 PM PDT 24 |
Finished | Jul 11 06:11:21 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-052a759f-c9d7-4468-8f62-97c19826cab5 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528738827 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 27.sram_ctrl_partial_access_b2b.3528738827 |
Directory | /workspace/27.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_ram_cfg.2908821188 |
Short name | T732 |
Test name | |
Test status | |
Simulation time | 705869431 ps |
CPU time | 3.36 seconds |
Started | Jul 11 06:04:18 PM PDT 24 |
Finished | Jul 11 06:04:25 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-f79e4bf6-9908-4c1c-8d24-e11fc392caca |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908821188 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.2908821188 |
Directory | /workspace/27.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_regwen.1841169600 |
Short name | T20 |
Test name | |
Test status | |
Simulation time | 4729761510 ps |
CPU time | 2169.05 seconds |
Started | Jul 11 06:04:13 PM PDT 24 |
Finished | Jul 11 06:40:30 PM PDT 24 |
Peak memory | 379772 kb |
Host | smart-9373b9ab-ce38-4b20-aa8a-8aad8d5af926 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841169600 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.1841169600 |
Directory | /workspace/27.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_smoke.1710507863 |
Short name | T10 |
Test name | |
Test status | |
Simulation time | 2795773773 ps |
CPU time | 14.39 seconds |
Started | Jul 11 06:04:18 PM PDT 24 |
Finished | Jul 11 06:04:36 PM PDT 24 |
Peak memory | 202820 kb |
Host | smart-299d78b8-bdbd-4f73-8705-2cddb9b8d623 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710507863 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.1710507863 |
Directory | /workspace/27.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_stress_all.2783007800 |
Short name | T158 |
Test name | |
Test status | |
Simulation time | 125398711394 ps |
CPU time | 8508.37 seconds |
Started | Jul 11 06:04:21 PM PDT 24 |
Finished | Jul 11 08:26:13 PM PDT 24 |
Peak memory | 383848 kb |
Host | smart-e10de602-70b3-426d-a11f-5d95eaaada2b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783007800 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 27.sram_ctrl_stress_all.2783007800 |
Directory | /workspace/27.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.3562151086 |
Short name | T133 |
Test name | |
Test status | |
Simulation time | 568184483 ps |
CPU time | 20.07 seconds |
Started | Jul 11 06:04:19 PM PDT 24 |
Finished | Jul 11 06:04:43 PM PDT 24 |
Peak memory | 211084 kb |
Host | smart-a486393c-a46e-4dd3-a0f5-aeff306ca10d |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3562151086 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all_with_rand_reset.3562151086 |
Directory | /workspace/27.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_stress_pipeline.2487948425 |
Short name | T597 |
Test name | |
Test status | |
Simulation time | 3086047663 ps |
CPU time | 221.01 seconds |
Started | Jul 11 06:04:08 PM PDT 24 |
Finished | Jul 11 06:07:58 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-7858c930-9016-4592-8d19-bba94dfcf9d4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487948425 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 7.sram_ctrl_stress_pipeline.2487948425 |
Directory | /workspace/27.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.3095307590 |
Short name | T749 |
Test name | |
Test status | |
Simulation time | 2491862979 ps |
CPU time | 33.93 seconds |
Started | Jul 11 06:04:18 PM PDT 24 |
Finished | Jul 11 06:04:56 PM PDT 24 |
Peak memory | 281888 kb |
Host | smart-e00371ab-2bb2-4b24-ac76-69bf08e2bd87 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095307590 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 27.sram_ctrl_throughput_w_partial_write.3095307590 |
Directory | /workspace/27.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_access_during_key_req.4242880595 |
Short name | T755 |
Test name | |
Test status | |
Simulation time | 17208952527 ps |
CPU time | 974.97 seconds |
Started | Jul 11 06:04:19 PM PDT 24 |
Finished | Jul 11 06:20:37 PM PDT 24 |
Peak memory | 371644 kb |
Host | smart-927886c5-6ee3-4ab9-af24-4d19ef70c7fa |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242880595 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 28.sram_ctrl_access_during_key_req.4242880595 |
Directory | /workspace/28.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_alert_test.387733215 |
Short name | T640 |
Test name | |
Test status | |
Simulation time | 24473492 ps |
CPU time | 0.64 seconds |
Started | Jul 11 06:04:21 PM PDT 24 |
Finished | Jul 11 06:04:24 PM PDT 24 |
Peak memory | 202608 kb |
Host | smart-5102db31-4da8-4c27-a55d-4ab85388f1ef |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387733215 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_alert_test.387733215 |
Directory | /workspace/28.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_bijection.3734518804 |
Short name | T279 |
Test name | |
Test status | |
Simulation time | 110021905439 ps |
CPU time | 2088.71 seconds |
Started | Jul 11 06:04:18 PM PDT 24 |
Finished | Jul 11 06:39:11 PM PDT 24 |
Peak memory | 203728 kb |
Host | smart-ecdb2229-3c25-4662-bb19-8d07d3304ae2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734518804 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection .3734518804 |
Directory | /workspace/28.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_executable.2228267036 |
Short name | T681 |
Test name | |
Test status | |
Simulation time | 7713780268 ps |
CPU time | 817.65 seconds |
Started | Jul 11 06:04:24 PM PDT 24 |
Finished | Jul 11 06:18:03 PM PDT 24 |
Peak memory | 377692 kb |
Host | smart-12777ad3-6866-413d-b151-a1716223e45b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228267036 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executab le.2228267036 |
Directory | /workspace/28.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_lc_escalation.1877601570 |
Short name | T931 |
Test name | |
Test status | |
Simulation time | 27079601468 ps |
CPU time | 54.82 seconds |
Started | Jul 11 06:04:22 PM PDT 24 |
Finished | Jul 11 06:05:19 PM PDT 24 |
Peak memory | 202920 kb |
Host | smart-2d76fcc1-dc0d-4bc3-8ab8-76ef98337e8a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877601570 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_es calation.1877601570 |
Directory | /workspace/28.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_max_throughput.3093189878 |
Short name | T191 |
Test name | |
Test status | |
Simulation time | 799071633 ps |
CPU time | 125.91 seconds |
Started | Jul 11 06:04:19 PM PDT 24 |
Finished | Jul 11 06:06:28 PM PDT 24 |
Peak memory | 370388 kb |
Host | smart-41621c2a-5a97-4cbf-9edd-2f1fc511846b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093189878 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 28.sram_ctrl_max_throughput.3093189878 |
Directory | /workspace/28.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_mem_partial_access.4201638742 |
Short name | T828 |
Test name | |
Test status | |
Simulation time | 2048355028 ps |
CPU time | 65.97 seconds |
Started | Jul 11 06:04:23 PM PDT 24 |
Finished | Jul 11 06:05:31 PM PDT 24 |
Peak memory | 219012 kb |
Host | smart-9c7e2f9c-61a1-485f-8888-ca725ef892d2 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201638742 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 8.sram_ctrl_mem_partial_access.4201638742 |
Directory | /workspace/28.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_mem_walk.952243906 |
Short name | T55 |
Test name | |
Test status | |
Simulation time | 14730474924 ps |
CPU time | 159.19 seconds |
Started | Jul 11 06:04:26 PM PDT 24 |
Finished | Jul 11 06:07:06 PM PDT 24 |
Peak memory | 210960 kb |
Host | smart-19ab7b76-7376-43af-be6e-e8eedc23bfd6 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952243906 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl _mem_walk.952243906 |
Directory | /workspace/28.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_multiple_keys.1682037741 |
Short name | T563 |
Test name | |
Test status | |
Simulation time | 57760725862 ps |
CPU time | 968.51 seconds |
Started | Jul 11 06:04:17 PM PDT 24 |
Finished | Jul 11 06:20:30 PM PDT 24 |
Peak memory | 380752 kb |
Host | smart-61e25234-7f5a-4d04-8729-4ec65df3db97 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682037741 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multi ple_keys.1682037741 |
Directory | /workspace/28.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_partial_access.396498310 |
Short name | T526 |
Test name | |
Test status | |
Simulation time | 1961149381 ps |
CPU time | 61.45 seconds |
Started | Jul 11 06:04:19 PM PDT 24 |
Finished | Jul 11 06:05:24 PM PDT 24 |
Peak memory | 321312 kb |
Host | smart-a19b121b-0899-47ff-8acd-86532938e81a |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396498310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.s ram_ctrl_partial_access.396498310 |
Directory | /workspace/28.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.2047615372 |
Short name | T745 |
Test name | |
Test status | |
Simulation time | 55187121221 ps |
CPU time | 332.03 seconds |
Started | Jul 11 06:04:22 PM PDT 24 |
Finished | Jul 11 06:09:56 PM PDT 24 |
Peak memory | 202796 kb |
Host | smart-2b90cfe8-d6db-4e8a-85e8-e4da8df5a3a3 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047615372 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 28.sram_ctrl_partial_access_b2b.2047615372 |
Directory | /workspace/28.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_ram_cfg.3952493499 |
Short name | T27 |
Test name | |
Test status | |
Simulation time | 1352105703 ps |
CPU time | 3.51 seconds |
Started | Jul 11 06:04:26 PM PDT 24 |
Finished | Jul 11 06:04:30 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-5b15448d-e2ea-4235-a979-a3e2286df115 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952493499 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.3952493499 |
Directory | /workspace/28.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_regwen.3033803092 |
Short name | T392 |
Test name | |
Test status | |
Simulation time | 145847991920 ps |
CPU time | 626.23 seconds |
Started | Jul 11 06:04:23 PM PDT 24 |
Finished | Jul 11 06:14:52 PM PDT 24 |
Peak memory | 369548 kb |
Host | smart-d67c990a-a4e0-47ff-a163-ee033e06b24f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033803092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.3033803092 |
Directory | /workspace/28.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_smoke.1171883602 |
Short name | T324 |
Test name | |
Test status | |
Simulation time | 1884221582 ps |
CPU time | 7.42 seconds |
Started | Jul 11 06:04:16 PM PDT 24 |
Finished | Jul 11 06:04:29 PM PDT 24 |
Peak memory | 208100 kb |
Host | smart-cfb76df6-3e82-43e3-b97d-c145ce3d258a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171883602 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.1171883602 |
Directory | /workspace/28.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_stress_all.4183705305 |
Short name | T750 |
Test name | |
Test status | |
Simulation time | 94364578714 ps |
CPU time | 5051.39 seconds |
Started | Jul 11 06:04:21 PM PDT 24 |
Finished | Jul 11 07:28:35 PM PDT 24 |
Peak memory | 379800 kb |
Host | smart-650c1a46-f048-4b48-84a5-3cfbf1290357 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183705305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 28.sram_ctrl_stress_all.4183705305 |
Directory | /workspace/28.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.1066190641 |
Short name | T896 |
Test name | |
Test status | |
Simulation time | 634097342 ps |
CPU time | 12.69 seconds |
Started | Jul 11 06:04:24 PM PDT 24 |
Finished | Jul 11 06:04:39 PM PDT 24 |
Peak memory | 211076 kb |
Host | smart-dcc1c96d-58ec-4f61-a9b0-a5b774524bed |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1066190641 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all_with_rand_reset.1066190641 |
Directory | /workspace/28.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_stress_pipeline.3187914536 |
Short name | T291 |
Test name | |
Test status | |
Simulation time | 14335173007 ps |
CPU time | 233.15 seconds |
Started | Jul 11 06:04:14 PM PDT 24 |
Finished | Jul 11 06:08:14 PM PDT 24 |
Peak memory | 202876 kb |
Host | smart-ed737718-bdbb-47ae-9cc6-42d2dcc20a10 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187914536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 8.sram_ctrl_stress_pipeline.3187914536 |
Directory | /workspace/28.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.3009833520 |
Short name | T627 |
Test name | |
Test status | |
Simulation time | 3247651661 ps |
CPU time | 141.47 seconds |
Started | Jul 11 06:04:22 PM PDT 24 |
Finished | Jul 11 06:06:45 PM PDT 24 |
Peak memory | 367352 kb |
Host | smart-b58ad335-e131-4cc3-bdb2-929608174557 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009833520 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 28.sram_ctrl_throughput_w_partial_write.3009833520 |
Directory | /workspace/28.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_access_during_key_req.3704843458 |
Short name | T42 |
Test name | |
Test status | |
Simulation time | 5290081692 ps |
CPU time | 699.02 seconds |
Started | Jul 11 06:04:24 PM PDT 24 |
Finished | Jul 11 06:16:05 PM PDT 24 |
Peak memory | 376800 kb |
Host | smart-c9d5db2b-bede-436c-9507-399790163017 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704843458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 29.sram_ctrl_access_during_key_req.3704843458 |
Directory | /workspace/29.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_alert_test.1383832482 |
Short name | T233 |
Test name | |
Test status | |
Simulation time | 96796250 ps |
CPU time | 0.67 seconds |
Started | Jul 11 06:04:29 PM PDT 24 |
Finished | Jul 11 06:04:31 PM PDT 24 |
Peak memory | 202604 kb |
Host | smart-811e5fb7-3680-4e9f-9932-b4ce65b27f30 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383832482 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_alert_test.1383832482 |
Directory | /workspace/29.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_bijection.1863855818 |
Short name | T64 |
Test name | |
Test status | |
Simulation time | 138994789305 ps |
CPU time | 617.72 seconds |
Started | Jul 11 06:04:21 PM PDT 24 |
Finished | Jul 11 06:14:42 PM PDT 24 |
Peak memory | 203396 kb |
Host | smart-83bf2f61-0f26-4c83-b181-cda28361f148 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863855818 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection .1863855818 |
Directory | /workspace/29.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_executable.4255037143 |
Short name | T835 |
Test name | |
Test status | |
Simulation time | 5298713112 ps |
CPU time | 692.93 seconds |
Started | Jul 11 06:04:30 PM PDT 24 |
Finished | Jul 11 06:16:04 PM PDT 24 |
Peak memory | 380744 kb |
Host | smart-4e9a36a4-f5a9-46fd-ab64-8512a023be3e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255037143 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executab le.4255037143 |
Directory | /workspace/29.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_lc_escalation.2206636659 |
Short name | T497 |
Test name | |
Test status | |
Simulation time | 3227794421 ps |
CPU time | 10.24 seconds |
Started | Jul 11 06:04:28 PM PDT 24 |
Finished | Jul 11 06:04:40 PM PDT 24 |
Peak memory | 211144 kb |
Host | smart-735380cc-9457-4c0f-baa7-a54d05159f67 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206636659 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_es calation.2206636659 |
Directory | /workspace/29.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_max_throughput.21854376 |
Short name | T544 |
Test name | |
Test status | |
Simulation time | 2782747499 ps |
CPU time | 17.04 seconds |
Started | Jul 11 06:04:20 PM PDT 24 |
Finished | Jul 11 06:04:40 PM PDT 24 |
Peak memory | 252912 kb |
Host | smart-1de4d31b-06a8-4fee-8f36-f06e86872e3d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21854376 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 29.sram_ctrl_max_throughput.21854376 |
Directory | /workspace/29.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_mem_partial_access.1985649210 |
Short name | T727 |
Test name | |
Test status | |
Simulation time | 1925290960 ps |
CPU time | 119.13 seconds |
Started | Jul 11 06:04:27 PM PDT 24 |
Finished | Jul 11 06:06:28 PM PDT 24 |
Peak memory | 219228 kb |
Host | smart-8f69b986-2f00-4249-bcf9-08126b98d8e1 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985649210 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 9.sram_ctrl_mem_partial_access.1985649210 |
Directory | /workspace/29.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_mem_walk.604575912 |
Short name | T598 |
Test name | |
Test status | |
Simulation time | 7883681713 ps |
CPU time | 274.88 seconds |
Started | Jul 11 06:04:30 PM PDT 24 |
Finished | Jul 11 06:09:06 PM PDT 24 |
Peak memory | 212172 kb |
Host | smart-cc8ffb68-7409-48cb-8277-80329f9e5646 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604575912 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl _mem_walk.604575912 |
Directory | /workspace/29.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_multiple_keys.3231649639 |
Short name | T125 |
Test name | |
Test status | |
Simulation time | 17601713022 ps |
CPU time | 1167.63 seconds |
Started | Jul 11 06:04:22 PM PDT 24 |
Finished | Jul 11 06:23:52 PM PDT 24 |
Peak memory | 378684 kb |
Host | smart-aceacf84-9639-41df-8011-994919bcf005 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231649639 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multi ple_keys.3231649639 |
Directory | /workspace/29.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_partial_access.2843042818 |
Short name | T754 |
Test name | |
Test status | |
Simulation time | 967867639 ps |
CPU time | 11.82 seconds |
Started | Jul 11 06:04:24 PM PDT 24 |
Finished | Jul 11 06:04:37 PM PDT 24 |
Peak memory | 202756 kb |
Host | smart-5bdaff75-2e13-4831-bb6d-fcd10f67dc08 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843042818 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29. sram_ctrl_partial_access.2843042818 |
Directory | /workspace/29.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.3418562569 |
Short name | T212 |
Test name | |
Test status | |
Simulation time | 23271356547 ps |
CPU time | 276.98 seconds |
Started | Jul 11 06:04:22 PM PDT 24 |
Finished | Jul 11 06:09:01 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-05a5d5d9-3a67-4c6f-b9f3-aa5bbac8916c |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418562569 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 29.sram_ctrl_partial_access_b2b.3418562569 |
Directory | /workspace/29.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_ram_cfg.1832625994 |
Short name | T523 |
Test name | |
Test status | |
Simulation time | 1350991357 ps |
CPU time | 3.51 seconds |
Started | Jul 11 06:04:27 PM PDT 24 |
Finished | Jul 11 06:04:33 PM PDT 24 |
Peak memory | 203020 kb |
Host | smart-ea19e890-bd6e-481b-9818-4b65d3b8623c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832625994 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.1832625994 |
Directory | /workspace/29.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_regwen.165933497 |
Short name | T509 |
Test name | |
Test status | |
Simulation time | 5067152681 ps |
CPU time | 141.51 seconds |
Started | Jul 11 06:04:24 PM PDT 24 |
Finished | Jul 11 06:06:47 PM PDT 24 |
Peak memory | 362440 kb |
Host | smart-f5bb58eb-2ecb-4a53-8e50-1c5d6109ba43 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165933497 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.165933497 |
Directory | /workspace/29.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_smoke.923313912 |
Short name | T226 |
Test name | |
Test status | |
Simulation time | 760974490 ps |
CPU time | 17.85 seconds |
Started | Jul 11 06:04:21 PM PDT 24 |
Finished | Jul 11 06:04:41 PM PDT 24 |
Peak memory | 202784 kb |
Host | smart-b1116900-d7db-4fbb-ba10-2602d87b5f8b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923313912 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.923313912 |
Directory | /workspace/29.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.1009643723 |
Short name | T71 |
Test name | |
Test status | |
Simulation time | 10148816221 ps |
CPU time | 115.16 seconds |
Started | Jul 11 06:04:27 PM PDT 24 |
Finished | Jul 11 06:06:23 PM PDT 24 |
Peak memory | 338776 kb |
Host | smart-8f16585d-b6aa-4bf8-8138-e1044c016f60 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1009643723 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all_with_rand_reset.1009643723 |
Directory | /workspace/29.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_stress_pipeline.1911942771 |
Short name | T438 |
Test name | |
Test status | |
Simulation time | 2410992394 ps |
CPU time | 148.97 seconds |
Started | Jul 11 06:04:24 PM PDT 24 |
Finished | Jul 11 06:06:54 PM PDT 24 |
Peak memory | 202856 kb |
Host | smart-2c9d0343-8470-4246-bb99-435d91591949 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911942771 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 9.sram_ctrl_stress_pipeline.1911942771 |
Directory | /workspace/29.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.4023694601 |
Short name | T9 |
Test name | |
Test status | |
Simulation time | 2550942487 ps |
CPU time | 62.57 seconds |
Started | Jul 11 06:04:29 PM PDT 24 |
Finished | Jul 11 06:05:33 PM PDT 24 |
Peak memory | 309404 kb |
Host | smart-335736a0-99db-47de-a065-22433dac6e48 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023694601 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 29.sram_ctrl_throughput_w_partial_write.4023694601 |
Directory | /workspace/29.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_access_during_key_req.256846227 |
Short name | T376 |
Test name | |
Test status | |
Simulation time | 15490573749 ps |
CPU time | 1010.15 seconds |
Started | Jul 11 06:03:03 PM PDT 24 |
Finished | Jul 11 06:20:12 PM PDT 24 |
Peak memory | 379244 kb |
Host | smart-566525f2-6073-4ce9-a37a-ed56cd2be144 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256846227 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 3.sram_ctrl_access_during_key_req.256846227 |
Directory | /workspace/3.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_alert_test.2575472225 |
Short name | T897 |
Test name | |
Test status | |
Simulation time | 49560835 ps |
CPU time | 0.67 seconds |
Started | Jul 11 06:03:14 PM PDT 24 |
Finished | Jul 11 06:03:30 PM PDT 24 |
Peak memory | 202360 kb |
Host | smart-5e5e3a71-cf42-4a97-92e1-4eb7d3bcaabf |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575472225 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_alert_test.2575472225 |
Directory | /workspace/3.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_bijection.3083894109 |
Short name | T615 |
Test name | |
Test status | |
Simulation time | 10850793500 ps |
CPU time | 757.52 seconds |
Started | Jul 11 06:02:59 PM PDT 24 |
Finished | Jul 11 06:15:55 PM PDT 24 |
Peak memory | 203560 kb |
Host | smart-5b520c9a-2a30-475a-9252-936c447a945d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083894109 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection. 3083894109 |
Directory | /workspace/3.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_executable.4245049692 |
Short name | T654 |
Test name | |
Test status | |
Simulation time | 49442568232 ps |
CPU time | 1847.52 seconds |
Started | Jul 11 06:03:03 PM PDT 24 |
Finished | Jul 11 06:34:09 PM PDT 24 |
Peak memory | 378772 kb |
Host | smart-846a5d12-5199-452f-9daa-6de225dffff1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245049692 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executabl e.4245049692 |
Directory | /workspace/3.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_lc_escalation.738694722 |
Short name | T665 |
Test name | |
Test status | |
Simulation time | 8115345405 ps |
CPU time | 45.54 seconds |
Started | Jul 11 06:03:04 PM PDT 24 |
Finished | Jul 11 06:04:08 PM PDT 24 |
Peak memory | 211132 kb |
Host | smart-a123c98f-2183-4551-9fb8-e8b07d629ab3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738694722 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_esca lation.738694722 |
Directory | /workspace/3.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_max_throughput.3210864600 |
Short name | T841 |
Test name | |
Test status | |
Simulation time | 785825119 ps |
CPU time | 43.34 seconds |
Started | Jul 11 06:03:00 PM PDT 24 |
Finished | Jul 11 06:04:03 PM PDT 24 |
Peak memory | 315508 kb |
Host | smart-a6916f05-98c1-4186-a70a-5c2a3e58d22f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210864600 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 3.sram_ctrl_max_throughput.3210864600 |
Directory | /workspace/3.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_mem_partial_access.738737567 |
Short name | T411 |
Test name | |
Test status | |
Simulation time | 5709288995 ps |
CPU time | 73.59 seconds |
Started | Jul 11 06:03:07 PM PDT 24 |
Finished | Jul 11 06:04:38 PM PDT 24 |
Peak memory | 211072 kb |
Host | smart-d0add08a-230d-43ab-a589-356cbfc806d5 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738737567 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3. sram_ctrl_mem_partial_access.738737567 |
Directory | /workspace/3.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_mem_walk.46717292 |
Short name | T331 |
Test name | |
Test status | |
Simulation time | 14136350871 ps |
CPU time | 165.63 seconds |
Started | Jul 11 06:03:07 PM PDT 24 |
Finished | Jul 11 06:06:09 PM PDT 24 |
Peak memory | 210988 kb |
Host | smart-21b354ef-03c0-4bef-ad6c-fe2194bd668c |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46717292 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sr am_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_m em_walk.46717292 |
Directory | /workspace/3.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_multiple_keys.872080012 |
Short name | T568 |
Test name | |
Test status | |
Simulation time | 5562533814 ps |
CPU time | 567 seconds |
Started | Jul 11 06:02:58 PM PDT 24 |
Finished | Jul 11 06:12:44 PM PDT 24 |
Peak memory | 363340 kb |
Host | smart-13845c0f-4c46-4499-9659-5a6cb4ddc3e7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872080012 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multipl e_keys.872080012 |
Directory | /workspace/3.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_partial_access.3593369278 |
Short name | T646 |
Test name | |
Test status | |
Simulation time | 529718112 ps |
CPU time | 137.15 seconds |
Started | Jul 11 06:02:59 PM PDT 24 |
Finished | Jul 11 06:05:35 PM PDT 24 |
Peak memory | 369344 kb |
Host | smart-4f199243-3e47-47e9-852d-11b7e8ac0721 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593369278 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.s ram_ctrl_partial_access.3593369278 |
Directory | /workspace/3.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.31673621 |
Short name | T942 |
Test name | |
Test status | |
Simulation time | 30707901182 ps |
CPU time | 388.92 seconds |
Started | Jul 11 06:03:17 PM PDT 24 |
Finished | Jul 11 06:10:01 PM PDT 24 |
Peak memory | 202924 kb |
Host | smart-d3be660f-1f4c-42f5-96fc-44125234f7e4 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31673621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 3.sram_ctrl_partial_access_b2b.31673621 |
Directory | /workspace/3.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_ram_cfg.906493231 |
Short name | T829 |
Test name | |
Test status | |
Simulation time | 1412317441 ps |
CPU time | 3.68 seconds |
Started | Jul 11 06:03:11 PM PDT 24 |
Finished | Jul 11 06:03:30 PM PDT 24 |
Peak memory | 202692 kb |
Host | smart-0f5b37f3-602e-4f5c-86c8-6719585796a4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906493231 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.906493231 |
Directory | /workspace/3.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_regwen.3552781660 |
Short name | T394 |
Test name | |
Test status | |
Simulation time | 93049660516 ps |
CPU time | 406.79 seconds |
Started | Jul 11 06:03:01 PM PDT 24 |
Finished | Jul 11 06:10:06 PM PDT 24 |
Peak memory | 364764 kb |
Host | smart-16d3490f-72d5-4fae-985b-9fc88e2ec5d6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552781660 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.3552781660 |
Directory | /workspace/3.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_sec_cm.4141486801 |
Short name | T17 |
Test name | |
Test status | |
Simulation time | 1389661595 ps |
CPU time | 3.53 seconds |
Started | Jul 11 06:03:02 PM PDT 24 |
Finished | Jul 11 06:03:24 PM PDT 24 |
Peak memory | 222320 kb |
Host | smart-71b743a0-9d12-4f5b-a550-9724a3d73821 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141486801 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_sec_cm.4141486801 |
Directory | /workspace/3.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_smoke.990333194 |
Short name | T267 |
Test name | |
Test status | |
Simulation time | 2801882168 ps |
CPU time | 10.12 seconds |
Started | Jul 11 06:03:04 PM PDT 24 |
Finished | Jul 11 06:03:32 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-2dd77b4b-21f6-4314-9bad-d1e45bc0f2d6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990333194 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.990333194 |
Directory | /workspace/3.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_stress_all.3743476367 |
Short name | T21 |
Test name | |
Test status | |
Simulation time | 26925844318 ps |
CPU time | 1267.37 seconds |
Started | Jul 11 06:03:03 PM PDT 24 |
Finished | Jul 11 06:24:29 PM PDT 24 |
Peak memory | 376692 kb |
Host | smart-e45f7f3d-aebe-4b9d-a996-9a148a0504d5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743476367 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 3.sram_ctrl_stress_all.3743476367 |
Directory | /workspace/3.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.3503093874 |
Short name | T490 |
Test name | |
Test status | |
Simulation time | 1271335957 ps |
CPU time | 69.45 seconds |
Started | Jul 11 06:03:00 PM PDT 24 |
Finished | Jul 11 06:04:28 PM PDT 24 |
Peak memory | 211080 kb |
Host | smart-0a12d3a7-50e4-417a-bb1f-756f965a1526 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3503093874 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all_with_rand_reset.3503093874 |
Directory | /workspace/3.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_stress_pipeline.2210673798 |
Short name | T252 |
Test name | |
Test status | |
Simulation time | 4955232838 ps |
CPU time | 309.9 seconds |
Started | Jul 11 06:03:33 PM PDT 24 |
Finished | Jul 11 06:08:54 PM PDT 24 |
Peak memory | 202820 kb |
Host | smart-5788d34b-4a41-41f4-b89e-944d579907c0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210673798 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 .sram_ctrl_stress_pipeline.2210673798 |
Directory | /workspace/3.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.3467748382 |
Short name | T673 |
Test name | |
Test status | |
Simulation time | 1531837861 ps |
CPU time | 40.42 seconds |
Started | Jul 11 06:02:59 PM PDT 24 |
Finished | Jul 11 06:03:58 PM PDT 24 |
Peak memory | 293696 kb |
Host | smart-656570a7-08c9-4548-b74c-967cb011f683 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467748382 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 3.sram_ctrl_throughput_w_partial_write.3467748382 |
Directory | /workspace/3.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_access_during_key_req.3479059788 |
Short name | T818 |
Test name | |
Test status | |
Simulation time | 9141242880 ps |
CPU time | 928.05 seconds |
Started | Jul 11 06:04:33 PM PDT 24 |
Finished | Jul 11 06:20:03 PM PDT 24 |
Peak memory | 377748 kb |
Host | smart-f52864c3-62c4-43c0-a0a0-1bd00be0464a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479059788 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 30.sram_ctrl_access_during_key_req.3479059788 |
Directory | /workspace/30.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_alert_test.494182965 |
Short name | T14 |
Test name | |
Test status | |
Simulation time | 32628674 ps |
CPU time | 0.64 seconds |
Started | Jul 11 06:04:31 PM PDT 24 |
Finished | Jul 11 06:04:33 PM PDT 24 |
Peak memory | 202372 kb |
Host | smart-795eea34-9562-4a72-9b95-44fadbb31beb |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494182965 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_alert_test.494182965 |
Directory | /workspace/30.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_bijection.2405607272 |
Short name | T461 |
Test name | |
Test status | |
Simulation time | 32792091072 ps |
CPU time | 1051.65 seconds |
Started | Jul 11 06:04:33 PM PDT 24 |
Finished | Jul 11 06:22:07 PM PDT 24 |
Peak memory | 203424 kb |
Host | smart-6e6239b5-54ce-4585-9311-585d0e9d6f48 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405607272 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection .2405607272 |
Directory | /workspace/30.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_executable.2091982039 |
Short name | T308 |
Test name | |
Test status | |
Simulation time | 38973151695 ps |
CPU time | 1138.61 seconds |
Started | Jul 11 06:04:33 PM PDT 24 |
Finished | Jul 11 06:23:34 PM PDT 24 |
Peak memory | 379812 kb |
Host | smart-387eeaa8-2253-4af0-bf84-9b7457431d01 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091982039 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executab le.2091982039 |
Directory | /workspace/30.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_lc_escalation.3755771879 |
Short name | T892 |
Test name | |
Test status | |
Simulation time | 26933358056 ps |
CPU time | 48.09 seconds |
Started | Jul 11 06:04:30 PM PDT 24 |
Finished | Jul 11 06:05:19 PM PDT 24 |
Peak memory | 211220 kb |
Host | smart-b1626013-a3a2-409d-82a2-e2f0bd945683 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755771879 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_es calation.3755771879 |
Directory | /workspace/30.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_max_throughput.2428728922 |
Short name | T530 |
Test name | |
Test status | |
Simulation time | 761406618 ps |
CPU time | 48.69 seconds |
Started | Jul 11 06:04:35 PM PDT 24 |
Finished | Jul 11 06:05:25 PM PDT 24 |
Peak memory | 291000 kb |
Host | smart-f8208076-c06e-42fc-9fb3-22cf1e95c862 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428728922 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 30.sram_ctrl_max_throughput.2428728922 |
Directory | /workspace/30.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_mem_partial_access.3039818406 |
Short name | T881 |
Test name | |
Test status | |
Simulation time | 6112111472 ps |
CPU time | 132.68 seconds |
Started | Jul 11 06:04:31 PM PDT 24 |
Finished | Jul 11 06:06:45 PM PDT 24 |
Peak memory | 211236 kb |
Host | smart-122df35a-f964-4b39-a355-57f3d53ee0eb |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039818406 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 0.sram_ctrl_mem_partial_access.3039818406 |
Directory | /workspace/30.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_mem_walk.3080335393 |
Short name | T200 |
Test name | |
Test status | |
Simulation time | 17506886102 ps |
CPU time | 298.05 seconds |
Started | Jul 11 06:04:32 PM PDT 24 |
Finished | Jul 11 06:09:32 PM PDT 24 |
Peak memory | 210980 kb |
Host | smart-0d90b299-8087-40e1-ad15-84ec91759a21 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080335393 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctr l_mem_walk.3080335393 |
Directory | /workspace/30.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_multiple_keys.3535125830 |
Short name | T397 |
Test name | |
Test status | |
Simulation time | 13810123358 ps |
CPU time | 851.13 seconds |
Started | Jul 11 06:04:30 PM PDT 24 |
Finished | Jul 11 06:18:42 PM PDT 24 |
Peak memory | 377688 kb |
Host | smart-a721752e-32bd-449f-b9e1-80a721076496 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535125830 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multi ple_keys.3535125830 |
Directory | /workspace/30.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_partial_access.2062447097 |
Short name | T179 |
Test name | |
Test status | |
Simulation time | 3832227953 ps |
CPU time | 14.86 seconds |
Started | Jul 11 06:04:32 PM PDT 24 |
Finished | Jul 11 06:04:49 PM PDT 24 |
Peak memory | 202856 kb |
Host | smart-a39637c1-5b45-405f-b166-be01cea714ee |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062447097 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30. sram_ctrl_partial_access.2062447097 |
Directory | /workspace/30.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.3206218459 |
Short name | T790 |
Test name | |
Test status | |
Simulation time | 8032042601 ps |
CPU time | 212.1 seconds |
Started | Jul 11 06:04:32 PM PDT 24 |
Finished | Jul 11 06:08:06 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-35fd1ca8-89ea-4d3b-a815-cf6c8e2fabc8 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206218459 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 30.sram_ctrl_partial_access_b2b.3206218459 |
Directory | /workspace/30.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_ram_cfg.4025275837 |
Short name | T209 |
Test name | |
Test status | |
Simulation time | 1351680687 ps |
CPU time | 3.57 seconds |
Started | Jul 11 06:04:34 PM PDT 24 |
Finished | Jul 11 06:04:40 PM PDT 24 |
Peak memory | 202916 kb |
Host | smart-5bad9696-df48-40ad-828f-59d76015535c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025275837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.4025275837 |
Directory | /workspace/30.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_regwen.4150507015 |
Short name | T928 |
Test name | |
Test status | |
Simulation time | 15044320083 ps |
CPU time | 1202.12 seconds |
Started | Jul 11 06:04:34 PM PDT 24 |
Finished | Jul 11 06:24:39 PM PDT 24 |
Peak memory | 375728 kb |
Host | smart-c6b4825d-d890-4788-861b-0d89af65f4bf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150507015 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.4150507015 |
Directory | /workspace/30.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_smoke.3394339171 |
Short name | T891 |
Test name | |
Test status | |
Simulation time | 1326748594 ps |
CPU time | 7.39 seconds |
Started | Jul 11 06:04:28 PM PDT 24 |
Finished | Jul 11 06:04:37 PM PDT 24 |
Peak memory | 208380 kb |
Host | smart-b806412c-ea73-43d1-958c-968d0ebf2d5c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394339171 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.3394339171 |
Directory | /workspace/30.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_stress_all.551722080 |
Short name | T492 |
Test name | |
Test status | |
Simulation time | 295448431197 ps |
CPU time | 6208.74 seconds |
Started | Jul 11 06:04:32 PM PDT 24 |
Finished | Jul 11 07:48:04 PM PDT 24 |
Peak memory | 377744 kb |
Host | smart-bc8aaad0-361c-46fb-badb-ef68fe4cfb3a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551722080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 30.sram_ctrl_stress_all.551722080 |
Directory | /workspace/30.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.166749214 |
Short name | T883 |
Test name | |
Test status | |
Simulation time | 1792042757 ps |
CPU time | 15.23 seconds |
Started | Jul 11 06:04:34 PM PDT 24 |
Finished | Jul 11 06:04:51 PM PDT 24 |
Peak memory | 211064 kb |
Host | smart-6005c5f7-29d5-41df-83f1-05556d34b81d |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=166749214 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all_with_rand_reset.166749214 |
Directory | /workspace/30.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.1164937278 |
Short name | T641 |
Test name | |
Test status | |
Simulation time | 7441942326 ps |
CPU time | 61.34 seconds |
Started | Jul 11 06:04:32 PM PDT 24 |
Finished | Jul 11 06:05:36 PM PDT 24 |
Peak memory | 318332 kb |
Host | smart-f60085cd-8866-4143-9721-f0ecf1b6c503 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164937278 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 30.sram_ctrl_throughput_w_partial_write.1164937278 |
Directory | /workspace/30.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_access_during_key_req.3253369520 |
Short name | T801 |
Test name | |
Test status | |
Simulation time | 28800272898 ps |
CPU time | 769.08 seconds |
Started | Jul 11 06:04:39 PM PDT 24 |
Finished | Jul 11 06:17:30 PM PDT 24 |
Peak memory | 374268 kb |
Host | smart-9f2db76a-b29f-443b-b6c8-af5930b0b414 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253369520 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 31.sram_ctrl_access_during_key_req.3253369520 |
Directory | /workspace/31.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_alert_test.4163582148 |
Short name | T399 |
Test name | |
Test status | |
Simulation time | 29551189 ps |
CPU time | 0.67 seconds |
Started | Jul 11 06:04:37 PM PDT 24 |
Finished | Jul 11 06:04:40 PM PDT 24 |
Peak memory | 202616 kb |
Host | smart-00c2a288-e0b9-4441-a903-459ac3df0a3d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163582148 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_alert_test.4163582148 |
Directory | /workspace/31.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_bijection.3122769536 |
Short name | T605 |
Test name | |
Test status | |
Simulation time | 159914250766 ps |
CPU time | 1873.87 seconds |
Started | Jul 11 06:04:35 PM PDT 24 |
Finished | Jul 11 06:35:51 PM PDT 24 |
Peak memory | 203448 kb |
Host | smart-27d2dbaa-602d-4125-84c2-c4163f401dbc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122769536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection .3122769536 |
Directory | /workspace/31.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_executable.3002074165 |
Short name | T580 |
Test name | |
Test status | |
Simulation time | 3091958646 ps |
CPU time | 81.47 seconds |
Started | Jul 11 06:04:36 PM PDT 24 |
Finished | Jul 11 06:05:59 PM PDT 24 |
Peak memory | 327820 kb |
Host | smart-bfbb7ef0-e275-4d99-aa0a-c100b04c890e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002074165 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executab le.3002074165 |
Directory | /workspace/31.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_lc_escalation.1731914410 |
Short name | T276 |
Test name | |
Test status | |
Simulation time | 20644928241 ps |
CPU time | 70.55 seconds |
Started | Jul 11 06:04:37 PM PDT 24 |
Finished | Jul 11 06:05:49 PM PDT 24 |
Peak memory | 215636 kb |
Host | smart-5558cbbb-2d8d-444b-a75a-ee5be018fb4d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731914410 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_es calation.1731914410 |
Directory | /workspace/31.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_max_throughput.717441730 |
Short name | T188 |
Test name | |
Test status | |
Simulation time | 3251746879 ps |
CPU time | 42.97 seconds |
Started | Jul 11 06:04:39 PM PDT 24 |
Finished | Jul 11 06:05:24 PM PDT 24 |
Peak memory | 286652 kb |
Host | smart-66e5d687-c54f-401b-a4bc-ca6849c78965 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717441730 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 31.sram_ctrl_max_throughput.717441730 |
Directory | /workspace/31.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_mem_partial_access.241268107 |
Short name | T693 |
Test name | |
Test status | |
Simulation time | 4529468332 ps |
CPU time | 161.3 seconds |
Started | Jul 11 06:04:36 PM PDT 24 |
Finished | Jul 11 06:07:19 PM PDT 24 |
Peak memory | 219240 kb |
Host | smart-d3bc51c0-6e5c-4d0c-8452-93f52fb7c95f |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241268107 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31 .sram_ctrl_mem_partial_access.241268107 |
Directory | /workspace/31.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_mem_walk.4138109924 |
Short name | T746 |
Test name | |
Test status | |
Simulation time | 10884234540 ps |
CPU time | 175.7 seconds |
Started | Jul 11 06:04:38 PM PDT 24 |
Finished | Jul 11 06:07:35 PM PDT 24 |
Peak memory | 210976 kb |
Host | smart-8772bbd0-fa55-4d7f-a32b-52df2b88fc5f |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138109924 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctr l_mem_walk.4138109924 |
Directory | /workspace/31.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_multiple_keys.2246711811 |
Short name | T486 |
Test name | |
Test status | |
Simulation time | 25757736584 ps |
CPU time | 617.3 seconds |
Started | Jul 11 06:04:33 PM PDT 24 |
Finished | Jul 11 06:14:52 PM PDT 24 |
Peak memory | 375764 kb |
Host | smart-dad42068-3085-4850-9e3c-888a5e3f849d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246711811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multi ple_keys.2246711811 |
Directory | /workspace/31.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_partial_access.3727644885 |
Short name | T192 |
Test name | |
Test status | |
Simulation time | 3388888043 ps |
CPU time | 109.31 seconds |
Started | Jul 11 06:04:38 PM PDT 24 |
Finished | Jul 11 06:06:29 PM PDT 24 |
Peak memory | 360232 kb |
Host | smart-fc1daef3-00ad-4866-a924-3de7d4d468a3 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727644885 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31. sram_ctrl_partial_access.3727644885 |
Directory | /workspace/31.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.1939534429 |
Short name | T227 |
Test name | |
Test status | |
Simulation time | 62455977000 ps |
CPU time | 354.38 seconds |
Started | Jul 11 06:04:37 PM PDT 24 |
Finished | Jul 11 06:10:33 PM PDT 24 |
Peak memory | 202904 kb |
Host | smart-1d4443af-be82-4c64-b8e2-28415cc5e31c |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939534429 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 31.sram_ctrl_partial_access_b2b.1939534429 |
Directory | /workspace/31.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_ram_cfg.4203184124 |
Short name | T581 |
Test name | |
Test status | |
Simulation time | 1245712792 ps |
CPU time | 3.64 seconds |
Started | Jul 11 06:04:39 PM PDT 24 |
Finished | Jul 11 06:04:45 PM PDT 24 |
Peak memory | 202868 kb |
Host | smart-67ef96a7-c4bb-4def-b364-a2faed1bdd15 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203184124 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.4203184124 |
Directory | /workspace/31.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_regwen.1039734080 |
Short name | T442 |
Test name | |
Test status | |
Simulation time | 31818773308 ps |
CPU time | 574.76 seconds |
Started | Jul 11 06:04:41 PM PDT 24 |
Finished | Jul 11 06:14:17 PM PDT 24 |
Peak memory | 365356 kb |
Host | smart-4fea2ba1-06e2-4562-baa7-e214a19c5b45 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039734080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.1039734080 |
Directory | /workspace/31.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_smoke.2090147911 |
Short name | T327 |
Test name | |
Test status | |
Simulation time | 584235291 ps |
CPU time | 7.16 seconds |
Started | Jul 11 06:04:36 PM PDT 24 |
Finished | Jul 11 06:04:45 PM PDT 24 |
Peak memory | 202760 kb |
Host | smart-2302d18f-6772-47cb-8145-de9bc358ace2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090147911 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.2090147911 |
Directory | /workspace/31.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_stress_all.3752856576 |
Short name | T210 |
Test name | |
Test status | |
Simulation time | 123342484315 ps |
CPU time | 2693.32 seconds |
Started | Jul 11 06:04:39 PM PDT 24 |
Finished | Jul 11 06:49:34 PM PDT 24 |
Peak memory | 325612 kb |
Host | smart-e5f4c776-8138-41fc-8fb5-142249a7d436 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752856576 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 31.sram_ctrl_stress_all.3752856576 |
Directory | /workspace/31.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.2266985676 |
Short name | T70 |
Test name | |
Test status | |
Simulation time | 5181724821 ps |
CPU time | 46.82 seconds |
Started | Jul 11 06:04:43 PM PDT 24 |
Finished | Jul 11 06:05:32 PM PDT 24 |
Peak memory | 278680 kb |
Host | smart-13065e0d-0577-4702-ad18-2e46be6ae717 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2266985676 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all_with_rand_reset.2266985676 |
Directory | /workspace/31.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_stress_pipeline.2713774796 |
Short name | T496 |
Test name | |
Test status | |
Simulation time | 18185578972 ps |
CPU time | 310.46 seconds |
Started | Jul 11 06:04:32 PM PDT 24 |
Finished | Jul 11 06:09:44 PM PDT 24 |
Peak memory | 202852 kb |
Host | smart-8fa01d89-ba7e-4faa-b510-62598e9434f7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713774796 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 1.sram_ctrl_stress_pipeline.2713774796 |
Directory | /workspace/31.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.175347231 |
Short name | T694 |
Test name | |
Test status | |
Simulation time | 1413831661 ps |
CPU time | 5.7 seconds |
Started | Jul 11 06:04:36 PM PDT 24 |
Finished | Jul 11 06:04:44 PM PDT 24 |
Peak memory | 210872 kb |
Host | smart-70b1e190-7df9-442f-9840-66b17b9458e6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175347231 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 31.sram_ctrl_throughput_w_partial_write.175347231 |
Directory | /workspace/31.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_access_during_key_req.3822671378 |
Short name | T128 |
Test name | |
Test status | |
Simulation time | 35972457416 ps |
CPU time | 604.4 seconds |
Started | Jul 11 06:04:41 PM PDT 24 |
Finished | Jul 11 06:14:47 PM PDT 24 |
Peak memory | 373608 kb |
Host | smart-fd2818a5-ec68-4d09-b45b-fb689187ecb9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822671378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 32.sram_ctrl_access_during_key_req.3822671378 |
Directory | /workspace/32.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_alert_test.3159355779 |
Short name | T255 |
Test name | |
Test status | |
Simulation time | 72592592 ps |
CPU time | 0.63 seconds |
Started | Jul 11 06:04:45 PM PDT 24 |
Finished | Jul 11 06:04:50 PM PDT 24 |
Peak memory | 202368 kb |
Host | smart-30fd1a66-0892-4f40-a0f3-31af72bb0cfc |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159355779 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_alert_test.3159355779 |
Directory | /workspace/32.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_bijection.4084699523 |
Short name | T758 |
Test name | |
Test status | |
Simulation time | 628398234366 ps |
CPU time | 1359.28 seconds |
Started | Jul 11 06:04:38 PM PDT 24 |
Finished | Jul 11 06:27:20 PM PDT 24 |
Peak memory | 203088 kb |
Host | smart-e8a2280e-58c2-4796-b899-173594e4203c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084699523 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection .4084699523 |
Directory | /workspace/32.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_executable.3083370879 |
Short name | T371 |
Test name | |
Test status | |
Simulation time | 23338568335 ps |
CPU time | 271.55 seconds |
Started | Jul 11 06:04:43 PM PDT 24 |
Finished | Jul 11 06:09:18 PM PDT 24 |
Peak memory | 375988 kb |
Host | smart-afc6cdbe-b9b7-4185-adac-52bbea064e4a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083370879 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executab le.3083370879 |
Directory | /workspace/32.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_lc_escalation.4265967503 |
Short name | T692 |
Test name | |
Test status | |
Simulation time | 11618514224 ps |
CPU time | 37.57 seconds |
Started | Jul 11 06:04:43 PM PDT 24 |
Finished | Jul 11 06:05:24 PM PDT 24 |
Peak memory | 202904 kb |
Host | smart-6784123b-2c0e-427d-89ac-ee659bc46789 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265967503 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_es calation.4265967503 |
Directory | /workspace/32.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_max_throughput.1415351448 |
Short name | T393 |
Test name | |
Test status | |
Simulation time | 1393822048 ps |
CPU time | 6.76 seconds |
Started | Jul 11 06:04:42 PM PDT 24 |
Finished | Jul 11 06:04:51 PM PDT 24 |
Peak memory | 210968 kb |
Host | smart-557021eb-f44e-4d69-8822-e9e003b40681 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415351448 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 32.sram_ctrl_max_throughput.1415351448 |
Directory | /workspace/32.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_mem_partial_access.2699120940 |
Short name | T547 |
Test name | |
Test status | |
Simulation time | 2705610725 ps |
CPU time | 90.12 seconds |
Started | Jul 11 06:04:48 PM PDT 24 |
Finished | Jul 11 06:06:21 PM PDT 24 |
Peak memory | 211012 kb |
Host | smart-db679a9d-8ee2-4538-8a3e-5bf0a0e89a2d |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699120940 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 2.sram_ctrl_mem_partial_access.2699120940 |
Directory | /workspace/32.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_mem_walk.3891483472 |
Short name | T566 |
Test name | |
Test status | |
Simulation time | 21010041140 ps |
CPU time | 316.96 seconds |
Started | Jul 11 06:04:41 PM PDT 24 |
Finished | Jul 11 06:10:00 PM PDT 24 |
Peak memory | 211044 kb |
Host | smart-54979c17-ec3d-4d2a-ba76-230408311656 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891483472 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctr l_mem_walk.3891483472 |
Directory | /workspace/32.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_multiple_keys.2767027520 |
Short name | T657 |
Test name | |
Test status | |
Simulation time | 46618341315 ps |
CPU time | 1364 seconds |
Started | Jul 11 06:04:40 PM PDT 24 |
Finished | Jul 11 06:27:26 PM PDT 24 |
Peak memory | 379816 kb |
Host | smart-a9677a9a-d8c5-4232-abc4-77b513e72a8d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767027520 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multi ple_keys.2767027520 |
Directory | /workspace/32.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_partial_access.4288080406 |
Short name | T804 |
Test name | |
Test status | |
Simulation time | 1905457599 ps |
CPU time | 28.55 seconds |
Started | Jul 11 06:04:43 PM PDT 24 |
Finished | Jul 11 06:05:14 PM PDT 24 |
Peak memory | 259708 kb |
Host | smart-70f45cdb-e850-4331-b4fd-74548af18f80 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288080406 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32. sram_ctrl_partial_access.4288080406 |
Directory | /workspace/32.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.3981061230 |
Short name | T918 |
Test name | |
Test status | |
Simulation time | 19929475386 ps |
CPU time | 362.69 seconds |
Started | Jul 11 06:04:41 PM PDT 24 |
Finished | Jul 11 06:10:46 PM PDT 24 |
Peak memory | 202848 kb |
Host | smart-8e8096fb-4058-4c41-810e-ac8bb7fa2581 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981061230 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 32.sram_ctrl_partial_access_b2b.3981061230 |
Directory | /workspace/32.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_ram_cfg.2463390183 |
Short name | T904 |
Test name | |
Test status | |
Simulation time | 711060127 ps |
CPU time | 3.37 seconds |
Started | Jul 11 06:04:42 PM PDT 24 |
Finished | Jul 11 06:04:48 PM PDT 24 |
Peak memory | 202844 kb |
Host | smart-8f958d8f-0c03-4934-aabf-a46cfd88195a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463390183 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.2463390183 |
Directory | /workspace/32.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_regwen.2086511752 |
Short name | T591 |
Test name | |
Test status | |
Simulation time | 19940356369 ps |
CPU time | 81.71 seconds |
Started | Jul 11 06:04:42 PM PDT 24 |
Finished | Jul 11 06:06:06 PM PDT 24 |
Peak memory | 265176 kb |
Host | smart-3183e412-9ee0-49d5-a5e1-7485fcd82d42 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086511752 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.2086511752 |
Directory | /workspace/32.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_smoke.2500393583 |
Short name | T372 |
Test name | |
Test status | |
Simulation time | 1843485911 ps |
CPU time | 103.76 seconds |
Started | Jul 11 06:04:43 PM PDT 24 |
Finished | Jul 11 06:06:31 PM PDT 24 |
Peak memory | 338780 kb |
Host | smart-2c7fc386-e3ac-4ce4-ad82-1cd9cb6c89f4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500393583 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.2500393583 |
Directory | /workspace/32.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_stress_all.2320686307 |
Short name | T355 |
Test name | |
Test status | |
Simulation time | 45506707388 ps |
CPU time | 3637.26 seconds |
Started | Jul 11 06:04:49 PM PDT 24 |
Finished | Jul 11 07:05:30 PM PDT 24 |
Peak memory | 380816 kb |
Host | smart-6710fa2e-effe-4597-9897-3a0c2ae29a82 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320686307 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 32.sram_ctrl_stress_all.2320686307 |
Directory | /workspace/32.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.3626583318 |
Short name | T60 |
Test name | |
Test status | |
Simulation time | 5200902833 ps |
CPU time | 247.87 seconds |
Started | Jul 11 06:04:48 PM PDT 24 |
Finished | Jul 11 06:08:59 PM PDT 24 |
Peak memory | 346100 kb |
Host | smart-5222a1a8-0b49-41c3-8747-71ee6cf4968d |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3626583318 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all_with_rand_reset.3626583318 |
Directory | /workspace/32.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_stress_pipeline.2445332560 |
Short name | T436 |
Test name | |
Test status | |
Simulation time | 7560884951 ps |
CPU time | 236.18 seconds |
Started | Jul 11 06:04:43 PM PDT 24 |
Finished | Jul 11 06:08:43 PM PDT 24 |
Peak memory | 202848 kb |
Host | smart-5836acbf-c5ad-46ec-9788-524fddb857b7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445332560 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 2.sram_ctrl_stress_pipeline.2445332560 |
Directory | /workspace/32.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.19888656 |
Short name | T474 |
Test name | |
Test status | |
Simulation time | 776739912 ps |
CPU time | 51.5 seconds |
Started | Jul 11 06:04:44 PM PDT 24 |
Finished | Jul 11 06:05:39 PM PDT 24 |
Peak memory | 295028 kb |
Host | smart-77420813-fac0-47b1-abe4-5c8cc834bd78 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19888656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 32.sram_ctrl_throughput_w_partial_write.19888656 |
Directory | /workspace/32.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_access_during_key_req.1959554241 |
Short name | T238 |
Test name | |
Test status | |
Simulation time | 151644881093 ps |
CPU time | 918.12 seconds |
Started | Jul 11 06:04:52 PM PDT 24 |
Finished | Jul 11 06:20:14 PM PDT 24 |
Peak memory | 337808 kb |
Host | smart-70c3731a-4a33-4a96-8ca1-e06467adfe18 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959554241 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 33.sram_ctrl_access_during_key_req.1959554241 |
Directory | /workspace/33.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_alert_test.3818858157 |
Short name | T400 |
Test name | |
Test status | |
Simulation time | 13542022 ps |
CPU time | 0.66 seconds |
Started | Jul 11 06:04:53 PM PDT 24 |
Finished | Jul 11 06:04:58 PM PDT 24 |
Peak memory | 202440 kb |
Host | smart-c619488d-962f-4d41-a5c1-7318891f1a57 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818858157 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_alert_test.3818858157 |
Directory | /workspace/33.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_bijection.862387054 |
Short name | T576 |
Test name | |
Test status | |
Simulation time | 167275582945 ps |
CPU time | 2815.75 seconds |
Started | Jul 11 06:04:46 PM PDT 24 |
Finished | Jul 11 06:51:46 PM PDT 24 |
Peak memory | 203568 kb |
Host | smart-01c0358f-7967-464a-9acc-29386cdc3650 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862387054 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection. 862387054 |
Directory | /workspace/33.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_executable.788275098 |
Short name | T572 |
Test name | |
Test status | |
Simulation time | 12775215539 ps |
CPU time | 266.13 seconds |
Started | Jul 11 06:04:52 PM PDT 24 |
Finished | Jul 11 06:09:23 PM PDT 24 |
Peak memory | 340896 kb |
Host | smart-519add1a-e7d1-45e7-9cf8-247106cfa50c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788275098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executabl e.788275098 |
Directory | /workspace/33.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_lc_escalation.3233125635 |
Short name | T244 |
Test name | |
Test status | |
Simulation time | 9855486360 ps |
CPU time | 64.27 seconds |
Started | Jul 11 06:04:53 PM PDT 24 |
Finished | Jul 11 06:06:02 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-2abf3f56-a097-4476-a81c-f3cc24667b7e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233125635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_es calation.3233125635 |
Directory | /workspace/33.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_max_throughput.2756490504 |
Short name | T644 |
Test name | |
Test status | |
Simulation time | 5749933955 ps |
CPU time | 87.89 seconds |
Started | Jul 11 06:04:45 PM PDT 24 |
Finished | Jul 11 06:06:17 PM PDT 24 |
Peak memory | 341864 kb |
Host | smart-41f725a5-1730-4ec1-a7e4-eb4a7af9a95b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756490504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 33.sram_ctrl_max_throughput.2756490504 |
Directory | /workspace/33.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_mem_partial_access.2976764957 |
Short name | T721 |
Test name | |
Test status | |
Simulation time | 2628746848 ps |
CPU time | 87.65 seconds |
Started | Jul 11 06:04:53 PM PDT 24 |
Finished | Jul 11 06:06:25 PM PDT 24 |
Peak memory | 210996 kb |
Host | smart-a13ec730-92ee-4d78-a588-789020754030 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976764957 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 3.sram_ctrl_mem_partial_access.2976764957 |
Directory | /workspace/33.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_mem_walk.2213389192 |
Short name | T836 |
Test name | |
Test status | |
Simulation time | 27652337942 ps |
CPU time | 298.15 seconds |
Started | Jul 11 06:04:54 PM PDT 24 |
Finished | Jul 11 06:09:56 PM PDT 24 |
Peak memory | 211036 kb |
Host | smart-42e76383-b153-4c43-bf41-0d2ee00bd4a3 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213389192 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctr l_mem_walk.2213389192 |
Directory | /workspace/33.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_multiple_keys.3545324106 |
Short name | T711 |
Test name | |
Test status | |
Simulation time | 20227420657 ps |
CPU time | 701.22 seconds |
Started | Jul 11 06:04:47 PM PDT 24 |
Finished | Jul 11 06:16:32 PM PDT 24 |
Peak memory | 377644 kb |
Host | smart-192b87e7-3271-493a-abf8-6150867b4345 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545324106 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multi ple_keys.3545324106 |
Directory | /workspace/33.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_partial_access.2498417419 |
Short name | T373 |
Test name | |
Test status | |
Simulation time | 4474549142 ps |
CPU time | 16.18 seconds |
Started | Jul 11 06:04:46 PM PDT 24 |
Finished | Jul 11 06:05:06 PM PDT 24 |
Peak memory | 202756 kb |
Host | smart-f9ab6939-74ee-43ce-a99b-c60d51d97cc1 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498417419 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33. sram_ctrl_partial_access.2498417419 |
Directory | /workspace/33.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.2833936522 |
Short name | T362 |
Test name | |
Test status | |
Simulation time | 42240644495 ps |
CPU time | 469.5 seconds |
Started | Jul 11 06:04:45 PM PDT 24 |
Finished | Jul 11 06:12:38 PM PDT 24 |
Peak memory | 202796 kb |
Host | smart-aa81df6c-e9f2-424b-b7c1-28973dc96b87 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833936522 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 33.sram_ctrl_partial_access_b2b.2833936522 |
Directory | /workspace/33.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_ram_cfg.4239723234 |
Short name | T312 |
Test name | |
Test status | |
Simulation time | 1352804131 ps |
CPU time | 3.35 seconds |
Started | Jul 11 06:04:53 PM PDT 24 |
Finished | Jul 11 06:05:01 PM PDT 24 |
Peak memory | 202916 kb |
Host | smart-eb423d98-4f02-457e-8375-3ae2c1c87be2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239723234 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.4239723234 |
Directory | /workspace/33.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_regwen.826112446 |
Short name | T356 |
Test name | |
Test status | |
Simulation time | 4332517135 ps |
CPU time | 262.28 seconds |
Started | Jul 11 06:04:51 PM PDT 24 |
Finished | Jul 11 06:09:18 PM PDT 24 |
Peak memory | 371504 kb |
Host | smart-1804931b-fba1-4058-a7a2-3cc68e5b3e3c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826112446 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.826112446 |
Directory | /workspace/33.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_smoke.78286802 |
Short name | T359 |
Test name | |
Test status | |
Simulation time | 1005253160 ps |
CPU time | 12.27 seconds |
Started | Jul 11 06:04:46 PM PDT 24 |
Finished | Jul 11 06:05:02 PM PDT 24 |
Peak memory | 202960 kb |
Host | smart-f191e3e2-bf7b-4681-af54-9c862ea5a93f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78286802 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.78286802 |
Directory | /workspace/33.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_stress_all.3743103526 |
Short name | T159 |
Test name | |
Test status | |
Simulation time | 153419440757 ps |
CPU time | 7149.8 seconds |
Started | Jul 11 06:04:54 PM PDT 24 |
Finished | Jul 11 08:04:09 PM PDT 24 |
Peak memory | 389024 kb |
Host | smart-b55f8424-2edf-4c8c-a867-8978643cae09 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743103526 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 33.sram_ctrl_stress_all.3743103526 |
Directory | /workspace/33.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.814608946 |
Short name | T724 |
Test name | |
Test status | |
Simulation time | 2575895975 ps |
CPU time | 96.74 seconds |
Started | Jul 11 06:04:53 PM PDT 24 |
Finished | Jul 11 06:06:34 PM PDT 24 |
Peak memory | 313036 kb |
Host | smart-cfa85bfe-597c-4152-8715-7a978b35a126 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=814608946 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all_with_rand_reset.814608946 |
Directory | /workspace/33.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_stress_pipeline.3315919695 |
Short name | T432 |
Test name | |
Test status | |
Simulation time | 4921451726 ps |
CPU time | 350.39 seconds |
Started | Jul 11 06:04:46 PM PDT 24 |
Finished | Jul 11 06:10:40 PM PDT 24 |
Peak memory | 202848 kb |
Host | smart-93806c18-e494-42af-b4eb-fe291b663b22 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315919695 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 3.sram_ctrl_stress_pipeline.3315919695 |
Directory | /workspace/33.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.2328112198 |
Short name | T783 |
Test name | |
Test status | |
Simulation time | 3107451827 ps |
CPU time | 112.63 seconds |
Started | Jul 11 06:04:55 PM PDT 24 |
Finished | Jul 11 06:06:51 PM PDT 24 |
Peak memory | 366300 kb |
Host | smart-af399ef5-0cf6-463c-a79a-03a8cd7dcdf5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328112198 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 33.sram_ctrl_throughput_w_partial_write.2328112198 |
Directory | /workspace/33.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_access_during_key_req.1796109451 |
Short name | T682 |
Test name | |
Test status | |
Simulation time | 70017298666 ps |
CPU time | 788.55 seconds |
Started | Jul 11 06:04:59 PM PDT 24 |
Finished | Jul 11 06:18:09 PM PDT 24 |
Peak memory | 376288 kb |
Host | smart-d324a2e6-1d89-4dde-87f2-2bff9e107c81 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796109451 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 34.sram_ctrl_access_during_key_req.1796109451 |
Directory | /workspace/34.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_alert_test.2012545746 |
Short name | T651 |
Test name | |
Test status | |
Simulation time | 61137369 ps |
CPU time | 0.65 seconds |
Started | Jul 11 06:04:58 PM PDT 24 |
Finished | Jul 11 06:05:01 PM PDT 24 |
Peak memory | 202452 kb |
Host | smart-f80f73de-786b-4496-8165-1a18520cb8d2 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012545746 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_alert_test.2012545746 |
Directory | /workspace/34.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_bijection.3068944492 |
Short name | T920 |
Test name | |
Test status | |
Simulation time | 33197240161 ps |
CPU time | 2412.47 seconds |
Started | Jul 11 06:04:51 PM PDT 24 |
Finished | Jul 11 06:45:08 PM PDT 24 |
Peak memory | 203440 kb |
Host | smart-87a75dcb-5bc8-4061-a8f7-4760fa710f48 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068944492 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection .3068944492 |
Directory | /workspace/34.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_executable.1342010153 |
Short name | T502 |
Test name | |
Test status | |
Simulation time | 9622937807 ps |
CPU time | 1793.67 seconds |
Started | Jul 11 06:04:58 PM PDT 24 |
Finished | Jul 11 06:34:54 PM PDT 24 |
Peak memory | 378712 kb |
Host | smart-208518be-9069-4ed8-98eb-a6f506bbbce5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342010153 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_executab le.1342010153 |
Directory | /workspace/34.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_lc_escalation.3015733593 |
Short name | T494 |
Test name | |
Test status | |
Simulation time | 7666607312 ps |
CPU time | 51.48 seconds |
Started | Jul 11 06:04:59 PM PDT 24 |
Finished | Jul 11 06:05:52 PM PDT 24 |
Peak memory | 202784 kb |
Host | smart-1d517ecf-f12b-462e-b891-600a3a70210c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015733593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_es calation.3015733593 |
Directory | /workspace/34.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_max_throughput.2500454709 |
Short name | T935 |
Test name | |
Test status | |
Simulation time | 1412910827 ps |
CPU time | 26.42 seconds |
Started | Jul 11 06:04:53 PM PDT 24 |
Finished | Jul 11 06:05:24 PM PDT 24 |
Peak memory | 288528 kb |
Host | smart-b3089db2-1c30-45db-b167-9b9e838c5161 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500454709 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 34.sram_ctrl_max_throughput.2500454709 |
Directory | /workspace/34.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_mem_partial_access.1631393075 |
Short name | T341 |
Test name | |
Test status | |
Simulation time | 4575742311 ps |
CPU time | 161.18 seconds |
Started | Jul 11 06:04:59 PM PDT 24 |
Finished | Jul 11 06:07:42 PM PDT 24 |
Peak memory | 219240 kb |
Host | smart-020367f1-07e0-4de9-ac2d-d2f8dc00b629 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631393075 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 4.sram_ctrl_mem_partial_access.1631393075 |
Directory | /workspace/34.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_mem_walk.3360114133 |
Short name | T943 |
Test name | |
Test status | |
Simulation time | 32097951192 ps |
CPU time | 167.88 seconds |
Started | Jul 11 06:05:02 PM PDT 24 |
Finished | Jul 11 06:07:51 PM PDT 24 |
Peak memory | 211040 kb |
Host | smart-f91ae9d6-92eb-43a0-8910-d127f5cacf25 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360114133 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctr l_mem_walk.3360114133 |
Directory | /workspace/34.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_multiple_keys.1481566024 |
Short name | T204 |
Test name | |
Test status | |
Simulation time | 134129640953 ps |
CPU time | 781.8 seconds |
Started | Jul 11 06:04:50 PM PDT 24 |
Finished | Jul 11 06:17:56 PM PDT 24 |
Peak memory | 379912 kb |
Host | smart-19301933-6c8f-4be4-9d73-6b95e8ab13b8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481566024 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multi ple_keys.1481566024 |
Directory | /workspace/34.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_partial_access.1191999733 |
Short name | T240 |
Test name | |
Test status | |
Simulation time | 1157144396 ps |
CPU time | 57.71 seconds |
Started | Jul 11 06:04:52 PM PDT 24 |
Finished | Jul 11 06:05:54 PM PDT 24 |
Peak memory | 313100 kb |
Host | smart-da644c9a-92f0-4781-911d-86b80b53fcbc |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191999733 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34. sram_ctrl_partial_access.1191999733 |
Directory | /workspace/34.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.1010106779 |
Short name | T443 |
Test name | |
Test status | |
Simulation time | 11175633216 ps |
CPU time | 282.93 seconds |
Started | Jul 11 06:05:00 PM PDT 24 |
Finished | Jul 11 06:09:44 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-8245014b-cba7-4006-a0f5-28b12d41ea79 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010106779 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 34.sram_ctrl_partial_access_b2b.1010106779 |
Directory | /workspace/34.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_ram_cfg.1884520415 |
Short name | T695 |
Test name | |
Test status | |
Simulation time | 408846132 ps |
CPU time | 3.16 seconds |
Started | Jul 11 06:04:59 PM PDT 24 |
Finished | Jul 11 06:05:04 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-096e8844-9913-4ce7-969a-103708d55adf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884520415 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.1884520415 |
Directory | /workspace/34.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_regwen.2167997787 |
Short name | T873 |
Test name | |
Test status | |
Simulation time | 5204890672 ps |
CPU time | 567.17 seconds |
Started | Jul 11 06:04:59 PM PDT 24 |
Finished | Jul 11 06:14:28 PM PDT 24 |
Peak memory | 373660 kb |
Host | smart-e2afa017-a848-41c0-844f-0d0c5e255b13 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167997787 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.2167997787 |
Directory | /workspace/34.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_smoke.1060749038 |
Short name | T844 |
Test name | |
Test status | |
Simulation time | 422706466 ps |
CPU time | 29.49 seconds |
Started | Jul 11 06:04:52 PM PDT 24 |
Finished | Jul 11 06:05:26 PM PDT 24 |
Peak memory | 285696 kb |
Host | smart-de14594c-a271-4395-acfe-81dd31a2e04c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060749038 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.1060749038 |
Directory | /workspace/34.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_stress_all.476989511 |
Short name | T493 |
Test name | |
Test status | |
Simulation time | 148184334004 ps |
CPU time | 3578.34 seconds |
Started | Jul 11 06:04:59 PM PDT 24 |
Finished | Jul 11 07:04:40 PM PDT 24 |
Peak memory | 380872 kb |
Host | smart-0ae0eeca-7860-4df9-af94-5daf6dae3b8e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476989511 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 34.sram_ctrl_stress_all.476989511 |
Directory | /workspace/34.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.3301756476 |
Short name | T515 |
Test name | |
Test status | |
Simulation time | 5271193581 ps |
CPU time | 32.83 seconds |
Started | Jul 11 06:04:59 PM PDT 24 |
Finished | Jul 11 06:05:34 PM PDT 24 |
Peak memory | 211160 kb |
Host | smart-57878d68-7dc4-4286-9e7b-e827dee27413 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3301756476 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all_with_rand_reset.3301756476 |
Directory | /workspace/34.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_stress_pipeline.2212246942 |
Short name | T706 |
Test name | |
Test status | |
Simulation time | 7149842164 ps |
CPU time | 301.6 seconds |
Started | Jul 11 06:04:54 PM PDT 24 |
Finished | Jul 11 06:10:00 PM PDT 24 |
Peak memory | 202856 kb |
Host | smart-a286c4ff-365a-4d14-8459-1d3c88c975c4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212246942 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 4.sram_ctrl_stress_pipeline.2212246942 |
Directory | /workspace/34.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.923127143 |
Short name | T730 |
Test name | |
Test status | |
Simulation time | 2700617449 ps |
CPU time | 7.5 seconds |
Started | Jul 11 06:04:59 PM PDT 24 |
Finished | Jul 11 06:05:09 PM PDT 24 |
Peak memory | 218896 kb |
Host | smart-fdf735de-3172-4a4c-b054-16f74a5e6d72 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923127143 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 34.sram_ctrl_throughput_w_partial_write.923127143 |
Directory | /workspace/34.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_access_during_key_req.281570529 |
Short name | T419 |
Test name | |
Test status | |
Simulation time | 16365271379 ps |
CPU time | 1673.54 seconds |
Started | Jul 11 06:05:05 PM PDT 24 |
Finished | Jul 11 06:33:01 PM PDT 24 |
Peak memory | 380792 kb |
Host | smart-e65648d1-108d-4b64-8b13-36f54eb17395 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281570529 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 35.sram_ctrl_access_during_key_req.281570529 |
Directory | /workspace/35.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_alert_test.1723513365 |
Short name | T484 |
Test name | |
Test status | |
Simulation time | 22115999 ps |
CPU time | 0.66 seconds |
Started | Jul 11 06:05:01 PM PDT 24 |
Finished | Jul 11 06:05:04 PM PDT 24 |
Peak memory | 202424 kb |
Host | smart-d0e04907-a102-4b17-b973-a54ee40c5450 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723513365 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_alert_test.1723513365 |
Directory | /workspace/35.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_bijection.2475929465 |
Short name | T422 |
Test name | |
Test status | |
Simulation time | 135254148212 ps |
CPU time | 759.87 seconds |
Started | Jul 11 06:05:00 PM PDT 24 |
Finished | Jul 11 06:17:41 PM PDT 24 |
Peak memory | 203568 kb |
Host | smart-eb900c35-b783-4abb-9edb-67539f42c351 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475929465 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection .2475929465 |
Directory | /workspace/35.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_executable.1822050145 |
Short name | T406 |
Test name | |
Test status | |
Simulation time | 7321882287 ps |
CPU time | 611.17 seconds |
Started | Jul 11 06:05:06 PM PDT 24 |
Finished | Jul 11 06:15:19 PM PDT 24 |
Peak memory | 376688 kb |
Host | smart-deccc1a6-80f7-44e9-b3c8-df4ac4a44e09 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822050145 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executab le.1822050145 |
Directory | /workspace/35.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_lc_escalation.731581498 |
Short name | T649 |
Test name | |
Test status | |
Simulation time | 59665931614 ps |
CPU time | 94.75 seconds |
Started | Jul 11 06:05:03 PM PDT 24 |
Finished | Jul 11 06:06:41 PM PDT 24 |
Peak memory | 211124 kb |
Host | smart-abd6103c-d471-49bd-a558-c3a88b827175 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731581498 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_esc alation.731581498 |
Directory | /workspace/35.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_max_throughput.1843625655 |
Short name | T562 |
Test name | |
Test status | |
Simulation time | 3077880867 ps |
CPU time | 64.08 seconds |
Started | Jul 11 06:05:02 PM PDT 24 |
Finished | Jul 11 06:06:08 PM PDT 24 |
Peak memory | 326520 kb |
Host | smart-5b44208c-2af1-46c6-8517-eea4ca124ddd |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843625655 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 35.sram_ctrl_max_throughput.1843625655 |
Directory | /workspace/35.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_mem_partial_access.2709181244 |
Short name | T57 |
Test name | |
Test status | |
Simulation time | 6319489425 ps |
CPU time | 76.63 seconds |
Started | Jul 11 06:05:02 PM PDT 24 |
Finished | Jul 11 06:06:20 PM PDT 24 |
Peak memory | 211080 kb |
Host | smart-dcc2cab3-f39d-4a92-8cd5-7578331c3f7b |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709181244 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 5.sram_ctrl_mem_partial_access.2709181244 |
Directory | /workspace/35.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_mem_walk.3561445766 |
Short name | T471 |
Test name | |
Test status | |
Simulation time | 10341824794 ps |
CPU time | 172.43 seconds |
Started | Jul 11 06:05:03 PM PDT 24 |
Finished | Jul 11 06:07:58 PM PDT 24 |
Peak memory | 210996 kb |
Host | smart-5741732a-8fd6-4a0d-8f67-86f32ac202d9 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561445766 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctr l_mem_walk.3561445766 |
Directory | /workspace/35.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_multiple_keys.2663555173 |
Short name | T425 |
Test name | |
Test status | |
Simulation time | 890797847 ps |
CPU time | 9.3 seconds |
Started | Jul 11 06:04:57 PM PDT 24 |
Finished | Jul 11 06:05:09 PM PDT 24 |
Peak memory | 205368 kb |
Host | smart-3e466458-b3f4-481d-bbae-bdfc5ee159e8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663555173 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multi ple_keys.2663555173 |
Directory | /workspace/35.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_partial_access.454361562 |
Short name | T384 |
Test name | |
Test status | |
Simulation time | 2637843655 ps |
CPU time | 20.86 seconds |
Started | Jul 11 06:05:02 PM PDT 24 |
Finished | Jul 11 06:05:25 PM PDT 24 |
Peak memory | 202792 kb |
Host | smart-7c00cd61-d12d-484d-bf54-dfb1690e6ce8 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454361562 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.s ram_ctrl_partial_access.454361562 |
Directory | /workspace/35.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_partial_access_b2b.3499863140 |
Short name | T302 |
Test name | |
Test status | |
Simulation time | 24128727550 ps |
CPU time | 156.78 seconds |
Started | Jul 11 06:05:00 PM PDT 24 |
Finished | Jul 11 06:07:39 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-87d5dfde-0d00-4f89-915a-38ca234f6c42 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499863140 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 35.sram_ctrl_partial_access_b2b.3499863140 |
Directory | /workspace/35.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_ram_cfg.353152365 |
Short name | T144 |
Test name | |
Test status | |
Simulation time | 1397390558 ps |
CPU time | 3.74 seconds |
Started | Jul 11 06:05:21 PM PDT 24 |
Finished | Jul 11 06:05:27 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-c567f0fb-29b1-4897-b4d6-ad1a9c0a0ec9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353152365 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.353152365 |
Directory | /workspace/35.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_regwen.3783373559 |
Short name | T83 |
Test name | |
Test status | |
Simulation time | 130027779799 ps |
CPU time | 695.8 seconds |
Started | Jul 11 06:05:06 PM PDT 24 |
Finished | Jul 11 06:16:44 PM PDT 24 |
Peak memory | 372552 kb |
Host | smart-2c891fb2-049a-4bec-ac24-8cad5d512575 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783373559 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.3783373559 |
Directory | /workspace/35.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_smoke.455148046 |
Short name | T907 |
Test name | |
Test status | |
Simulation time | 5575905174 ps |
CPU time | 22.17 seconds |
Started | Jul 11 06:04:58 PM PDT 24 |
Finished | Jul 11 06:05:22 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-646da5c8-4c48-47a1-88f1-02137713b386 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455148046 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.455148046 |
Directory | /workspace/35.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_stress_all.1319639756 |
Short name | T577 |
Test name | |
Test status | |
Simulation time | 116859264411 ps |
CPU time | 4013.13 seconds |
Started | Jul 11 06:05:02 PM PDT 24 |
Finished | Jul 11 07:11:59 PM PDT 24 |
Peak memory | 380836 kb |
Host | smart-fe3b0843-299a-410e-877d-9e2d65c6f693 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319639756 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 35.sram_ctrl_stress_all.1319639756 |
Directory | /workspace/35.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.3296798480 |
Short name | T134 |
Test name | |
Test status | |
Simulation time | 952049225 ps |
CPU time | 24.45 seconds |
Started | Jul 11 06:05:01 PM PDT 24 |
Finished | Jul 11 06:05:28 PM PDT 24 |
Peak memory | 211060 kb |
Host | smart-93dec2b8-e6fa-4388-9152-59bb44471620 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3296798480 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all_with_rand_reset.3296798480 |
Directory | /workspace/35.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_stress_pipeline.2273179997 |
Short name | T929 |
Test name | |
Test status | |
Simulation time | 8565835650 ps |
CPU time | 301.61 seconds |
Started | Jul 11 06:05:04 PM PDT 24 |
Finished | Jul 11 06:10:08 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-f8923e3d-e534-4167-a040-a0b76886768f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273179997 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 5.sram_ctrl_stress_pipeline.2273179997 |
Directory | /workspace/35.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.3847801907 |
Short name | T171 |
Test name | |
Test status | |
Simulation time | 6469002786 ps |
CPU time | 25.65 seconds |
Started | Jul 11 06:05:02 PM PDT 24 |
Finished | Jul 11 06:05:31 PM PDT 24 |
Peak memory | 268352 kb |
Host | smart-56b050f9-d4e7-4f20-b139-d9054ec34d16 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847801907 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 35.sram_ctrl_throughput_w_partial_write.3847801907 |
Directory | /workspace/35.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_access_during_key_req.2885168892 |
Short name | T315 |
Test name | |
Test status | |
Simulation time | 10904589246 ps |
CPU time | 813.74 seconds |
Started | Jul 11 06:05:06 PM PDT 24 |
Finished | Jul 11 06:18:42 PM PDT 24 |
Peak memory | 367500 kb |
Host | smart-d1b65423-33c2-4e0b-87be-a6f9bd9046ab |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885168892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 36.sram_ctrl_access_during_key_req.2885168892 |
Directory | /workspace/36.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_alert_test.3628176546 |
Short name | T606 |
Test name | |
Test status | |
Simulation time | 44276130 ps |
CPU time | 0.68 seconds |
Started | Jul 11 06:05:15 PM PDT 24 |
Finished | Jul 11 06:05:17 PM PDT 24 |
Peak memory | 202120 kb |
Host | smart-f58f7d1b-bfac-4f4a-ba8f-12bc7d293d9c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628176546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_alert_test.3628176546 |
Directory | /workspace/36.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_bijection.2205510266 |
Short name | T34 |
Test name | |
Test status | |
Simulation time | 181068018695 ps |
CPU time | 1042.44 seconds |
Started | Jul 11 06:05:10 PM PDT 24 |
Finished | Jul 11 06:22:34 PM PDT 24 |
Peak memory | 203428 kb |
Host | smart-d634f8b2-178e-4411-9901-922f367cf8a2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205510266 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection .2205510266 |
Directory | /workspace/36.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_executable.2253003591 |
Short name | T353 |
Test name | |
Test status | |
Simulation time | 8382318830 ps |
CPU time | 1225.6 seconds |
Started | Jul 11 06:05:13 PM PDT 24 |
Finished | Jul 11 06:25:40 PM PDT 24 |
Peak memory | 379732 kb |
Host | smart-5be2c2eb-e338-422e-a718-59f1d7187631 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253003591 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executab le.2253003591 |
Directory | /workspace/36.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_lc_escalation.1156350689 |
Short name | T700 |
Test name | |
Test status | |
Simulation time | 15358016858 ps |
CPU time | 86.06 seconds |
Started | Jul 11 06:05:07 PM PDT 24 |
Finished | Jul 11 06:06:35 PM PDT 24 |
Peak memory | 214992 kb |
Host | smart-c5cb8047-842b-4b87-828c-2ab9921dd6a6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156350689 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_es calation.1156350689 |
Directory | /workspace/36.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_max_throughput.26685454 |
Short name | T879 |
Test name | |
Test status | |
Simulation time | 5093491686 ps |
CPU time | 153.77 seconds |
Started | Jul 11 06:05:12 PM PDT 24 |
Finished | Jul 11 06:07:47 PM PDT 24 |
Peak memory | 372412 kb |
Host | smart-7bca3c3e-f7ba-4fc7-a6ba-c7343e56f73a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26685454 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 36.sram_ctrl_max_throughput.26685454 |
Directory | /workspace/36.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_mem_partial_access.2332630855 |
Short name | T51 |
Test name | |
Test status | |
Simulation time | 11552524002 ps |
CPU time | 89.46 seconds |
Started | Jul 11 06:05:08 PM PDT 24 |
Finished | Jul 11 06:06:39 PM PDT 24 |
Peak memory | 211056 kb |
Host | smart-24dd1f2a-744a-4b3e-93a5-c28cf6d18c52 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332630855 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 6.sram_ctrl_mem_partial_access.2332630855 |
Directory | /workspace/36.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_mem_walk.688137387 |
Short name | T795 |
Test name | |
Test status | |
Simulation time | 9073517925 ps |
CPU time | 176.86 seconds |
Started | Jul 11 06:05:09 PM PDT 24 |
Finished | Jul 11 06:08:07 PM PDT 24 |
Peak memory | 211036 kb |
Host | smart-dca9e742-889b-406a-8b31-f83e95b7ad4a |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688137387 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl _mem_walk.688137387 |
Directory | /workspace/36.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_multiple_keys.1381329111 |
Short name | T922 |
Test name | |
Test status | |
Simulation time | 63258873597 ps |
CPU time | 835.31 seconds |
Started | Jul 11 06:05:09 PM PDT 24 |
Finished | Jul 11 06:19:06 PM PDT 24 |
Peak memory | 369552 kb |
Host | smart-ba0e08fc-4201-47c9-b110-1314d9755cec |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381329111 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multi ple_keys.1381329111 |
Directory | /workspace/36.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_partial_access.2047172341 |
Short name | T177 |
Test name | |
Test status | |
Simulation time | 570736675 ps |
CPU time | 6.61 seconds |
Started | Jul 11 06:05:12 PM PDT 24 |
Finished | Jul 11 06:05:21 PM PDT 24 |
Peak memory | 202724 kb |
Host | smart-56af029c-717e-49e0-ad26-892b861df329 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047172341 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36. sram_ctrl_partial_access.2047172341 |
Directory | /workspace/36.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.3652574925 |
Short name | T696 |
Test name | |
Test status | |
Simulation time | 6314000663 ps |
CPU time | 294.68 seconds |
Started | Jul 11 06:05:11 PM PDT 24 |
Finished | Jul 11 06:10:07 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-05042171-d6f5-4265-b7c2-c3cb6674d389 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652574925 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 36.sram_ctrl_partial_access_b2b.3652574925 |
Directory | /workspace/36.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_ram_cfg.463877211 |
Short name | T28 |
Test name | |
Test status | |
Simulation time | 552637948 ps |
CPU time | 3.17 seconds |
Started | Jul 11 06:05:12 PM PDT 24 |
Finished | Jul 11 06:05:17 PM PDT 24 |
Peak memory | 202916 kb |
Host | smart-ccf23e42-707e-4d05-aba3-18f94a41ee7f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463877211 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.463877211 |
Directory | /workspace/36.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_regwen.399329609 |
Short name | T542 |
Test name | |
Test status | |
Simulation time | 71529491479 ps |
CPU time | 767.13 seconds |
Started | Jul 11 06:05:10 PM PDT 24 |
Finished | Jul 11 06:17:58 PM PDT 24 |
Peak memory | 379784 kb |
Host | smart-ae29a718-dc07-4746-afc0-b1cd928f8fdd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399329609 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.399329609 |
Directory | /workspace/36.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_smoke.2025344573 |
Short name | T685 |
Test name | |
Test status | |
Simulation time | 565754542 ps |
CPU time | 15.1 seconds |
Started | Jul 11 06:05:04 PM PDT 24 |
Finished | Jul 11 06:05:22 PM PDT 24 |
Peak memory | 254392 kb |
Host | smart-a43c257e-dd1c-4436-be05-40faf22d7f46 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025344573 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.2025344573 |
Directory | /workspace/36.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_stress_all.3997625927 |
Short name | T386 |
Test name | |
Test status | |
Simulation time | 96712937736 ps |
CPU time | 5049.98 seconds |
Started | Jul 11 06:05:08 PM PDT 24 |
Finished | Jul 11 07:29:21 PM PDT 24 |
Peak memory | 381768 kb |
Host | smart-1ecf8207-c5dd-4a91-9d49-0e0803c99f96 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997625927 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 36.sram_ctrl_stress_all.3997625927 |
Directory | /workspace/36.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.2298402912 |
Short name | T132 |
Test name | |
Test status | |
Simulation time | 597532051 ps |
CPU time | 20.43 seconds |
Started | Jul 11 06:05:09 PM PDT 24 |
Finished | Jul 11 06:05:31 PM PDT 24 |
Peak memory | 211012 kb |
Host | smart-b4c902e8-de67-4cde-a4d5-9b483f5eb0ac |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2298402912 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all_with_rand_reset.2298402912 |
Directory | /workspace/36.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_stress_pipeline.2638176704 |
Short name | T764 |
Test name | |
Test status | |
Simulation time | 5399227644 ps |
CPU time | 123.87 seconds |
Started | Jul 11 06:05:09 PM PDT 24 |
Finished | Jul 11 06:07:14 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-474e594e-abb3-48a0-a89f-5e5e4da73c33 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638176704 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 6.sram_ctrl_stress_pipeline.2638176704 |
Directory | /workspace/36.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.2771577628 |
Short name | T272 |
Test name | |
Test status | |
Simulation time | 738978490 ps |
CPU time | 58.16 seconds |
Started | Jul 11 06:05:08 PM PDT 24 |
Finished | Jul 11 06:06:08 PM PDT 24 |
Peak memory | 300900 kb |
Host | smart-22b0bc04-913f-4edc-9106-ec33930a5305 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771577628 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 36.sram_ctrl_throughput_w_partial_write.2771577628 |
Directory | /workspace/36.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_access_during_key_req.1052685391 |
Short name | T814 |
Test name | |
Test status | |
Simulation time | 33662673560 ps |
CPU time | 602.68 seconds |
Started | Jul 11 06:05:13 PM PDT 24 |
Finished | Jul 11 06:15:18 PM PDT 24 |
Peak memory | 375648 kb |
Host | smart-05501fd8-38b5-4132-9443-c93eedca9d98 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052685391 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 37.sram_ctrl_access_during_key_req.1052685391 |
Directory | /workspace/37.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_alert_test.3057789060 |
Short name | T318 |
Test name | |
Test status | |
Simulation time | 27112671 ps |
CPU time | 0.66 seconds |
Started | Jul 11 06:05:18 PM PDT 24 |
Finished | Jul 11 06:05:21 PM PDT 24 |
Peak memory | 202616 kb |
Host | smart-4587e6b8-5f02-4a98-b8c7-4a01b9782ae6 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057789060 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_alert_test.3057789060 |
Directory | /workspace/37.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_bijection.2616443669 |
Short name | T416 |
Test name | |
Test status | |
Simulation time | 43234528085 ps |
CPU time | 687.73 seconds |
Started | Jul 11 06:05:12 PM PDT 24 |
Finished | Jul 11 06:16:42 PM PDT 24 |
Peak memory | 203424 kb |
Host | smart-4f2b1406-6273-4382-ae52-722192aacec6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616443669 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection .2616443669 |
Directory | /workspace/37.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_executable.7240479 |
Short name | T564 |
Test name | |
Test status | |
Simulation time | 40626026242 ps |
CPU time | 653.03 seconds |
Started | Jul 11 06:05:14 PM PDT 24 |
Finished | Jul 11 06:16:09 PM PDT 24 |
Peak memory | 373532 kb |
Host | smart-6835c26c-221e-493b-a91a-6bb1f16423a8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7240479 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executa ble_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executable.7240479 |
Directory | /workspace/37.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_lc_escalation.697426089 |
Short name | T543 |
Test name | |
Test status | |
Simulation time | 26232802713 ps |
CPU time | 84.52 seconds |
Started | Jul 11 06:05:14 PM PDT 24 |
Finished | Jul 11 06:06:40 PM PDT 24 |
Peak memory | 202880 kb |
Host | smart-101c63e0-6cc2-43af-bc25-7ced5bcb595b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697426089 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_esc alation.697426089 |
Directory | /workspace/37.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_max_throughput.608046377 |
Short name | T473 |
Test name | |
Test status | |
Simulation time | 1393825191 ps |
CPU time | 9.96 seconds |
Started | Jul 11 06:05:14 PM PDT 24 |
Finished | Jul 11 06:05:25 PM PDT 24 |
Peak memory | 235284 kb |
Host | smart-faa5bc09-cf62-4884-8ab1-b6168b3486eb |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608046377 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 37.sram_ctrl_max_throughput.608046377 |
Directory | /workspace/37.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_mem_partial_access.223354568 |
Short name | T864 |
Test name | |
Test status | |
Simulation time | 9648442787 ps |
CPU time | 63.61 seconds |
Started | Jul 11 06:05:16 PM PDT 24 |
Finished | Jul 11 06:06:21 PM PDT 24 |
Peak memory | 211684 kb |
Host | smart-9a039128-9e99-4ab3-818d-a0e5ddc73367 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223354568 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37 .sram_ctrl_mem_partial_access.223354568 |
Directory | /workspace/37.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_mem_walk.2045073778 |
Short name | T54 |
Test name | |
Test status | |
Simulation time | 5591236791 ps |
CPU time | 293.98 seconds |
Started | Jul 11 06:05:14 PM PDT 24 |
Finished | Jul 11 06:10:10 PM PDT 24 |
Peak memory | 211044 kb |
Host | smart-23930c2a-2ae6-403a-aff6-2c9649875be9 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045073778 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctr l_mem_walk.2045073778 |
Directory | /workspace/37.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_multiple_keys.4238499812 |
Short name | T589 |
Test name | |
Test status | |
Simulation time | 13708384822 ps |
CPU time | 977.82 seconds |
Started | Jul 11 06:05:14 PM PDT 24 |
Finished | Jul 11 06:21:34 PM PDT 24 |
Peak memory | 374604 kb |
Host | smart-ae3169f6-a3ec-41fc-879a-1514f28cd851 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238499812 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multi ple_keys.4238499812 |
Directory | /workspace/37.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_partial_access.3985545867 |
Short name | T596 |
Test name | |
Test status | |
Simulation time | 4074778701 ps |
CPU time | 109.25 seconds |
Started | Jul 11 06:05:16 PM PDT 24 |
Finished | Jul 11 06:07:06 PM PDT 24 |
Peak memory | 340784 kb |
Host | smart-eb6c4d11-1587-4a27-afb1-f5f5f22b22c7 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985545867 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37. sram_ctrl_partial_access.3985545867 |
Directory | /workspace/37.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.391496299 |
Short name | T773 |
Test name | |
Test status | |
Simulation time | 13213211842 ps |
CPU time | 379.38 seconds |
Started | Jul 11 06:05:18 PM PDT 24 |
Finished | Jul 11 06:11:39 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-170d989f-2888-4b98-9fa4-c505228c9fc1 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391496299 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 37.sram_ctrl_partial_access_b2b.391496299 |
Directory | /workspace/37.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_ram_cfg.879757627 |
Short name | T274 |
Test name | |
Test status | |
Simulation time | 1680816813 ps |
CPU time | 3.91 seconds |
Started | Jul 11 06:05:11 PM PDT 24 |
Finished | Jul 11 06:05:17 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-7e1b979f-8a3b-4c35-bdbd-8c5da59b5d78 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879757627 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.879757627 |
Directory | /workspace/37.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_regwen.3892408010 |
Short name | T661 |
Test name | |
Test status | |
Simulation time | 10753542518 ps |
CPU time | 1190.95 seconds |
Started | Jul 11 06:05:13 PM PDT 24 |
Finished | Jul 11 06:25:06 PM PDT 24 |
Peak memory | 375648 kb |
Host | smart-6b325dbb-d5d1-4521-90b1-5a410bae10bb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892408010 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.3892408010 |
Directory | /workspace/37.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_smoke.3464901811 |
Short name | T582 |
Test name | |
Test status | |
Simulation time | 2514031357 ps |
CPU time | 17.96 seconds |
Started | Jul 11 06:05:16 PM PDT 24 |
Finished | Jul 11 06:05:35 PM PDT 24 |
Peak memory | 253872 kb |
Host | smart-a2e59432-a186-4e5f-9f38-91da95749758 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464901811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.3464901811 |
Directory | /workspace/37.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_stress_all.2623117396 |
Short name | T19 |
Test name | |
Test status | |
Simulation time | 226383145913 ps |
CPU time | 6865.54 seconds |
Started | Jul 11 06:05:17 PM PDT 24 |
Finished | Jul 11 07:59:44 PM PDT 24 |
Peak memory | 379604 kb |
Host | smart-52bee918-431d-4b18-bb88-e2492333d424 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623117396 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 37.sram_ctrl_stress_all.2623117396 |
Directory | /workspace/37.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.2024619643 |
Short name | T689 |
Test name | |
Test status | |
Simulation time | 398390088 ps |
CPU time | 13.02 seconds |
Started | Jul 11 06:05:24 PM PDT 24 |
Finished | Jul 11 06:05:39 PM PDT 24 |
Peak memory | 211164 kb |
Host | smart-dc45066c-808f-4b49-a932-2361ed17fc86 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2024619643 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all_with_rand_reset.2024619643 |
Directory | /workspace/37.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_stress_pipeline.1250308145 |
Short name | T519 |
Test name | |
Test status | |
Simulation time | 6602060193 ps |
CPU time | 259.87 seconds |
Started | Jul 11 06:05:15 PM PDT 24 |
Finished | Jul 11 06:09:36 PM PDT 24 |
Peak memory | 202868 kb |
Host | smart-d6f22256-5d5d-4ce8-b9e8-5dd033a1e7fc |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250308145 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 7.sram_ctrl_stress_pipeline.1250308145 |
Directory | /workspace/37.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.1016622614 |
Short name | T791 |
Test name | |
Test status | |
Simulation time | 754571184 ps |
CPU time | 39.27 seconds |
Started | Jul 11 06:05:13 PM PDT 24 |
Finished | Jul 11 06:05:54 PM PDT 24 |
Peak memory | 293732 kb |
Host | smart-0a268ef3-f25f-4817-bc7e-3c3fe06027e5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016622614 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 37.sram_ctrl_throughput_w_partial_write.1016622614 |
Directory | /workspace/37.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_access_during_key_req.1025615780 |
Short name | T604 |
Test name | |
Test status | |
Simulation time | 178138877622 ps |
CPU time | 1021.25 seconds |
Started | Jul 11 06:05:24 PM PDT 24 |
Finished | Jul 11 06:22:27 PM PDT 24 |
Peak memory | 373612 kb |
Host | smart-51c060f2-586f-4927-b97d-eeb9bf1b1e15 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025615780 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 38.sram_ctrl_access_during_key_req.1025615780 |
Directory | /workspace/38.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_alert_test.2284952256 |
Short name | T388 |
Test name | |
Test status | |
Simulation time | 43719666 ps |
CPU time | 0.67 seconds |
Started | Jul 11 06:05:25 PM PDT 24 |
Finished | Jul 11 06:05:28 PM PDT 24 |
Peak memory | 202392 kb |
Host | smart-a55bfe32-7a7d-4d11-9e09-8dade88eb77d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284952256 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_alert_test.2284952256 |
Directory | /workspace/38.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_bijection.2855163850 |
Short name | T808 |
Test name | |
Test status | |
Simulation time | 106833671822 ps |
CPU time | 2334.23 seconds |
Started | Jul 11 06:05:19 PM PDT 24 |
Finished | Jul 11 06:44:15 PM PDT 24 |
Peak memory | 203384 kb |
Host | smart-716e92a9-b1a2-43bd-870d-56c15b354e4b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855163850 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection .2855163850 |
Directory | /workspace/38.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_lc_escalation.266415311 |
Short name | T522 |
Test name | |
Test status | |
Simulation time | 1841124120 ps |
CPU time | 6.89 seconds |
Started | Jul 11 06:05:19 PM PDT 24 |
Finished | Jul 11 06:05:28 PM PDT 24 |
Peak memory | 210976 kb |
Host | smart-fb206f22-e8ba-4b9c-aae4-151f31e0450c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266415311 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_esc alation.266415311 |
Directory | /workspace/38.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_max_throughput.72489378 |
Short name | T250 |
Test name | |
Test status | |
Simulation time | 3998322750 ps |
CPU time | 129.94 seconds |
Started | Jul 11 06:05:20 PM PDT 24 |
Finished | Jul 11 06:07:33 PM PDT 24 |
Peak memory | 361224 kb |
Host | smart-ec55a1e3-67a4-4439-901a-a1bf3793f1d7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72489378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 38.sram_ctrl_max_throughput.72489378 |
Directory | /workspace/38.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_mem_walk.811572641 |
Short name | T704 |
Test name | |
Test status | |
Simulation time | 34575194913 ps |
CPU time | 319.06 seconds |
Started | Jul 11 06:05:23 PM PDT 24 |
Finished | Jul 11 06:10:45 PM PDT 24 |
Peak memory | 210968 kb |
Host | smart-bebcac85-65bc-40c4-a086-f1ca20c56d4c |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811572641 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl _mem_walk.811572641 |
Directory | /workspace/38.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_multiple_keys.274101654 |
Short name | T882 |
Test name | |
Test status | |
Simulation time | 3191631250 ps |
CPU time | 183.51 seconds |
Started | Jul 11 06:05:18 PM PDT 24 |
Finished | Jul 11 06:08:23 PM PDT 24 |
Peak memory | 370456 kb |
Host | smart-b38d088a-d9fa-4d9c-959e-8b26c10792c7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274101654 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multip le_keys.274101654 |
Directory | /workspace/38.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_partial_access.3714853656 |
Short name | T270 |
Test name | |
Test status | |
Simulation time | 574777304 ps |
CPU time | 14.73 seconds |
Started | Jul 11 06:05:17 PM PDT 24 |
Finished | Jul 11 06:05:33 PM PDT 24 |
Peak memory | 202728 kb |
Host | smart-294ed152-e2de-46a7-9c8c-94dd6e05124a |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714853656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38. sram_ctrl_partial_access.3714853656 |
Directory | /workspace/38.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_ram_cfg.4150170008 |
Short name | T788 |
Test name | |
Test status | |
Simulation time | 707033184 ps |
CPU time | 3.51 seconds |
Started | Jul 11 06:05:22 PM PDT 24 |
Finished | Jul 11 06:05:28 PM PDT 24 |
Peak memory | 202880 kb |
Host | smart-79a6bfb8-86f1-489c-ab2e-50b78652ba8b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150170008 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.4150170008 |
Directory | /workspace/38.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_regwen.3225104936 |
Short name | T872 |
Test name | |
Test status | |
Simulation time | 8317938111 ps |
CPU time | 956.95 seconds |
Started | Jul 11 06:05:17 PM PDT 24 |
Finished | Jul 11 06:21:16 PM PDT 24 |
Peak memory | 371804 kb |
Host | smart-c890d15d-598b-49a1-90b2-62ca9a203bf2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225104936 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.3225104936 |
Directory | /workspace/38.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_smoke.236522631 |
Short name | T822 |
Test name | |
Test status | |
Simulation time | 396516766 ps |
CPU time | 20.72 seconds |
Started | Jul 11 06:05:20 PM PDT 24 |
Finished | Jul 11 06:05:43 PM PDT 24 |
Peak memory | 265100 kb |
Host | smart-9b5c7756-9c62-4aef-b309-1dc1f4ffebba |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236522631 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.236522631 |
Directory | /workspace/38.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_stress_all.3109268661 |
Short name | T944 |
Test name | |
Test status | |
Simulation time | 104428390508 ps |
CPU time | 2661.04 seconds |
Started | Jul 11 06:05:25 PM PDT 24 |
Finished | Jul 11 06:49:49 PM PDT 24 |
Peak memory | 377752 kb |
Host | smart-e17d846c-99e7-45c1-a65c-bb0925d7852c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109268661 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 38.sram_ctrl_stress_all.3109268661 |
Directory | /workspace/38.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.83383793 |
Short name | T136 |
Test name | |
Test status | |
Simulation time | 1305696676 ps |
CPU time | 71.86 seconds |
Started | Jul 11 06:05:25 PM PDT 24 |
Finished | Jul 11 06:06:39 PM PDT 24 |
Peak memory | 298948 kb |
Host | smart-6a836811-7406-4671-8c1e-7b43e09e2d5c |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=83383793 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all_with_rand_reset.83383793 |
Directory | /workspace/38.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_stress_pipeline.2266969037 |
Short name | T463 |
Test name | |
Test status | |
Simulation time | 10618168529 ps |
CPU time | 311.51 seconds |
Started | Jul 11 06:05:18 PM PDT 24 |
Finished | Jul 11 06:10:31 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-078b67ef-a3db-4010-8dda-6d31e51a2347 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266969037 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 8.sram_ctrl_stress_pipeline.2266969037 |
Directory | /workspace/38.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.724806406 |
Short name | T671 |
Test name | |
Test status | |
Simulation time | 1438745537 ps |
CPU time | 17.94 seconds |
Started | Jul 11 06:05:19 PM PDT 24 |
Finished | Jul 11 06:05:40 PM PDT 24 |
Peak memory | 253792 kb |
Host | smart-b73d6a1a-e9a2-441c-a188-23ef2dc58d7f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724806406 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 38.sram_ctrl_throughput_w_partial_write.724806406 |
Directory | /workspace/38.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_access_during_key_req.2593394802 |
Short name | T623 |
Test name | |
Test status | |
Simulation time | 26780236848 ps |
CPU time | 612.01 seconds |
Started | Jul 11 06:05:25 PM PDT 24 |
Finished | Jul 11 06:15:39 PM PDT 24 |
Peak memory | 376072 kb |
Host | smart-d6c2be38-54f5-4296-9a1c-34bbe37b8a51 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593394802 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 39.sram_ctrl_access_during_key_req.2593394802 |
Directory | /workspace/39.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_alert_test.3936735991 |
Short name | T619 |
Test name | |
Test status | |
Simulation time | 14106024 ps |
CPU time | 0.68 seconds |
Started | Jul 11 06:05:30 PM PDT 24 |
Finished | Jul 11 06:05:32 PM PDT 24 |
Peak memory | 202396 kb |
Host | smart-c6ee484f-60af-40f8-ab3c-1203b2354e80 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936735991 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_alert_test.3936735991 |
Directory | /workspace/39.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_bijection.1136159713 |
Short name | T628 |
Test name | |
Test status | |
Simulation time | 151327223816 ps |
CPU time | 2341.62 seconds |
Started | Jul 11 06:05:25 PM PDT 24 |
Finished | Jul 11 06:44:29 PM PDT 24 |
Peak memory | 203592 kb |
Host | smart-f3a0a2ba-eb80-4020-a353-880665e29a39 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136159713 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection .1136159713 |
Directory | /workspace/39.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_executable.1998556870 |
Short name | T367 |
Test name | |
Test status | |
Simulation time | 259964134725 ps |
CPU time | 1291.5 seconds |
Started | Jul 11 06:05:30 PM PDT 24 |
Finished | Jul 11 06:27:03 PM PDT 24 |
Peak memory | 379708 kb |
Host | smart-9a19b137-c646-4719-bbdd-7307263ca8c1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998556870 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executab le.1998556870 |
Directory | /workspace/39.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_lc_escalation.2729685740 |
Short name | T868 |
Test name | |
Test status | |
Simulation time | 8528326140 ps |
CPU time | 52.71 seconds |
Started | Jul 11 06:05:24 PM PDT 24 |
Finished | Jul 11 06:06:19 PM PDT 24 |
Peak memory | 215472 kb |
Host | smart-ccc3aec8-8176-471d-8cb1-d6a0a9b5fc10 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729685740 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_es calation.2729685740 |
Directory | /workspace/39.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_max_throughput.3880474307 |
Short name | T465 |
Test name | |
Test status | |
Simulation time | 1498927150 ps |
CPU time | 30.29 seconds |
Started | Jul 11 06:05:32 PM PDT 24 |
Finished | Jul 11 06:06:04 PM PDT 24 |
Peak memory | 289640 kb |
Host | smart-d62efc4d-ef2f-4cd4-98c8-b02a899d9243 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880474307 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 39.sram_ctrl_max_throughput.3880474307 |
Directory | /workspace/39.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_mem_partial_access.3282838265 |
Short name | T58 |
Test name | |
Test status | |
Simulation time | 25222507319 ps |
CPU time | 182.25 seconds |
Started | Jul 11 06:05:28 PM PDT 24 |
Finished | Jul 11 06:08:32 PM PDT 24 |
Peak memory | 211084 kb |
Host | smart-6fdbb115-f0cf-4dea-a35e-0b5899f4eb39 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282838265 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 9.sram_ctrl_mem_partial_access.3282838265 |
Directory | /workspace/39.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_mem_walk.886162568 |
Short name | T245 |
Test name | |
Test status | |
Simulation time | 10506445671 ps |
CPU time | 294.28 seconds |
Started | Jul 11 06:05:29 PM PDT 24 |
Finished | Jul 11 06:10:25 PM PDT 24 |
Peak memory | 211056 kb |
Host | smart-52edd1b4-0109-461d-8023-41e643e1ccfc |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886162568 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl _mem_walk.886162568 |
Directory | /workspace/39.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_multiple_keys.2359923645 |
Short name | T223 |
Test name | |
Test status | |
Simulation time | 11815561901 ps |
CPU time | 684.66 seconds |
Started | Jul 11 06:05:23 PM PDT 24 |
Finished | Jul 11 06:16:50 PM PDT 24 |
Peak memory | 374956 kb |
Host | smart-df540f37-3d18-4952-b5c5-482c98059e7c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359923645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multi ple_keys.2359923645 |
Directory | /workspace/39.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_partial_access.97047196 |
Short name | T744 |
Test name | |
Test status | |
Simulation time | 13828124920 ps |
CPU time | 148.16 seconds |
Started | Jul 11 06:05:32 PM PDT 24 |
Finished | Jul 11 06:08:02 PM PDT 24 |
Peak memory | 361136 kb |
Host | smart-a3684023-6c73-4b7e-8404-82f50e8fcb74 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97047196 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sr am_ctrl_partial_access.97047196 |
Directory | /workspace/39.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.954345234 |
Short name | T421 |
Test name | |
Test status | |
Simulation time | 207691732683 ps |
CPU time | 463.52 seconds |
Started | Jul 11 06:05:32 PM PDT 24 |
Finished | Jul 11 06:13:17 PM PDT 24 |
Peak memory | 202656 kb |
Host | smart-55cb8441-27fd-4200-b14c-9212278c801a |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954345234 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 39.sram_ctrl_partial_access_b2b.954345234 |
Directory | /workspace/39.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_ram_cfg.742704181 |
Short name | T752 |
Test name | |
Test status | |
Simulation time | 402392897 ps |
CPU time | 3.24 seconds |
Started | Jul 11 06:05:32 PM PDT 24 |
Finished | Jul 11 06:05:37 PM PDT 24 |
Peak memory | 202828 kb |
Host | smart-da812a70-081f-4988-8a9a-42319537edfe |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742704181 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.742704181 |
Directory | /workspace/39.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_regwen.1142324876 |
Short name | T161 |
Test name | |
Test status | |
Simulation time | 16463782541 ps |
CPU time | 831.68 seconds |
Started | Jul 11 06:05:30 PM PDT 24 |
Finished | Jul 11 06:19:24 PM PDT 24 |
Peak memory | 381692 kb |
Host | smart-67946789-2c8d-474e-87e6-dd7dbafd13f9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142324876 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.1142324876 |
Directory | /workspace/39.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_smoke.2499180345 |
Short name | T871 |
Test name | |
Test status | |
Simulation time | 957591502 ps |
CPU time | 17.16 seconds |
Started | Jul 11 06:05:25 PM PDT 24 |
Finished | Jul 11 06:05:45 PM PDT 24 |
Peak memory | 202784 kb |
Host | smart-99d7ec3b-49ba-4746-a1f8-ff2e63a1f728 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499180345 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.2499180345 |
Directory | /workspace/39.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_stress_all.1082887373 |
Short name | T635 |
Test name | |
Test status | |
Simulation time | 38804292089 ps |
CPU time | 3056.54 seconds |
Started | Jul 11 06:05:30 PM PDT 24 |
Finished | Jul 11 06:56:28 PM PDT 24 |
Peak memory | 382840 kb |
Host | smart-7b7028c4-dbb8-4376-860f-1ba0fa8309ad |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082887373 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 39.sram_ctrl_stress_all.1082887373 |
Directory | /workspace/39.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.1346946586 |
Short name | T69 |
Test name | |
Test status | |
Simulation time | 24218242022 ps |
CPU time | 36.51 seconds |
Started | Jul 11 06:05:29 PM PDT 24 |
Finished | Jul 11 06:06:07 PM PDT 24 |
Peak memory | 211176 kb |
Host | smart-e135b46b-1986-4e9a-b85f-2cd4b2eee671 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1346946586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all_with_rand_reset.1346946586 |
Directory | /workspace/39.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_stress_pipeline.2334884521 |
Short name | T579 |
Test name | |
Test status | |
Simulation time | 6111102160 ps |
CPU time | 172.04 seconds |
Started | Jul 11 06:05:25 PM PDT 24 |
Finished | Jul 11 06:08:19 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-1aba712f-50dd-4d0b-84d2-430a78354527 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334884521 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 9.sram_ctrl_stress_pipeline.2334884521 |
Directory | /workspace/39.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.4077609362 |
Short name | T802 |
Test name | |
Test status | |
Simulation time | 2554943207 ps |
CPU time | 26.6 seconds |
Started | Jul 11 06:05:45 PM PDT 24 |
Finished | Jul 11 06:06:14 PM PDT 24 |
Peak memory | 273360 kb |
Host | smart-a15b6c95-b607-4366-89ce-ee72ce142019 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077609362 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 39.sram_ctrl_throughput_w_partial_write.4077609362 |
Directory | /workspace/39.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_access_during_key_req.231490379 |
Short name | T539 |
Test name | |
Test status | |
Simulation time | 12529788815 ps |
CPU time | 694.82 seconds |
Started | Jul 11 06:03:04 PM PDT 24 |
Finished | Jul 11 06:14:57 PM PDT 24 |
Peak memory | 378672 kb |
Host | smart-3efe77df-5cda-4022-96eb-18a471f187af |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231490379 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 4.sram_ctrl_access_during_key_req.231490379 |
Directory | /workspace/4.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_alert_test.2332916991 |
Short name | T119 |
Test name | |
Test status | |
Simulation time | 14309633 ps |
CPU time | 0.66 seconds |
Started | Jul 11 06:03:06 PM PDT 24 |
Finished | Jul 11 06:03:24 PM PDT 24 |
Peak memory | 202568 kb |
Host | smart-ae425b6b-3a7b-4c1c-87e1-195243a9f860 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332916991 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_alert_test.2332916991 |
Directory | /workspace/4.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_bijection.1170144556 |
Short name | T218 |
Test name | |
Test status | |
Simulation time | 111793467504 ps |
CPU time | 1778.01 seconds |
Started | Jul 11 06:03:06 PM PDT 24 |
Finished | Jul 11 06:33:01 PM PDT 24 |
Peak memory | 203940 kb |
Host | smart-40e585cf-a844-47c1-ae0f-e85cd1da8b7f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170144556 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection. 1170144556 |
Directory | /workspace/4.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_executable.730670483 |
Short name | T707 |
Test name | |
Test status | |
Simulation time | 65314234909 ps |
CPU time | 946.81 seconds |
Started | Jul 11 06:03:06 PM PDT 24 |
Finished | Jul 11 06:19:10 PM PDT 24 |
Peak memory | 373684 kb |
Host | smart-24d18437-cf31-408b-a91a-087a11894e5b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730670483 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executable .730670483 |
Directory | /workspace/4.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_lc_escalation.767732003 |
Short name | T629 |
Test name | |
Test status | |
Simulation time | 14817831043 ps |
CPU time | 89.01 seconds |
Started | Jul 11 06:03:06 PM PDT 24 |
Finished | Jul 11 06:04:52 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-d8d9aad6-e2b4-4de5-9d4b-8285a52d901b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767732003 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_esca lation.767732003 |
Directory | /workspace/4.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_max_throughput.2089745661 |
Short name | T335 |
Test name | |
Test status | |
Simulation time | 1431715903 ps |
CPU time | 11.69 seconds |
Started | Jul 11 06:03:04 PM PDT 24 |
Finished | Jul 11 06:03:34 PM PDT 24 |
Peak memory | 235480 kb |
Host | smart-b6c3881e-e9f6-4a33-a034-6d516d784cd6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089745661 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 4.sram_ctrl_max_throughput.2089745661 |
Directory | /workspace/4.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_mem_partial_access.3763990784 |
Short name | T776 |
Test name | |
Test status | |
Simulation time | 2693223723 ps |
CPU time | 82.93 seconds |
Started | Jul 11 06:03:03 PM PDT 24 |
Finished | Jul 11 06:04:44 PM PDT 24 |
Peak memory | 210964 kb |
Host | smart-a76dfebd-5f04-4c52-b3e1-f798259153d2 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763990784 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 .sram_ctrl_mem_partial_access.3763990784 |
Directory | /workspace/4.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_mem_walk.909108638 |
Short name | T466 |
Test name | |
Test status | |
Simulation time | 6932274601 ps |
CPU time | 163.03 seconds |
Started | Jul 11 06:03:10 PM PDT 24 |
Finished | Jul 11 06:06:09 PM PDT 24 |
Peak memory | 211008 kb |
Host | smart-5bd7bb82-2fab-4c09-9de6-8bfd1b3c9bb4 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909108638 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ mem_walk.909108638 |
Directory | /workspace/4.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_multiple_keys.1195732624 |
Short name | T639 |
Test name | |
Test status | |
Simulation time | 7972025408 ps |
CPU time | 1037.2 seconds |
Started | Jul 11 06:03:09 PM PDT 24 |
Finished | Jul 11 06:20:43 PM PDT 24 |
Peak memory | 374620 kb |
Host | smart-4ac2b178-bd80-4f02-9ed6-53c6f81fb661 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195732624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multip le_keys.1195732624 |
Directory | /workspace/4.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_partial_access.2645546868 |
Short name | T35 |
Test name | |
Test status | |
Simulation time | 1223369048 ps |
CPU time | 98.48 seconds |
Started | Jul 11 06:03:14 PM PDT 24 |
Finished | Jul 11 06:05:08 PM PDT 24 |
Peak memory | 339864 kb |
Host | smart-1ceec8dc-33a1-404b-a744-5f4d31641649 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645546868 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.s ram_ctrl_partial_access.2645546868 |
Directory | /workspace/4.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.3579075816 |
Short name | T320 |
Test name | |
Test status | |
Simulation time | 13257427960 ps |
CPU time | 378.75 seconds |
Started | Jul 11 06:03:04 PM PDT 24 |
Finished | Jul 11 06:09:41 PM PDT 24 |
Peak memory | 202868 kb |
Host | smart-8103da74-70cc-4b9c-b27a-e6c94495f945 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579075816 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 4.sram_ctrl_partial_access_b2b.3579075816 |
Directory | /workspace/4.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_ram_cfg.4099273335 |
Short name | T851 |
Test name | |
Test status | |
Simulation time | 1405036368 ps |
CPU time | 3.23 seconds |
Started | Jul 11 06:03:24 PM PDT 24 |
Finished | Jul 11 06:03:40 PM PDT 24 |
Peak memory | 202836 kb |
Host | smart-e01148f0-984e-4120-ab4c-7c62339b8c97 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099273335 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.4099273335 |
Directory | /workspace/4.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_regwen.977212255 |
Short name | T820 |
Test name | |
Test status | |
Simulation time | 15987839114 ps |
CPU time | 694.86 seconds |
Started | Jul 11 06:03:26 PM PDT 24 |
Finished | Jul 11 06:15:13 PM PDT 24 |
Peak memory | 355212 kb |
Host | smart-98655ce0-8503-4a35-9904-33a3db38580c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977212255 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.977212255 |
Directory | /workspace/4.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_sec_cm.2566878808 |
Short name | T16 |
Test name | |
Test status | |
Simulation time | 196106503 ps |
CPU time | 1.96 seconds |
Started | Jul 11 06:03:08 PM PDT 24 |
Finished | Jul 11 06:03:27 PM PDT 24 |
Peak memory | 222668 kb |
Host | smart-37812534-dcf6-49f3-abd8-391ef54a0629 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566878808 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_sec_cm.2566878808 |
Directory | /workspace/4.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_smoke.712900088 |
Short name | T451 |
Test name | |
Test status | |
Simulation time | 1988258616 ps |
CPU time | 3.91 seconds |
Started | Jul 11 06:03:06 PM PDT 24 |
Finished | Jul 11 06:03:27 PM PDT 24 |
Peak memory | 202836 kb |
Host | smart-f72e393d-3411-4216-9a5b-498926390a55 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712900088 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.712900088 |
Directory | /workspace/4.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_stress_all.2998511040 |
Short name | T751 |
Test name | |
Test status | |
Simulation time | 132258511163 ps |
CPU time | 4529.71 seconds |
Started | Jul 11 06:03:24 PM PDT 24 |
Finished | Jul 11 07:19:07 PM PDT 24 |
Peak memory | 381808 kb |
Host | smart-d6f9d498-5625-4765-b949-31104c0e5218 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998511040 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 4.sram_ctrl_stress_all.2998511040 |
Directory | /workspace/4.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.2943706646 |
Short name | T849 |
Test name | |
Test status | |
Simulation time | 2438189539 ps |
CPU time | 190.89 seconds |
Started | Jul 11 06:03:10 PM PDT 24 |
Finished | Jul 11 06:06:36 PM PDT 24 |
Peak memory | 376808 kb |
Host | smart-c3cac50f-8d3d-4574-a91f-4e8e1c6debc1 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2943706646 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all_with_rand_reset.2943706646 |
Directory | /workspace/4.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_stress_pipeline.2388604841 |
Short name | T812 |
Test name | |
Test status | |
Simulation time | 14116834143 ps |
CPU time | 240.62 seconds |
Started | Jul 11 06:03:02 PM PDT 24 |
Finished | Jul 11 06:07:21 PM PDT 24 |
Peak memory | 202872 kb |
Host | smart-65495f64-ccd5-4ddf-9100-d7f7015dce0f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388604841 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 .sram_ctrl_stress_pipeline.2388604841 |
Directory | /workspace/4.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.178087037 |
Short name | T385 |
Test name | |
Test status | |
Simulation time | 3231687906 ps |
CPU time | 133.41 seconds |
Started | Jul 11 06:03:14 PM PDT 24 |
Finished | Jul 11 06:05:43 PM PDT 24 |
Peak memory | 364252 kb |
Host | smart-53a7b3bd-6eaa-4ec7-9133-edbde5ed6a77 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178087037 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 4.sram_ctrl_throughput_w_partial_write.178087037 |
Directory | /workspace/4.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_access_during_key_req.3281866520 |
Short name | T508 |
Test name | |
Test status | |
Simulation time | 230005610994 ps |
CPU time | 1945.23 seconds |
Started | Jul 11 06:05:46 PM PDT 24 |
Finished | Jul 11 06:38:14 PM PDT 24 |
Peak memory | 378712 kb |
Host | smart-1f3d2183-f36b-489e-ae01-df76fc810c53 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281866520 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 40.sram_ctrl_access_during_key_req.3281866520 |
Directory | /workspace/40.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_alert_test.1638666398 |
Short name | T507 |
Test name | |
Test status | |
Simulation time | 23878272 ps |
CPU time | 0.67 seconds |
Started | Jul 11 06:05:44 PM PDT 24 |
Finished | Jul 11 06:05:47 PM PDT 24 |
Peak memory | 202440 kb |
Host | smart-3a9bd844-ab40-4058-a0f5-917b881a1e47 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638666398 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_alert_test.1638666398 |
Directory | /workspace/40.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_bijection.3402099071 |
Short name | T714 |
Test name | |
Test status | |
Simulation time | 78346430255 ps |
CPU time | 1819.94 seconds |
Started | Jul 11 06:05:44 PM PDT 24 |
Finished | Jul 11 06:36:06 PM PDT 24 |
Peak memory | 203156 kb |
Host | smart-64c38991-adec-4977-a837-f06c0bb5a890 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402099071 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection .3402099071 |
Directory | /workspace/40.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_executable.3949524938 |
Short name | T423 |
Test name | |
Test status | |
Simulation time | 37496330508 ps |
CPU time | 606.88 seconds |
Started | Jul 11 06:05:43 PM PDT 24 |
Finished | Jul 11 06:15:52 PM PDT 24 |
Peak memory | 372544 kb |
Host | smart-afc17f5a-eaf9-496b-83a8-daad72972a9b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949524938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executab le.3949524938 |
Directory | /workspace/40.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_lc_escalation.3237916152 |
Short name | T37 |
Test name | |
Test status | |
Simulation time | 63543385920 ps |
CPU time | 82.51 seconds |
Started | Jul 11 06:05:49 PM PDT 24 |
Finished | Jul 11 06:07:14 PM PDT 24 |
Peak memory | 202928 kb |
Host | smart-e1304d4f-b18d-40b1-8b21-2f82e95c8159 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237916152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_es calation.3237916152 |
Directory | /workspace/40.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_max_throughput.322095485 |
Short name | T378 |
Test name | |
Test status | |
Simulation time | 1475804245 ps |
CPU time | 21.92 seconds |
Started | Jul 11 06:05:46 PM PDT 24 |
Finished | Jul 11 06:06:10 PM PDT 24 |
Peak memory | 269168 kb |
Host | smart-f248f477-3d35-4918-b3e2-ceb2ea8e702d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322095485 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 40.sram_ctrl_max_throughput.322095485 |
Directory | /workspace/40.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_mem_partial_access.1027892460 |
Short name | T789 |
Test name | |
Test status | |
Simulation time | 6549642714 ps |
CPU time | 128.87 seconds |
Started | Jul 11 06:05:47 PM PDT 24 |
Finished | Jul 11 06:07:58 PM PDT 24 |
Peak memory | 211092 kb |
Host | smart-1edc0d44-2a17-48cc-b653-40a587abaf69 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027892460 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 0.sram_ctrl_mem_partial_access.1027892460 |
Directory | /workspace/40.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_mem_walk.798506249 |
Short name | T52 |
Test name | |
Test status | |
Simulation time | 27244510051 ps |
CPU time | 340.91 seconds |
Started | Jul 11 06:05:43 PM PDT 24 |
Finished | Jul 11 06:11:25 PM PDT 24 |
Peak memory | 211008 kb |
Host | smart-00ee7927-82b7-4ad7-9d15-2f45ad08cd4d |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798506249 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl _mem_walk.798506249 |
Directory | /workspace/40.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_multiple_keys.2384713484 |
Short name | T268 |
Test name | |
Test status | |
Simulation time | 33236948730 ps |
CPU time | 665.86 seconds |
Started | Jul 11 06:05:30 PM PDT 24 |
Finished | Jul 11 06:16:38 PM PDT 24 |
Peak memory | 381840 kb |
Host | smart-b7070e8e-bf19-4c04-81da-8c686a0db42f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384713484 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multi ple_keys.2384713484 |
Directory | /workspace/40.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_partial_access.364307965 |
Short name | T798 |
Test name | |
Test status | |
Simulation time | 4216656946 ps |
CPU time | 14.94 seconds |
Started | Jul 11 06:05:43 PM PDT 24 |
Finished | Jul 11 06:05:59 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-824d7dac-df49-4d5a-8779-4b8e917c9676 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364307965 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.s ram_ctrl_partial_access.364307965 |
Directory | /workspace/40.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.468013486 |
Short name | T771 |
Test name | |
Test status | |
Simulation time | 17467042605 ps |
CPU time | 426 seconds |
Started | Jul 11 06:05:43 PM PDT 24 |
Finished | Jul 11 06:12:51 PM PDT 24 |
Peak memory | 202820 kb |
Host | smart-c88ea443-2d6b-4096-8c4e-9d5accb62eec |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468013486 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 40.sram_ctrl_partial_access_b2b.468013486 |
Directory | /workspace/40.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_ram_cfg.2069102437 |
Short name | T231 |
Test name | |
Test status | |
Simulation time | 698230357 ps |
CPU time | 3.48 seconds |
Started | Jul 11 06:05:45 PM PDT 24 |
Finished | Jul 11 06:05:50 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-4ab26d08-50e4-48b5-9137-6235b8bd60a5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069102437 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.2069102437 |
Directory | /workspace/40.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_regwen.1899177160 |
Short name | T477 |
Test name | |
Test status | |
Simulation time | 35591550824 ps |
CPU time | 1066.42 seconds |
Started | Jul 11 06:05:45 PM PDT 24 |
Finished | Jul 11 06:23:33 PM PDT 24 |
Peak memory | 380816 kb |
Host | smart-5e609cc0-117a-4722-a813-aa017211de12 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899177160 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.1899177160 |
Directory | /workspace/40.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_smoke.1708169384 |
Short name | T435 |
Test name | |
Test status | |
Simulation time | 402513652 ps |
CPU time | 32.27 seconds |
Started | Jul 11 06:05:30 PM PDT 24 |
Finished | Jul 11 06:06:04 PM PDT 24 |
Peak memory | 291236 kb |
Host | smart-8a9c000e-891a-4305-9a04-8f84dbc072a8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708169384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.1708169384 |
Directory | /workspace/40.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.1180018476 |
Short name | T26 |
Test name | |
Test status | |
Simulation time | 286835260 ps |
CPU time | 11.52 seconds |
Started | Jul 11 06:05:44 PM PDT 24 |
Finished | Jul 11 06:05:58 PM PDT 24 |
Peak memory | 212652 kb |
Host | smart-f8ea3c94-474e-4558-940a-72a2d779e69f |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1180018476 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all_with_rand_reset.1180018476 |
Directory | /workspace/40.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_stress_pipeline.1250514242 |
Short name | T923 |
Test name | |
Test status | |
Simulation time | 69982046784 ps |
CPU time | 270.34 seconds |
Started | Jul 11 06:05:45 PM PDT 24 |
Finished | Jul 11 06:10:18 PM PDT 24 |
Peak memory | 202836 kb |
Host | smart-dbbce84d-0933-4160-adc3-2e1ad989ac44 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250514242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 0.sram_ctrl_stress_pipeline.1250514242 |
Directory | /workspace/40.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.2081311889 |
Short name | T607 |
Test name | |
Test status | |
Simulation time | 3003443114 ps |
CPU time | 61.22 seconds |
Started | Jul 11 06:05:43 PM PDT 24 |
Finished | Jul 11 06:06:45 PM PDT 24 |
Peak memory | 318500 kb |
Host | smart-c2a2e2e8-f186-48cf-9752-a91d2b858629 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081311889 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 40.sram_ctrl_throughput_w_partial_write.2081311889 |
Directory | /workspace/40.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_access_during_key_req.3815858311 |
Short name | T455 |
Test name | |
Test status | |
Simulation time | 2043350773 ps |
CPU time | 261.8 seconds |
Started | Jul 11 06:05:45 PM PDT 24 |
Finished | Jul 11 06:10:09 PM PDT 24 |
Peak memory | 359796 kb |
Host | smart-b0eb7d2f-6f95-4af5-9c50-2a72b9921378 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815858311 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 41.sram_ctrl_access_during_key_req.3815858311 |
Directory | /workspace/41.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_alert_test.2271800057 |
Short name | T288 |
Test name | |
Test status | |
Simulation time | 59596317 ps |
CPU time | 0.68 seconds |
Started | Jul 11 06:05:49 PM PDT 24 |
Finished | Jul 11 06:05:51 PM PDT 24 |
Peak memory | 202328 kb |
Host | smart-4df29366-bdae-4656-8223-264c20979c9e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271800057 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_alert_test.2271800057 |
Directory | /workspace/41.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_bijection.1857583359 |
Short name | T611 |
Test name | |
Test status | |
Simulation time | 46465140693 ps |
CPU time | 850 seconds |
Started | Jul 11 06:05:47 PM PDT 24 |
Finished | Jul 11 06:19:59 PM PDT 24 |
Peak memory | 203504 kb |
Host | smart-59bdec43-f4f3-4de9-a76e-9c672fc06db7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857583359 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection .1857583359 |
Directory | /workspace/41.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_executable.1177423655 |
Short name | T729 |
Test name | |
Test status | |
Simulation time | 59349639944 ps |
CPU time | 1072.08 seconds |
Started | Jul 11 06:05:45 PM PDT 24 |
Finished | Jul 11 06:23:39 PM PDT 24 |
Peak memory | 375636 kb |
Host | smart-693756d3-d5b9-435e-a0cc-08dbccbc1e8a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177423655 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_executab le.1177423655 |
Directory | /workspace/41.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_lc_escalation.3087466439 |
Short name | T22 |
Test name | |
Test status | |
Simulation time | 9422544969 ps |
CPU time | 27.28 seconds |
Started | Jul 11 06:05:45 PM PDT 24 |
Finished | Jul 11 06:06:15 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-0e422e9f-358e-41c4-8597-9671ed222a4f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087466439 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_es calation.3087466439 |
Directory | /workspace/41.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_max_throughput.4265540510 |
Short name | T441 |
Test name | |
Test status | |
Simulation time | 731324926 ps |
CPU time | 45.33 seconds |
Started | Jul 11 06:05:45 PM PDT 24 |
Finished | Jul 11 06:06:33 PM PDT 24 |
Peak memory | 306264 kb |
Host | smart-36f28ff6-a616-419d-8009-3819dc05dff0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265540510 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 41.sram_ctrl_max_throughput.4265540510 |
Directory | /workspace/41.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_mem_partial_access.410793034 |
Short name | T853 |
Test name | |
Test status | |
Simulation time | 1638552459 ps |
CPU time | 128.37 seconds |
Started | Jul 11 06:05:49 PM PDT 24 |
Finished | Jul 11 06:08:00 PM PDT 24 |
Peak memory | 219096 kb |
Host | smart-a0bdde54-56c8-421b-957b-7c5a6ee47527 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410793034 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41 .sram_ctrl_mem_partial_access.410793034 |
Directory | /workspace/41.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_mem_walk.1573950037 |
Short name | T295 |
Test name | |
Test status | |
Simulation time | 21884482999 ps |
CPU time | 301.56 seconds |
Started | Jul 11 06:05:47 PM PDT 24 |
Finished | Jul 11 06:10:51 PM PDT 24 |
Peak memory | 211020 kb |
Host | smart-fc04bcaa-678b-4bfd-b089-feb1aab0926c |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573950037 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctr l_mem_walk.1573950037 |
Directory | /workspace/41.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_multiple_keys.3999369771 |
Short name | T756 |
Test name | |
Test status | |
Simulation time | 25119043070 ps |
CPU time | 1791.06 seconds |
Started | Jul 11 06:05:45 PM PDT 24 |
Finished | Jul 11 06:35:39 PM PDT 24 |
Peak memory | 380896 kb |
Host | smart-95dbabd3-62aa-481a-92a1-bb0f2ccad1bc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999369771 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multi ple_keys.3999369771 |
Directory | /workspace/41.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_partial_access.2364291844 |
Short name | T559 |
Test name | |
Test status | |
Simulation time | 693635904 ps |
CPU time | 6.15 seconds |
Started | Jul 11 06:05:41 PM PDT 24 |
Finished | Jul 11 06:05:48 PM PDT 24 |
Peak memory | 202648 kb |
Host | smart-8ca6cd68-83d9-4280-9986-b4045c39f9ae |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364291844 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41. sram_ctrl_partial_access.2364291844 |
Directory | /workspace/41.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.2416264320 |
Short name | T118 |
Test name | |
Test status | |
Simulation time | 14948063433 ps |
CPU time | 171.22 seconds |
Started | Jul 11 06:05:44 PM PDT 24 |
Finished | Jul 11 06:08:37 PM PDT 24 |
Peak memory | 203044 kb |
Host | smart-26b07887-35ef-4670-a118-b49b4049b70f |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416264320 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 41.sram_ctrl_partial_access_b2b.2416264320 |
Directory | /workspace/41.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_ram_cfg.3387200914 |
Short name | T761 |
Test name | |
Test status | |
Simulation time | 2598744823 ps |
CPU time | 4 seconds |
Started | Jul 11 06:05:43 PM PDT 24 |
Finished | Jul 11 06:05:50 PM PDT 24 |
Peak memory | 202852 kb |
Host | smart-d22a0a9c-f5e2-4142-84a9-f1cb71d8b660 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387200914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.3387200914 |
Directory | /workspace/41.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_regwen.2769183371 |
Short name | T819 |
Test name | |
Test status | |
Simulation time | 14552683088 ps |
CPU time | 135.98 seconds |
Started | Jul 11 06:05:46 PM PDT 24 |
Finished | Jul 11 06:08:04 PM PDT 24 |
Peak memory | 272312 kb |
Host | smart-199e6be3-01e5-4c8d-8768-ba051a5b39ef |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769183371 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.2769183371 |
Directory | /workspace/41.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_smoke.1367247336 |
Short name | T880 |
Test name | |
Test status | |
Simulation time | 420588914 ps |
CPU time | 8.75 seconds |
Started | Jul 11 06:05:43 PM PDT 24 |
Finished | Jul 11 06:05:53 PM PDT 24 |
Peak memory | 202820 kb |
Host | smart-6ded3268-6fe1-4a1b-9901-dc605affa8bd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367247336 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.1367247336 |
Directory | /workspace/41.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_stress_all.2175222756 |
Short name | T434 |
Test name | |
Test status | |
Simulation time | 15473661023 ps |
CPU time | 337.03 seconds |
Started | Jul 11 06:05:49 PM PDT 24 |
Finished | Jul 11 06:11:28 PM PDT 24 |
Peak memory | 379800 kb |
Host | smart-b75ecd74-e724-4ca9-91ba-11dd0a6b2c78 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175222756 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 41.sram_ctrl_stress_all.2175222756 |
Directory | /workspace/41.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.1984606027 |
Short name | T626 |
Test name | |
Test status | |
Simulation time | 1468862091 ps |
CPU time | 175.91 seconds |
Started | Jul 11 06:05:50 PM PDT 24 |
Finished | Jul 11 06:08:49 PM PDT 24 |
Peak memory | 374016 kb |
Host | smart-3551e3e2-d714-49fb-bb7c-6303f6b31b29 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1984606027 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all_with_rand_reset.1984606027 |
Directory | /workspace/41.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_stress_pipeline.457665190 |
Short name | T241 |
Test name | |
Test status | |
Simulation time | 35383951154 ps |
CPU time | 253.2 seconds |
Started | Jul 11 06:05:45 PM PDT 24 |
Finished | Jul 11 06:10:00 PM PDT 24 |
Peak memory | 202872 kb |
Host | smart-b164c5f1-0280-4a69-b92b-11b3caf568d7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457665190 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41 .sram_ctrl_stress_pipeline.457665190 |
Directory | /workspace/41.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.3385702801 |
Short name | T190 |
Test name | |
Test status | |
Simulation time | 1510550441 ps |
CPU time | 39.17 seconds |
Started | Jul 11 06:05:43 PM PDT 24 |
Finished | Jul 11 06:06:24 PM PDT 24 |
Peak memory | 284580 kb |
Host | smart-ceec76a7-b9e3-4aa8-aefa-5b06a15a70d8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385702801 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 41.sram_ctrl_throughput_w_partial_write.3385702801 |
Directory | /workspace/41.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_access_during_key_req.1726938264 |
Short name | T44 |
Test name | |
Test status | |
Simulation time | 10946321040 ps |
CPU time | 1234.53 seconds |
Started | Jul 11 06:05:50 PM PDT 24 |
Finished | Jul 11 06:26:28 PM PDT 24 |
Peak memory | 379760 kb |
Host | smart-48ceee8a-ac28-4b13-8d82-fee8cddf68cc |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726938264 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 42.sram_ctrl_access_during_key_req.1726938264 |
Directory | /workspace/42.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_alert_test.2282842788 |
Short name | T296 |
Test name | |
Test status | |
Simulation time | 29459684 ps |
CPU time | 0.67 seconds |
Started | Jul 11 06:05:57 PM PDT 24 |
Finished | Jul 11 06:05:59 PM PDT 24 |
Peak memory | 202408 kb |
Host | smart-3424ddbe-5c96-4911-b0a3-c088332a44dd |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282842788 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_alert_test.2282842788 |
Directory | /workspace/42.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_bijection.1864286585 |
Short name | T616 |
Test name | |
Test status | |
Simulation time | 12140719284 ps |
CPU time | 842.95 seconds |
Started | Jul 11 06:05:50 PM PDT 24 |
Finished | Jul 11 06:19:56 PM PDT 24 |
Peak memory | 203088 kb |
Host | smart-e6138537-821e-43f0-8ead-99e5cf95edc9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864286585 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection .1864286585 |
Directory | /workspace/42.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_executable.4072842947 |
Short name | T555 |
Test name | |
Test status | |
Simulation time | 8518216482 ps |
CPU time | 299.88 seconds |
Started | Jul 11 06:05:51 PM PDT 24 |
Finished | Jul 11 06:10:54 PM PDT 24 |
Peak memory | 321476 kb |
Host | smart-d0b212bf-fb80-4718-85ae-fa84f62c3573 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072842947 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executab le.4072842947 |
Directory | /workspace/42.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_lc_escalation.1134655541 |
Short name | T251 |
Test name | |
Test status | |
Simulation time | 5849772488 ps |
CPU time | 18.53 seconds |
Started | Jul 11 06:05:51 PM PDT 24 |
Finished | Jul 11 06:06:12 PM PDT 24 |
Peak memory | 211120 kb |
Host | smart-19441e3b-e875-47a8-8266-106d171af284 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134655541 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_es calation.1134655541 |
Directory | /workspace/42.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_max_throughput.3171754669 |
Short name | T586 |
Test name | |
Test status | |
Simulation time | 3186657407 ps |
CPU time | 101.24 seconds |
Started | Jul 11 06:05:50 PM PDT 24 |
Finished | Jul 11 06:07:35 PM PDT 24 |
Peak memory | 370540 kb |
Host | smart-d002eda9-548a-4b3f-a391-0fe0df52035c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171754669 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 42.sram_ctrl_max_throughput.3171754669 |
Directory | /workspace/42.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_mem_partial_access.1598889511 |
Short name | T857 |
Test name | |
Test status | |
Simulation time | 5691767998 ps |
CPU time | 180.73 seconds |
Started | Jul 11 06:05:55 PM PDT 24 |
Finished | Jul 11 06:08:57 PM PDT 24 |
Peak memory | 211096 kb |
Host | smart-aa8ae778-f687-4fe7-9904-2f3099179463 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598889511 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 2.sram_ctrl_mem_partial_access.1598889511 |
Directory | /workspace/42.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_mem_walk.376443343 |
Short name | T834 |
Test name | |
Test status | |
Simulation time | 81370023037 ps |
CPU time | 322.6 seconds |
Started | Jul 11 06:05:55 PM PDT 24 |
Finished | Jul 11 06:11:20 PM PDT 24 |
Peak memory | 210992 kb |
Host | smart-074abe37-4d61-4ba2-82ce-eadb9241633f |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376443343 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl _mem_walk.376443343 |
Directory | /workspace/42.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_multiple_keys.3425113203 |
Short name | T249 |
Test name | |
Test status | |
Simulation time | 11831470094 ps |
CPU time | 183.04 seconds |
Started | Jul 11 06:05:46 PM PDT 24 |
Finished | Jul 11 06:08:52 PM PDT 24 |
Peak memory | 330368 kb |
Host | smart-7d6fa3a7-ef22-47fe-8c74-c3d7f41f5f13 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425113203 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multi ple_keys.3425113203 |
Directory | /workspace/42.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_partial_access.2193474435 |
Short name | T457 |
Test name | |
Test status | |
Simulation time | 1309599902 ps |
CPU time | 9.65 seconds |
Started | Jul 11 06:05:54 PM PDT 24 |
Finished | Jul 11 06:06:06 PM PDT 24 |
Peak memory | 202748 kb |
Host | smart-efee3a3c-ae55-4d80-bb9c-2e5c42445831 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193474435 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42. sram_ctrl_partial_access.2193474435 |
Directory | /workspace/42.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.654582293 |
Short name | T289 |
Test name | |
Test status | |
Simulation time | 24561414143 ps |
CPU time | 537.57 seconds |
Started | Jul 11 06:05:49 PM PDT 24 |
Finished | Jul 11 06:14:50 PM PDT 24 |
Peak memory | 202872 kb |
Host | smart-9c17cddd-d9aa-4a0a-952e-44ffbfdedc19 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654582293 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 42.sram_ctrl_partial_access_b2b.654582293 |
Directory | /workspace/42.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_ram_cfg.1050335253 |
Short name | T705 |
Test name | |
Test status | |
Simulation time | 1205448002 ps |
CPU time | 3.63 seconds |
Started | Jul 11 06:05:48 PM PDT 24 |
Finished | Jul 11 06:05:53 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-89e761c2-7ca4-4b41-81a8-34b11e3c00c3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050335253 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.1050335253 |
Directory | /workspace/42.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_regwen.4139738193 |
Short name | T937 |
Test name | |
Test status | |
Simulation time | 20810259350 ps |
CPU time | 1678 seconds |
Started | Jul 11 06:05:49 PM PDT 24 |
Finished | Jul 11 06:33:50 PM PDT 24 |
Peak memory | 377712 kb |
Host | smart-db2fc051-1802-40a1-bbba-5bf48d8e8f41 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139738193 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.4139738193 |
Directory | /workspace/42.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_smoke.1475541089 |
Short name | T593 |
Test name | |
Test status | |
Simulation time | 2683775098 ps |
CPU time | 10.01 seconds |
Started | Jul 11 06:05:49 PM PDT 24 |
Finished | Jul 11 06:06:02 PM PDT 24 |
Peak memory | 214188 kb |
Host | smart-ee1adb82-6985-43f3-894b-d7a0f0af8d56 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475541089 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.1475541089 |
Directory | /workspace/42.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_stress_all.3628944091 |
Short name | T840 |
Test name | |
Test status | |
Simulation time | 179584529452 ps |
CPU time | 3518.35 seconds |
Started | Jul 11 06:05:58 PM PDT 24 |
Finished | Jul 11 07:04:38 PM PDT 24 |
Peak memory | 378864 kb |
Host | smart-50430374-8174-4daa-bec8-d303e579a096 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628944091 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 42.sram_ctrl_stress_all.3628944091 |
Directory | /workspace/42.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.1057352380 |
Short name | T74 |
Test name | |
Test status | |
Simulation time | 1625288396 ps |
CPU time | 12.82 seconds |
Started | Jul 11 06:05:57 PM PDT 24 |
Finished | Jul 11 06:06:11 PM PDT 24 |
Peak memory | 211088 kb |
Host | smart-2371b378-5ec4-48ca-8460-4ef04df687de |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1057352380 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all_with_rand_reset.1057352380 |
Directory | /workspace/42.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_stress_pipeline.3289188963 |
Short name | T670 |
Test name | |
Test status | |
Simulation time | 15919174162 ps |
CPU time | 284.83 seconds |
Started | Jul 11 06:05:52 PM PDT 24 |
Finished | Jul 11 06:10:39 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-be3402b1-dddf-4065-a180-d26c9f819ade |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289188963 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 2.sram_ctrl_stress_pipeline.3289188963 |
Directory | /workspace/42.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.180444540 |
Short name | T220 |
Test name | |
Test status | |
Simulation time | 2704466404 ps |
CPU time | 100.38 seconds |
Started | Jul 11 06:05:51 PM PDT 24 |
Finished | Jul 11 06:07:34 PM PDT 24 |
Peak memory | 345976 kb |
Host | smart-891fe6f3-e1b8-4067-ad99-c387e3a794f7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180444540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 42.sram_ctrl_throughput_w_partial_write.180444540 |
Directory | /workspace/42.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_access_during_key_req.3256733424 |
Short name | T823 |
Test name | |
Test status | |
Simulation time | 8860103265 ps |
CPU time | 495.08 seconds |
Started | Jul 11 06:06:03 PM PDT 24 |
Finished | Jul 11 06:14:20 PM PDT 24 |
Peak memory | 359788 kb |
Host | smart-f6a6fa55-b3e9-4b0e-a154-adf7ac220496 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256733424 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 43.sram_ctrl_access_during_key_req.3256733424 |
Directory | /workspace/43.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_alert_test.1298163248 |
Short name | T551 |
Test name | |
Test status | |
Simulation time | 13213849 ps |
CPU time | 0.63 seconds |
Started | Jul 11 06:06:06 PM PDT 24 |
Finished | Jul 11 06:06:08 PM PDT 24 |
Peak memory | 202388 kb |
Host | smart-ccf6e760-0fd0-42b6-9b53-18f9a757f730 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298163248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_alert_test.1298163248 |
Directory | /workspace/43.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_executable.719620963 |
Short name | T232 |
Test name | |
Test status | |
Simulation time | 4389084769 ps |
CPU time | 130.2 seconds |
Started | Jul 11 06:06:01 PM PDT 24 |
Finished | Jul 11 06:08:13 PM PDT 24 |
Peak memory | 324324 kb |
Host | smart-9ab21cce-a0b8-42fb-b000-f54a5bcd43c1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719620963 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executabl e.719620963 |
Directory | /workspace/43.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_lc_escalation.2647999818 |
Short name | T208 |
Test name | |
Test status | |
Simulation time | 50999159954 ps |
CPU time | 66.39 seconds |
Started | Jul 11 06:05:55 PM PDT 24 |
Finished | Jul 11 06:07:03 PM PDT 24 |
Peak memory | 202904 kb |
Host | smart-5d24b7e8-e81e-4286-9488-d35c69a108bf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647999818 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_es calation.2647999818 |
Directory | /workspace/43.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_max_throughput.3075699070 |
Short name | T430 |
Test name | |
Test status | |
Simulation time | 3030920193 ps |
CPU time | 97.46 seconds |
Started | Jul 11 06:05:56 PM PDT 24 |
Finished | Jul 11 06:07:35 PM PDT 24 |
Peak memory | 356192 kb |
Host | smart-724d7791-458d-4968-b023-1dfa4540ae27 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075699070 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 43.sram_ctrl_max_throughput.3075699070 |
Directory | /workspace/43.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_mem_partial_access.1592695252 |
Short name | T101 |
Test name | |
Test status | |
Simulation time | 6624634298 ps |
CPU time | 125.04 seconds |
Started | Jul 11 06:11:46 PM PDT 24 |
Finished | Jul 11 06:13:57 PM PDT 24 |
Peak memory | 219120 kb |
Host | smart-315f6c18-3023-4475-b487-47e408848ab1 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592695252 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 3.sram_ctrl_mem_partial_access.1592695252 |
Directory | /workspace/43.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_mem_walk.3145509202 |
Short name | T894 |
Test name | |
Test status | |
Simulation time | 26272170142 ps |
CPU time | 268.61 seconds |
Started | Jul 11 06:06:02 PM PDT 24 |
Finished | Jul 11 06:10:31 PM PDT 24 |
Peak memory | 211000 kb |
Host | smart-df1fbc99-3fa3-4d8d-97bf-b905ef623755 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145509202 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctr l_mem_walk.3145509202 |
Directory | /workspace/43.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_multiple_keys.1587176126 |
Short name | T583 |
Test name | |
Test status | |
Simulation time | 11337150603 ps |
CPU time | 786.6 seconds |
Started | Jul 11 06:05:57 PM PDT 24 |
Finished | Jul 11 06:19:05 PM PDT 24 |
Peak memory | 375596 kb |
Host | smart-2f5df0d7-0f52-42d6-8e43-8424c9ee5e00 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587176126 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multi ple_keys.1587176126 |
Directory | /workspace/43.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_partial_access.2599649029 |
Short name | T33 |
Test name | |
Test status | |
Simulation time | 4336505002 ps |
CPU time | 16.75 seconds |
Started | Jul 11 06:05:56 PM PDT 24 |
Finished | Jul 11 06:06:15 PM PDT 24 |
Peak memory | 202856 kb |
Host | smart-2c3253a1-a128-4d5e-bc06-fb2953c70ba0 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599649029 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43. sram_ctrl_partial_access.2599649029 |
Directory | /workspace/43.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.162193136 |
Short name | T876 |
Test name | |
Test status | |
Simulation time | 11693464732 ps |
CPU time | 289.62 seconds |
Started | Jul 11 06:05:55 PM PDT 24 |
Finished | Jul 11 06:10:47 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-41ec6f0e-0813-416f-b0ab-072d88673d1f |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162193136 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 43.sram_ctrl_partial_access_b2b.162193136 |
Directory | /workspace/43.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_ram_cfg.4262594957 |
Short name | T450 |
Test name | |
Test status | |
Simulation time | 349572092 ps |
CPU time | 3.61 seconds |
Started | Jul 11 06:06:04 PM PDT 24 |
Finished | Jul 11 06:06:10 PM PDT 24 |
Peak memory | 202916 kb |
Host | smart-3ed7ff11-b87e-42f8-90ae-df0b85d01f6e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262594957 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.4262594957 |
Directory | /workspace/43.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_regwen.619877880 |
Short name | T824 |
Test name | |
Test status | |
Simulation time | 97620755358 ps |
CPU time | 1785.95 seconds |
Started | Jul 11 06:06:06 PM PDT 24 |
Finished | Jul 11 06:35:53 PM PDT 24 |
Peak memory | 381872 kb |
Host | smart-c6b52fb9-0d91-4767-bbf2-a734ffe0b767 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619877880 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.619877880 |
Directory | /workspace/43.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_smoke.768708935 |
Short name | T185 |
Test name | |
Test status | |
Simulation time | 4139033215 ps |
CPU time | 58.01 seconds |
Started | Jul 11 06:05:57 PM PDT 24 |
Finished | Jul 11 06:06:57 PM PDT 24 |
Peak memory | 326880 kb |
Host | smart-067acd19-e2a0-4751-ae6d-df154755bcb1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768708935 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.768708935 |
Directory | /workspace/43.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_stress_all.145553134 |
Short name | T625 |
Test name | |
Test status | |
Simulation time | 75339342185 ps |
CPU time | 5214.87 seconds |
Started | Jul 11 06:06:01 PM PDT 24 |
Finished | Jul 11 07:32:58 PM PDT 24 |
Peak memory | 360328 kb |
Host | smart-7f5b047b-96eb-4be2-a7d1-b639a5e39f82 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145553134 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 43.sram_ctrl_stress_all.145553134 |
Directory | /workspace/43.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.3223906440 |
Short name | T344 |
Test name | |
Test status | |
Simulation time | 3376765115 ps |
CPU time | 26.06 seconds |
Started | Jul 11 06:06:02 PM PDT 24 |
Finished | Jul 11 06:06:30 PM PDT 24 |
Peak memory | 211204 kb |
Host | smart-6cf8352c-95c9-4c2a-b084-ca8788b743f5 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3223906440 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all_with_rand_reset.3223906440 |
Directory | /workspace/43.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_stress_pipeline.1704969071 |
Short name | T242 |
Test name | |
Test status | |
Simulation time | 7116213078 ps |
CPU time | 258.83 seconds |
Started | Jul 11 06:05:55 PM PDT 24 |
Finished | Jul 11 06:10:16 PM PDT 24 |
Peak memory | 203028 kb |
Host | smart-131cf9e6-c960-48b9-b7e3-a9748096661f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704969071 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 3.sram_ctrl_stress_pipeline.1704969071 |
Directory | /workspace/43.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.4289471641 |
Short name | T273 |
Test name | |
Test status | |
Simulation time | 2820085998 ps |
CPU time | 6.16 seconds |
Started | Jul 11 06:05:54 PM PDT 24 |
Finished | Jul 11 06:06:02 PM PDT 24 |
Peak memory | 210940 kb |
Host | smart-3efe3cc6-ae6b-45ba-876b-1a49d64c4651 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289471641 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 43.sram_ctrl_throughput_w_partial_write.4289471641 |
Directory | /workspace/43.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_access_during_key_req.161180267 |
Short name | T328 |
Test name | |
Test status | |
Simulation time | 33425486014 ps |
CPU time | 1112.5 seconds |
Started | Jul 11 06:06:02 PM PDT 24 |
Finished | Jul 11 06:24:36 PM PDT 24 |
Peak memory | 356264 kb |
Host | smart-09a21b18-29b5-4052-8631-08849b3759a9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161180267 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 44.sram_ctrl_access_during_key_req.161180267 |
Directory | /workspace/44.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_alert_test.1698144203 |
Short name | T684 |
Test name | |
Test status | |
Simulation time | 30756466 ps |
CPU time | 0.67 seconds |
Started | Jul 11 06:06:10 PM PDT 24 |
Finished | Jul 11 06:06:13 PM PDT 24 |
Peak memory | 202400 kb |
Host | smart-967d896f-37c2-4538-8bcd-ea460bddab28 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698144203 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_alert_test.1698144203 |
Directory | /workspace/44.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_bijection.1353225854 |
Short name | T182 |
Test name | |
Test status | |
Simulation time | 176040920915 ps |
CPU time | 2983.96 seconds |
Started | Jul 11 06:06:03 PM PDT 24 |
Finished | Jul 11 06:55:49 PM PDT 24 |
Peak memory | 203508 kb |
Host | smart-5f5766a7-5b8f-4a74-9cc4-8187b16cefb0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353225854 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection .1353225854 |
Directory | /workspace/44.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_executable.2559254833 |
Short name | T479 |
Test name | |
Test status | |
Simulation time | 86734215621 ps |
CPU time | 634.91 seconds |
Started | Jul 11 06:06:09 PM PDT 24 |
Finished | Jul 11 06:16:46 PM PDT 24 |
Peak memory | 355288 kb |
Host | smart-09315a25-a012-4d7c-aff9-b2f7fed77c70 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559254833 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_executab le.2559254833 |
Directory | /workspace/44.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_lc_escalation.1690415009 |
Short name | T861 |
Test name | |
Test status | |
Simulation time | 9234777397 ps |
CPU time | 53.45 seconds |
Started | Jul 11 06:06:04 PM PDT 24 |
Finished | Jul 11 06:06:59 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-9ece8845-e3c9-4753-9709-d08be001b9f5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690415009 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_es calation.1690415009 |
Directory | /workspace/44.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_max_throughput.1272702205 |
Short name | T720 |
Test name | |
Test status | |
Simulation time | 699233797 ps |
CPU time | 10.71 seconds |
Started | Jul 11 06:06:01 PM PDT 24 |
Finished | Jul 11 06:06:12 PM PDT 24 |
Peak memory | 235520 kb |
Host | smart-7f7d65cc-9f10-480e-9f4b-08078cdff784 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272702205 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 44.sram_ctrl_max_throughput.1272702205 |
Directory | /workspace/44.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_mem_partial_access.3081504123 |
Short name | T655 |
Test name | |
Test status | |
Simulation time | 20186343589 ps |
CPU time | 154.28 seconds |
Started | Jul 11 06:06:10 PM PDT 24 |
Finished | Jul 11 06:08:47 PM PDT 24 |
Peak memory | 211244 kb |
Host | smart-ff32c787-7e42-4238-b2e4-b3c129266d51 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081504123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 4.sram_ctrl_mem_partial_access.3081504123 |
Directory | /workspace/44.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_mem_walk.3723636897 |
Short name | T647 |
Test name | |
Test status | |
Simulation time | 14385562134 ps |
CPU time | 320.62 seconds |
Started | Jul 11 06:06:09 PM PDT 24 |
Finished | Jul 11 06:11:33 PM PDT 24 |
Peak memory | 211000 kb |
Host | smart-809b6e80-b677-4f32-96b9-9904a9f1ddeb |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723636897 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctr l_mem_walk.3723636897 |
Directory | /workspace/44.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_multiple_keys.4016369595 |
Short name | T659 |
Test name | |
Test status | |
Simulation time | 7073316660 ps |
CPU time | 1086.51 seconds |
Started | Jul 11 06:06:02 PM PDT 24 |
Finished | Jul 11 06:24:10 PM PDT 24 |
Peak memory | 358496 kb |
Host | smart-070827e8-bfea-4ed9-a5ed-de9e9e5cc1fa |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016369595 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multi ple_keys.4016369595 |
Directory | /workspace/44.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_partial_access.3913770212 |
Short name | T447 |
Test name | |
Test status | |
Simulation time | 8529942734 ps |
CPU time | 17.21 seconds |
Started | Jul 11 06:06:04 PM PDT 24 |
Finished | Jul 11 06:06:23 PM PDT 24 |
Peak memory | 202896 kb |
Host | smart-485a7205-cf11-4c43-8501-4c582e61f426 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913770212 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44. sram_ctrl_partial_access.3913770212 |
Directory | /workspace/44.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.415576963 |
Short name | T602 |
Test name | |
Test status | |
Simulation time | 4257352048 ps |
CPU time | 199.38 seconds |
Started | Jul 11 06:06:04 PM PDT 24 |
Finished | Jul 11 06:09:25 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-56494239-6a1e-4ef4-b5b1-aa9b1edc9d2c |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415576963 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 44.sram_ctrl_partial_access_b2b.415576963 |
Directory | /workspace/44.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_ram_cfg.3227284998 |
Short name | T401 |
Test name | |
Test status | |
Simulation time | 4798970699 ps |
CPU time | 3.81 seconds |
Started | Jul 11 06:06:08 PM PDT 24 |
Finished | Jul 11 06:06:14 PM PDT 24 |
Peak memory | 203000 kb |
Host | smart-bea087a1-cb87-408b-ae9a-3ad7cfea60bb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227284998 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.3227284998 |
Directory | /workspace/44.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_regwen.2987758617 |
Short name | T832 |
Test name | |
Test status | |
Simulation time | 5571053812 ps |
CPU time | 685.24 seconds |
Started | Jul 11 06:06:11 PM PDT 24 |
Finished | Jul 11 06:17:39 PM PDT 24 |
Peak memory | 376660 kb |
Host | smart-57ac1713-c889-40f7-a457-68986399e16c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987758617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.2987758617 |
Directory | /workspace/44.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_smoke.3350143707 |
Short name | T550 |
Test name | |
Test status | |
Simulation time | 2166593887 ps |
CPU time | 16.57 seconds |
Started | Jul 11 06:06:02 PM PDT 24 |
Finished | Jul 11 06:06:19 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-d683264c-4570-4043-b33a-6395063d113c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350143707 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.3350143707 |
Directory | /workspace/44.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_stress_all.3693903577 |
Short name | T299 |
Test name | |
Test status | |
Simulation time | 277760126854 ps |
CPU time | 3563.66 seconds |
Started | Jul 11 06:06:10 PM PDT 24 |
Finished | Jul 11 07:05:37 PM PDT 24 |
Peak memory | 381084 kb |
Host | smart-1c600b31-3c97-4c3f-9f6b-fa985003d399 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693903577 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 44.sram_ctrl_stress_all.3693903577 |
Directory | /workspace/44.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_stress_pipeline.1887895785 |
Short name | T600 |
Test name | |
Test status | |
Simulation time | 10233899809 ps |
CPU time | 171.84 seconds |
Started | Jul 11 06:06:02 PM PDT 24 |
Finished | Jul 11 06:08:56 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-8b3a1761-c0d6-4897-8c4d-9758c45dcb43 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887895785 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 4.sram_ctrl_stress_pipeline.1887895785 |
Directory | /workspace/44.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.1120890512 |
Short name | T571 |
Test name | |
Test status | |
Simulation time | 2882525572 ps |
CPU time | 13.53 seconds |
Started | Jul 11 06:06:06 PM PDT 24 |
Finished | Jul 11 06:06:21 PM PDT 24 |
Peak memory | 240228 kb |
Host | smart-1e81b5be-1a9d-4e3d-b611-58494917965a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120890512 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 44.sram_ctrl_throughput_w_partial_write.1120890512 |
Directory | /workspace/44.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_access_during_key_req.4267322767 |
Short name | T43 |
Test name | |
Test status | |
Simulation time | 46523244285 ps |
CPU time | 961.26 seconds |
Started | Jul 11 06:06:07 PM PDT 24 |
Finished | Jul 11 06:22:10 PM PDT 24 |
Peak memory | 371028 kb |
Host | smart-96f8acc4-1654-42a4-af27-307c44a587c6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267322767 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 45.sram_ctrl_access_during_key_req.4267322767 |
Directory | /workspace/45.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_alert_test.434751867 |
Short name | T538 |
Test name | |
Test status | |
Simulation time | 13090541 ps |
CPU time | 0.67 seconds |
Started | Jul 11 06:06:14 PM PDT 24 |
Finished | Jul 11 06:06:17 PM PDT 24 |
Peak memory | 202488 kb |
Host | smart-7d332dba-0e45-4892-9f37-3bde92f06a2d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434751867 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_alert_test.434751867 |
Directory | /workspace/45.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_bijection.1280408984 |
Short name | T504 |
Test name | |
Test status | |
Simulation time | 47140435428 ps |
CPU time | 1643.98 seconds |
Started | Jul 11 06:06:07 PM PDT 24 |
Finished | Jul 11 06:33:32 PM PDT 24 |
Peak memory | 202988 kb |
Host | smart-aec02160-8194-49b0-b8b8-31e3addbfdee |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280408984 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection .1280408984 |
Directory | /workspace/45.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_executable.2822582430 |
Short name | T160 |
Test name | |
Test status | |
Simulation time | 40921978751 ps |
CPU time | 1052.92 seconds |
Started | Jul 11 06:06:08 PM PDT 24 |
Finished | Jul 11 06:23:43 PM PDT 24 |
Peak memory | 379932 kb |
Host | smart-0051d641-c744-4c8e-9ec0-7ed7a951da19 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822582430 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executab le.2822582430 |
Directory | /workspace/45.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_lc_escalation.2511538828 |
Short name | T211 |
Test name | |
Test status | |
Simulation time | 5796486034 ps |
CPU time | 20.6 seconds |
Started | Jul 11 06:06:09 PM PDT 24 |
Finished | Jul 11 06:06:32 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-3f2169e0-691c-40fd-bee3-80917a1362a2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511538828 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_es calation.2511538828 |
Directory | /workspace/45.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_max_throughput.345783687 |
Short name | T248 |
Test name | |
Test status | |
Simulation time | 3098399660 ps |
CPU time | 77.31 seconds |
Started | Jul 11 06:06:08 PM PDT 24 |
Finished | Jul 11 06:07:28 PM PDT 24 |
Peak memory | 336724 kb |
Host | smart-ea01f9ba-7adf-40e1-b0ce-86571af50384 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345783687 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 45.sram_ctrl_max_throughput.345783687 |
Directory | /workspace/45.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_mem_partial_access.1865028635 |
Short name | T633 |
Test name | |
Test status | |
Simulation time | 5062978498 ps |
CPU time | 150.65 seconds |
Started | Jul 11 06:06:13 PM PDT 24 |
Finished | Jul 11 06:08:46 PM PDT 24 |
Peak memory | 211044 kb |
Host | smart-08774472-faf4-4a7f-82c7-f60fdd0545a9 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865028635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 5.sram_ctrl_mem_partial_access.1865028635 |
Directory | /workspace/45.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_mem_walk.1014177524 |
Short name | T737 |
Test name | |
Test status | |
Simulation time | 2743954834 ps |
CPU time | 151.05 seconds |
Started | Jul 11 06:06:13 PM PDT 24 |
Finished | Jul 11 06:08:47 PM PDT 24 |
Peak memory | 211000 kb |
Host | smart-466033be-71f9-45eb-9d80-240b90a77d2e |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014177524 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctr l_mem_walk.1014177524 |
Directory | /workspace/45.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_multiple_keys.2947599954 |
Short name | T464 |
Test name | |
Test status | |
Simulation time | 16998913112 ps |
CPU time | 910.69 seconds |
Started | Jul 11 06:06:09 PM PDT 24 |
Finished | Jul 11 06:21:22 PM PDT 24 |
Peak memory | 380040 kb |
Host | smart-bf4b57eb-0372-40df-bb21-516705020c63 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947599954 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multi ple_keys.2947599954 |
Directory | /workspace/45.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_partial_access.820055765 |
Short name | T294 |
Test name | |
Test status | |
Simulation time | 775416669 ps |
CPU time | 11.68 seconds |
Started | Jul 11 06:06:08 PM PDT 24 |
Finished | Jul 11 06:06:22 PM PDT 24 |
Peak memory | 202744 kb |
Host | smart-15541cbd-f96f-44c1-af5a-1c76e87f6eb1 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820055765 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.s ram_ctrl_partial_access.820055765 |
Directory | /workspace/45.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.995905767 |
Short name | T317 |
Test name | |
Test status | |
Simulation time | 45559402752 ps |
CPU time | 636.61 seconds |
Started | Jul 11 06:06:08 PM PDT 24 |
Finished | Jul 11 06:16:48 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-943e7dad-2360-443d-ad8c-660cc80f8760 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995905767 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 45.sram_ctrl_partial_access_b2b.995905767 |
Directory | /workspace/45.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_ram_cfg.2336609476 |
Short name | T313 |
Test name | |
Test status | |
Simulation time | 697030800 ps |
CPU time | 3.59 seconds |
Started | Jul 11 06:06:14 PM PDT 24 |
Finished | Jul 11 06:06:20 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-68a08fd7-4ef3-4c41-a18f-d6dc3a4a07a9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336609476 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.2336609476 |
Directory | /workspace/45.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_regwen.4151647774 |
Short name | T601 |
Test name | |
Test status | |
Simulation time | 7833548595 ps |
CPU time | 880.63 seconds |
Started | Jul 11 06:06:31 PM PDT 24 |
Finished | Jul 11 06:21:13 PM PDT 24 |
Peak memory | 375692 kb |
Host | smart-95f4bf30-1d0f-46d5-968f-3a388d9c8893 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151647774 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.4151647774 |
Directory | /workspace/45.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_smoke.3165863812 |
Short name | T183 |
Test name | |
Test status | |
Simulation time | 604458507 ps |
CPU time | 7.25 seconds |
Started | Jul 11 06:06:08 PM PDT 24 |
Finished | Jul 11 06:06:17 PM PDT 24 |
Peak memory | 202720 kb |
Host | smart-49222cf9-9b58-4394-9f09-c374a47a32ee |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165863812 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.3165863812 |
Directory | /workspace/45.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_stress_all.2106414991 |
Short name | T874 |
Test name | |
Test status | |
Simulation time | 117313033754 ps |
CPU time | 8064.54 seconds |
Started | Jul 11 06:06:13 PM PDT 24 |
Finished | Jul 11 08:20:42 PM PDT 24 |
Peak memory | 381856 kb |
Host | smart-242d8a67-f92e-4d1a-9cf2-1b8ca72adf43 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106414991 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 45.sram_ctrl_stress_all.2106414991 |
Directory | /workspace/45.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.955654521 |
Short name | T934 |
Test name | |
Test status | |
Simulation time | 811318129 ps |
CPU time | 19.7 seconds |
Started | Jul 11 06:06:13 PM PDT 24 |
Finished | Jul 11 06:06:35 PM PDT 24 |
Peak memory | 211128 kb |
Host | smart-ce1bcd63-7203-4a13-9411-bae529c92e2c |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=955654521 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all_with_rand_reset.955654521 |
Directory | /workspace/45.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_stress_pipeline.2577743647 |
Short name | T305 |
Test name | |
Test status | |
Simulation time | 13097103488 ps |
CPU time | 282.69 seconds |
Started | Jul 11 06:06:09 PM PDT 24 |
Finished | Jul 11 06:10:55 PM PDT 24 |
Peak memory | 202840 kb |
Host | smart-536b8394-5217-4bb4-b265-574356e55ba7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577743647 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 5.sram_ctrl_stress_pipeline.2577743647 |
Directory | /workspace/45.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.167178271 |
Short name | T391 |
Test name | |
Test status | |
Simulation time | 1817484222 ps |
CPU time | 97.31 seconds |
Started | Jul 11 06:06:08 PM PDT 24 |
Finished | Jul 11 06:07:48 PM PDT 24 |
Peak memory | 372544 kb |
Host | smart-d95e0731-728f-48fc-8962-05f575b6e832 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167178271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 45.sram_ctrl_throughput_w_partial_write.167178271 |
Directory | /workspace/45.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_access_during_key_req.1952336022 |
Short name | T546 |
Test name | |
Test status | |
Simulation time | 12147660525 ps |
CPU time | 791.74 seconds |
Started | Jul 11 06:06:22 PM PDT 24 |
Finished | Jul 11 06:19:35 PM PDT 24 |
Peak memory | 348092 kb |
Host | smart-e8edf081-2c61-4ee7-8055-f0caa2b810e3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952336022 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 46.sram_ctrl_access_during_key_req.1952336022 |
Directory | /workspace/46.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_alert_test.1435518229 |
Short name | T339 |
Test name | |
Test status | |
Simulation time | 23500218 ps |
CPU time | 0.66 seconds |
Started | Jul 11 06:06:27 PM PDT 24 |
Finished | Jul 11 06:06:29 PM PDT 24 |
Peak memory | 202588 kb |
Host | smart-eeabc219-b2a3-4190-956c-5c1d4258b06c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435518229 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_alert_test.1435518229 |
Directory | /workspace/46.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_bijection.674275607 |
Short name | T610 |
Test name | |
Test status | |
Simulation time | 111563048975 ps |
CPU time | 1832.3 seconds |
Started | Jul 11 06:06:13 PM PDT 24 |
Finished | Jul 11 06:36:48 PM PDT 24 |
Peak memory | 203212 kb |
Host | smart-cf44abb5-10cf-4f1d-bbdd-88372ee422f3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674275607 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection. 674275607 |
Directory | /workspace/46.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_executable.3334885278 |
Short name | T506 |
Test name | |
Test status | |
Simulation time | 51766817851 ps |
CPU time | 644.71 seconds |
Started | Jul 11 06:06:21 PM PDT 24 |
Finished | Jul 11 06:17:07 PM PDT 24 |
Peak memory | 378680 kb |
Host | smart-cce8a220-48ae-4182-9f9b-aa52bbdeab99 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334885278 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executab le.3334885278 |
Directory | /workspace/46.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_lc_escalation.429678250 |
Short name | T763 |
Test name | |
Test status | |
Simulation time | 21379230454 ps |
CPU time | 68.23 seconds |
Started | Jul 11 06:06:20 PM PDT 24 |
Finished | Jul 11 06:07:30 PM PDT 24 |
Peak memory | 202904 kb |
Host | smart-ea75d4d2-b079-4ff1-a3bd-f716f7b67848 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429678250 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_esc alation.429678250 |
Directory | /workspace/46.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_max_throughput.3123445035 |
Short name | T178 |
Test name | |
Test status | |
Simulation time | 765814798 ps |
CPU time | 87.82 seconds |
Started | Jul 11 06:06:20 PM PDT 24 |
Finished | Jul 11 06:07:49 PM PDT 24 |
Peak memory | 329460 kb |
Host | smart-d4eb351b-5931-409c-8dcc-5244e13c5bc8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123445035 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 46.sram_ctrl_max_throughput.3123445035 |
Directory | /workspace/46.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_mem_partial_access.715063001 |
Short name | T921 |
Test name | |
Test status | |
Simulation time | 4952921294 ps |
CPU time | 156.33 seconds |
Started | Jul 11 06:06:20 PM PDT 24 |
Finished | Jul 11 06:08:58 PM PDT 24 |
Peak memory | 211024 kb |
Host | smart-a92af9b2-b17c-4cae-aa3b-d766728538ff |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715063001 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46 .sram_ctrl_mem_partial_access.715063001 |
Directory | /workspace/46.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_mem_walk.615996146 |
Short name | T271 |
Test name | |
Test status | |
Simulation time | 57567986557 ps |
CPU time | 327.35 seconds |
Started | Jul 11 06:06:22 PM PDT 24 |
Finished | Jul 11 06:11:50 PM PDT 24 |
Peak memory | 211012 kb |
Host | smart-9d97e52f-79b7-47a9-acad-ee982849a853 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615996146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl _mem_walk.615996146 |
Directory | /workspace/46.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_multiple_keys.857102783 |
Short name | T905 |
Test name | |
Test status | |
Simulation time | 80154513440 ps |
CPU time | 1269.34 seconds |
Started | Jul 11 06:06:13 PM PDT 24 |
Finished | Jul 11 06:27:25 PM PDT 24 |
Peak memory | 377692 kb |
Host | smart-899e3658-fd6c-48cd-b344-8cec228899f0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857102783 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multip le_keys.857102783 |
Directory | /workspace/46.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_partial_access.1920315074 |
Short name | T793 |
Test name | |
Test status | |
Simulation time | 1759318696 ps |
CPU time | 7.26 seconds |
Started | Jul 11 06:06:13 PM PDT 24 |
Finished | Jul 11 06:06:23 PM PDT 24 |
Peak memory | 217844 kb |
Host | smart-884194ee-9c2e-4a19-9c16-3a63fc8e0dd4 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920315074 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46. sram_ctrl_partial_access.1920315074 |
Directory | /workspace/46.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.1389924314 |
Short name | T617 |
Test name | |
Test status | |
Simulation time | 99059289700 ps |
CPU time | 552.57 seconds |
Started | Jul 11 06:06:13 PM PDT 24 |
Finished | Jul 11 06:15:28 PM PDT 24 |
Peak memory | 202904 kb |
Host | smart-987bbfed-1a1f-46ed-bf6a-9b6fd9a6e5ce |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389924314 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 46.sram_ctrl_partial_access_b2b.1389924314 |
Directory | /workspace/46.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_ram_cfg.1499957462 |
Short name | T221 |
Test name | |
Test status | |
Simulation time | 970381236 ps |
CPU time | 3.53 seconds |
Started | Jul 11 06:06:22 PM PDT 24 |
Finished | Jul 11 06:06:27 PM PDT 24 |
Peak memory | 202872 kb |
Host | smart-27a0e66d-9fab-4474-b7cb-e4237f8e654e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499957462 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.1499957462 |
Directory | /workspace/46.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_regwen.2464131835 |
Short name | T2 |
Test name | |
Test status | |
Simulation time | 88851937932 ps |
CPU time | 1529.66 seconds |
Started | Jul 11 06:06:21 PM PDT 24 |
Finished | Jul 11 06:31:52 PM PDT 24 |
Peak memory | 379780 kb |
Host | smart-0c39b17a-4af1-4f5e-8d4f-6c971cf9f904 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464131835 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.2464131835 |
Directory | /workspace/46.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_smoke.616546088 |
Short name | T867 |
Test name | |
Test status | |
Simulation time | 828363901 ps |
CPU time | 13.6 seconds |
Started | Jul 11 06:06:13 PM PDT 24 |
Finished | Jul 11 06:06:29 PM PDT 24 |
Peak memory | 241268 kb |
Host | smart-0f96a2c2-2e75-4dee-920b-2ff0e9e6d52c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616546088 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.616546088 |
Directory | /workspace/46.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_stress_all.1478117637 |
Short name | T501 |
Test name | |
Test status | |
Simulation time | 137106097581 ps |
CPU time | 3495.3 seconds |
Started | Jul 11 06:06:21 PM PDT 24 |
Finished | Jul 11 07:04:38 PM PDT 24 |
Peak memory | 382836 kb |
Host | smart-456aff5c-89d5-4e79-8c48-19b45a3b1663 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478117637 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 46.sram_ctrl_stress_all.1478117637 |
Directory | /workspace/46.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3007346683 |
Short name | T75 |
Test name | |
Test status | |
Simulation time | 3215440184 ps |
CPU time | 45.16 seconds |
Started | Jul 11 06:06:20 PM PDT 24 |
Finished | Jul 11 06:07:07 PM PDT 24 |
Peak memory | 211272 kb |
Host | smart-10a8e6d6-5161-4898-bd9f-150e3d7dd660 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3007346683 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all_with_rand_reset.3007346683 |
Directory | /workspace/46.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_stress_pipeline.2858205577 |
Short name | T398 |
Test name | |
Test status | |
Simulation time | 3192778064 ps |
CPU time | 191.78 seconds |
Started | Jul 11 06:06:13 PM PDT 24 |
Finished | Jul 11 06:09:28 PM PDT 24 |
Peak memory | 202848 kb |
Host | smart-8a90ac9f-7ed0-4bed-88fb-ddbee2790f32 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858205577 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 6.sram_ctrl_stress_pipeline.2858205577 |
Directory | /workspace/46.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.2537302348 |
Short name | T784 |
Test name | |
Test status | |
Simulation time | 6648781171 ps |
CPU time | 7.34 seconds |
Started | Jul 11 06:06:21 PM PDT 24 |
Finished | Jul 11 06:06:30 PM PDT 24 |
Peak memory | 211000 kb |
Host | smart-59bb9792-19ee-464a-b8d8-c593e934a634 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537302348 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 46.sram_ctrl_throughput_w_partial_write.2537302348 |
Directory | /workspace/46.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_access_during_key_req.1775872639 |
Short name | T298 |
Test name | |
Test status | |
Simulation time | 32564480545 ps |
CPU time | 904.39 seconds |
Started | Jul 11 06:06:27 PM PDT 24 |
Finished | Jul 11 06:21:33 PM PDT 24 |
Peak memory | 377112 kb |
Host | smart-a915c931-0d69-47c3-9209-79a2d503799d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775872639 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 47.sram_ctrl_access_during_key_req.1775872639 |
Directory | /workspace/47.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_alert_test.654788791 |
Short name | T12 |
Test name | |
Test status | |
Simulation time | 32823305 ps |
CPU time | 0.67 seconds |
Started | Jul 11 06:06:33 PM PDT 24 |
Finished | Jul 11 06:06:35 PM PDT 24 |
Peak memory | 202368 kb |
Host | smart-47eb0a65-5e60-42b9-beef-1f706dc77b62 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654788791 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_alert_test.654788791 |
Directory | /workspace/47.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_bijection.1611239189 |
Short name | T800 |
Test name | |
Test status | |
Simulation time | 27806184866 ps |
CPU time | 1830.79 seconds |
Started | Jul 11 06:06:27 PM PDT 24 |
Finished | Jul 11 06:36:59 PM PDT 24 |
Peak memory | 203656 kb |
Host | smart-11f78c7d-a183-42f3-a887-2200c6ecf6d3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611239189 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection .1611239189 |
Directory | /workspace/47.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_executable.1662844487 |
Short name | T459 |
Test name | |
Test status | |
Simulation time | 21158851237 ps |
CPU time | 1130.82 seconds |
Started | Jul 11 06:06:25 PM PDT 24 |
Finished | Jul 11 06:25:18 PM PDT 24 |
Peak memory | 379764 kb |
Host | smart-90d6fbd6-d7cb-4c40-a3b6-bc0e68a650b0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662844487 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executab le.1662844487 |
Directory | /workspace/47.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_lc_escalation.1400490456 |
Short name | T769 |
Test name | |
Test status | |
Simulation time | 8851236608 ps |
CPU time | 54.89 seconds |
Started | Jul 11 06:06:28 PM PDT 24 |
Finished | Jul 11 06:07:24 PM PDT 24 |
Peak memory | 202828 kb |
Host | smart-288e4d9a-6781-473a-97be-87403da76670 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400490456 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_es calation.1400490456 |
Directory | /workspace/47.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_max_throughput.2042677285 |
Short name | T467 |
Test name | |
Test status | |
Simulation time | 741833733 ps |
CPU time | 15.18 seconds |
Started | Jul 11 06:06:25 PM PDT 24 |
Finished | Jul 11 06:06:42 PM PDT 24 |
Peak memory | 242484 kb |
Host | smart-8fec733e-4a70-446f-83df-f2bba95ca147 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042677285 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 47.sram_ctrl_max_throughput.2042677285 |
Directory | /workspace/47.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_mem_partial_access.3873315659 |
Short name | T452 |
Test name | |
Test status | |
Simulation time | 10387463073 ps |
CPU time | 153.27 seconds |
Started | Jul 11 06:06:30 PM PDT 24 |
Finished | Jul 11 06:09:04 PM PDT 24 |
Peak memory | 211116 kb |
Host | smart-8060ab21-6cf2-478c-9660-afb0d9a803dc |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873315659 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 7.sram_ctrl_mem_partial_access.3873315659 |
Directory | /workspace/47.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_mem_walk.3427446813 |
Short name | T206 |
Test name | |
Test status | |
Simulation time | 72728834346 ps |
CPU time | 308.79 seconds |
Started | Jul 11 06:06:29 PM PDT 24 |
Finished | Jul 11 06:11:39 PM PDT 24 |
Peak memory | 211008 kb |
Host | smart-45e66ba0-26ae-4a40-b365-70f6990cd2c0 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427446813 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctr l_mem_walk.3427446813 |
Directory | /workspace/47.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_multiple_keys.429143192 |
Short name | T631 |
Test name | |
Test status | |
Simulation time | 16086811444 ps |
CPU time | 716.8 seconds |
Started | Jul 11 06:06:25 PM PDT 24 |
Finished | Jul 11 06:18:23 PM PDT 24 |
Peak memory | 377744 kb |
Host | smart-167dfa64-3717-4427-8614-62a1ccb7bd9d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429143192 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multip le_keys.429143192 |
Directory | /workspace/47.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_partial_access.2209027406 |
Short name | T199 |
Test name | |
Test status | |
Simulation time | 833515928 ps |
CPU time | 77.63 seconds |
Started | Jul 11 06:06:26 PM PDT 24 |
Finished | Jul 11 06:07:45 PM PDT 24 |
Peak memory | 311256 kb |
Host | smart-54ae713d-bae3-415c-bb71-53ac2e8ddfa8 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209027406 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47. sram_ctrl_partial_access.2209027406 |
Directory | /workspace/47.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.1159728597 |
Short name | T164 |
Test name | |
Test status | |
Simulation time | 12285120809 ps |
CPU time | 274.15 seconds |
Started | Jul 11 06:06:24 PM PDT 24 |
Finished | Jul 11 06:10:59 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-187e927e-9f32-4c62-bc05-67206d98e148 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159728597 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 47.sram_ctrl_partial_access_b2b.1159728597 |
Directory | /workspace/47.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_ram_cfg.84933193 |
Short name | T345 |
Test name | |
Test status | |
Simulation time | 6698345598 ps |
CPU time | 5.4 seconds |
Started | Jul 11 06:06:30 PM PDT 24 |
Finished | Jul 11 06:06:37 PM PDT 24 |
Peak memory | 202992 kb |
Host | smart-4085a493-84fe-4cc2-8824-e60ae3288592 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84933193 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cf g_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.84933193 |
Directory | /workspace/47.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_regwen.2444723250 |
Short name | T803 |
Test name | |
Test status | |
Simulation time | 3368728192 ps |
CPU time | 640.73 seconds |
Started | Jul 11 06:06:34 PM PDT 24 |
Finished | Jul 11 06:17:16 PM PDT 24 |
Peak memory | 375552 kb |
Host | smart-02e03ec4-db2e-4581-8a6c-a9de2115a1e6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444723250 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.2444723250 |
Directory | /workspace/47.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_smoke.1221924197 |
Short name | T898 |
Test name | |
Test status | |
Simulation time | 1599339607 ps |
CPU time | 14.51 seconds |
Started | Jul 11 06:06:26 PM PDT 24 |
Finished | Jul 11 06:06:42 PM PDT 24 |
Peak memory | 202748 kb |
Host | smart-f883713f-2dc5-4692-b464-34874c34b2b9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221924197 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.1221924197 |
Directory | /workspace/47.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_stress_all.3891481017 |
Short name | T796 |
Test name | |
Test status | |
Simulation time | 19491644993 ps |
CPU time | 2061.61 seconds |
Started | Jul 11 06:06:31 PM PDT 24 |
Finished | Jul 11 06:40:54 PM PDT 24 |
Peak memory | 379916 kb |
Host | smart-c6389322-62d3-4a08-92e6-e2df14c23b28 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891481017 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 47.sram_ctrl_stress_all.3891481017 |
Directory | /workspace/47.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.2965231372 |
Short name | T342 |
Test name | |
Test status | |
Simulation time | 32021502270 ps |
CPU time | 113.75 seconds |
Started | Jul 11 06:06:33 PM PDT 24 |
Finished | Jul 11 06:08:27 PM PDT 24 |
Peak memory | 218928 kb |
Host | smart-271b5ddd-4255-4f4c-a7a7-5d9574ed7f80 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2965231372 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all_with_rand_reset.2965231372 |
Directory | /workspace/47.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_stress_pipeline.939590826 |
Short name | T143 |
Test name | |
Test status | |
Simulation time | 5521479176 ps |
CPU time | 339.26 seconds |
Started | Jul 11 06:06:26 PM PDT 24 |
Finished | Jul 11 06:12:07 PM PDT 24 |
Peak memory | 202832 kb |
Host | smart-ac49dba4-de83-47cd-b731-a8093a2d15fd |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939590826 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47 .sram_ctrl_stress_pipeline.939590826 |
Directory | /workspace/47.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.3534294542 |
Short name | T283 |
Test name | |
Test status | |
Simulation time | 776296983 ps |
CPU time | 42.37 seconds |
Started | Jul 11 06:06:26 PM PDT 24 |
Finished | Jul 11 06:07:09 PM PDT 24 |
Peak memory | 307872 kb |
Host | smart-0f2fa823-d5e2-48db-999a-c806db036e06 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534294542 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 47.sram_ctrl_throughput_w_partial_write.3534294542 |
Directory | /workspace/47.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_access_during_key_req.3322410468 |
Short name | T300 |
Test name | |
Test status | |
Simulation time | 9134657597 ps |
CPU time | 583.8 seconds |
Started | Jul 11 06:06:47 PM PDT 24 |
Finished | Jul 11 06:16:33 PM PDT 24 |
Peak memory | 370980 kb |
Host | smart-b8aeef4a-ca70-41a5-81a0-ac4da40206cd |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322410468 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 48.sram_ctrl_access_during_key_req.3322410468 |
Directory | /workspace/48.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_alert_test.1939374363 |
Short name | T389 |
Test name | |
Test status | |
Simulation time | 24427318 ps |
CPU time | 0.67 seconds |
Started | Jul 11 06:06:43 PM PDT 24 |
Finished | Jul 11 06:06:44 PM PDT 24 |
Peak memory | 202580 kb |
Host | smart-91849aa1-0b47-44a9-a077-ef1122f63eab |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939374363 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_alert_test.1939374363 |
Directory | /workspace/48.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_bijection.3371580535 |
Short name | T329 |
Test name | |
Test status | |
Simulation time | 67343973995 ps |
CPU time | 875.47 seconds |
Started | Jul 11 06:06:33 PM PDT 24 |
Finished | Jul 11 06:21:09 PM PDT 24 |
Peak memory | 203400 kb |
Host | smart-14256ed7-432f-406e-9fa1-80336ea2e8a4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371580535 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection .3371580535 |
Directory | /workspace/48.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_executable.1161966167 |
Short name | T717 |
Test name | |
Test status | |
Simulation time | 14668578840 ps |
CPU time | 1515.81 seconds |
Started | Jul 11 06:06:38 PM PDT 24 |
Finished | Jul 11 06:31:56 PM PDT 24 |
Peak memory | 379696 kb |
Host | smart-c02d1a1d-f2d3-454f-b967-9205b55dfc85 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161966167 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executab le.1161966167 |
Directory | /workspace/48.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_lc_escalation.2725059982 |
Short name | T785 |
Test name | |
Test status | |
Simulation time | 11888817097 ps |
CPU time | 20.45 seconds |
Started | Jul 11 06:06:38 PM PDT 24 |
Finished | Jul 11 06:07:00 PM PDT 24 |
Peak memory | 211096 kb |
Host | smart-2e171978-b98f-474e-b103-fc48dffba1c5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725059982 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_es calation.2725059982 |
Directory | /workspace/48.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_max_throughput.502703129 |
Short name | T680 |
Test name | |
Test status | |
Simulation time | 793100071 ps |
CPU time | 95.01 seconds |
Started | Jul 11 06:06:38 PM PDT 24 |
Finished | Jul 11 06:08:15 PM PDT 24 |
Peak memory | 355216 kb |
Host | smart-34e092a4-2210-400a-ae28-781f6689a9d2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502703129 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 48.sram_ctrl_max_throughput.502703129 |
Directory | /workspace/48.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_mem_partial_access.812711782 |
Short name | T100 |
Test name | |
Test status | |
Simulation time | 6360479954 ps |
CPU time | 127.66 seconds |
Started | Jul 11 06:06:40 PM PDT 24 |
Finished | Jul 11 06:08:49 PM PDT 24 |
Peak memory | 219216 kb |
Host | smart-430c375b-f679-4ded-bcf1-25a476b812c7 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812711782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48 .sram_ctrl_mem_partial_access.812711782 |
Directory | /workspace/48.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_mem_walk.2087314168 |
Short name | T811 |
Test name | |
Test status | |
Simulation time | 18692913513 ps |
CPU time | 334.34 seconds |
Started | Jul 11 06:06:39 PM PDT 24 |
Finished | Jul 11 06:12:15 PM PDT 24 |
Peak memory | 211008 kb |
Host | smart-5ec804a1-04e6-41d3-a64d-fe0aa90605c6 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087314168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctr l_mem_walk.2087314168 |
Directory | /workspace/48.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_multiple_keys.1415781374 |
Short name | T513 |
Test name | |
Test status | |
Simulation time | 22988045299 ps |
CPU time | 1093.39 seconds |
Started | Jul 11 06:06:35 PM PDT 24 |
Finished | Jul 11 06:24:50 PM PDT 24 |
Peak memory | 373648 kb |
Host | smart-52f22992-4e32-48fe-b9d0-1d0400ff2fb2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415781374 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multi ple_keys.1415781374 |
Directory | /workspace/48.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_partial_access.3597910501 |
Short name | T713 |
Test name | |
Test status | |
Simulation time | 431841940 ps |
CPU time | 4.76 seconds |
Started | Jul 11 06:06:37 PM PDT 24 |
Finished | Jul 11 06:06:42 PM PDT 24 |
Peak memory | 202768 kb |
Host | smart-807caa59-3c44-477f-b29c-62952c82724b |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597910501 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48. sram_ctrl_partial_access.3597910501 |
Directory | /workspace/48.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.3106402433 |
Short name | T122 |
Test name | |
Test status | |
Simulation time | 17289223478 ps |
CPU time | 368.77 seconds |
Started | Jul 11 06:06:38 PM PDT 24 |
Finished | Jul 11 06:12:48 PM PDT 24 |
Peak memory | 202816 kb |
Host | smart-ef35f118-7000-46c3-98c9-a462cd682b12 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106402433 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 48.sram_ctrl_partial_access_b2b.3106402433 |
Directory | /workspace/48.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_ram_cfg.2995657893 |
Short name | T196 |
Test name | |
Test status | |
Simulation time | 1409159003 ps |
CPU time | 3.56 seconds |
Started | Jul 11 06:06:38 PM PDT 24 |
Finished | Jul 11 06:06:43 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-30e49fbc-aa56-47d7-a490-b9ad6b9975b3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995657893 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.2995657893 |
Directory | /workspace/48.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_regwen.3248350201 |
Short name | T645 |
Test name | |
Test status | |
Simulation time | 7256151653 ps |
CPU time | 535.85 seconds |
Started | Jul 11 06:06:35 PM PDT 24 |
Finished | Jul 11 06:15:32 PM PDT 24 |
Peak memory | 375840 kb |
Host | smart-ee924c7c-0f7b-4ab7-a200-c26bb8ea698a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248350201 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.3248350201 |
Directory | /workspace/48.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_smoke.3207902211 |
Short name | T405 |
Test name | |
Test status | |
Simulation time | 1099933531 ps |
CPU time | 17.11 seconds |
Started | Jul 11 06:06:30 PM PDT 24 |
Finished | Jul 11 06:06:49 PM PDT 24 |
Peak memory | 202764 kb |
Host | smart-0bea91eb-32bf-4d8a-8533-1cd1638ea3ef |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207902211 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.3207902211 |
Directory | /workspace/48.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_stress_all.3580685854 |
Short name | T332 |
Test name | |
Test status | |
Simulation time | 401221385592 ps |
CPU time | 3309.43 seconds |
Started | Jul 11 06:06:44 PM PDT 24 |
Finished | Jul 11 07:01:56 PM PDT 24 |
Peak memory | 379780 kb |
Host | smart-daf4535f-afd3-4f81-a178-44753ce03dc2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580685854 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 48.sram_ctrl_stress_all.3580685854 |
Directory | /workspace/48.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.3275531493 |
Short name | T702 |
Test name | |
Test status | |
Simulation time | 652219883 ps |
CPU time | 22.72 seconds |
Started | Jul 11 06:06:37 PM PDT 24 |
Finished | Jul 11 06:07:01 PM PDT 24 |
Peak memory | 210992 kb |
Host | smart-c9b15309-5f85-4897-bcd3-5ede52003569 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3275531493 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all_with_rand_reset.3275531493 |
Directory | /workspace/48.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_stress_pipeline.2353805132 |
Short name | T895 |
Test name | |
Test status | |
Simulation time | 11807892878 ps |
CPU time | 286.16 seconds |
Started | Jul 11 06:06:40 PM PDT 24 |
Finished | Jul 11 06:11:27 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-4924eedf-567f-406c-9bb9-0e7023c5dcdd |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353805132 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 8.sram_ctrl_stress_pipeline.2353805132 |
Directory | /workspace/48.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.1895733383 |
Short name | T205 |
Test name | |
Test status | |
Simulation time | 703377720 ps |
CPU time | 5.58 seconds |
Started | Jul 11 06:06:39 PM PDT 24 |
Finished | Jul 11 06:06:46 PM PDT 24 |
Peak memory | 202644 kb |
Host | smart-43378839-7c8c-4838-be46-d69918c72a3d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895733383 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 48.sram_ctrl_throughput_w_partial_write.1895733383 |
Directory | /workspace/48.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_access_during_key_req.3571041869 |
Short name | T521 |
Test name | |
Test status | |
Simulation time | 6344959303 ps |
CPU time | 127.96 seconds |
Started | Jul 11 06:06:41 PM PDT 24 |
Finished | Jul 11 06:08:50 PM PDT 24 |
Peak memory | 365380 kb |
Host | smart-ab35072f-bf49-4c96-bd39-823cec249071 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571041869 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 49.sram_ctrl_access_during_key_req.3571041869 |
Directory | /workspace/49.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_alert_test.4091881054 |
Short name | T165 |
Test name | |
Test status | |
Simulation time | 15644405 ps |
CPU time | 0.66 seconds |
Started | Jul 11 06:06:48 PM PDT 24 |
Finished | Jul 11 06:06:51 PM PDT 24 |
Peak memory | 202584 kb |
Host | smart-98910157-d5d2-40b4-9fbe-f3ef0588c50d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091881054 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_alert_test.4091881054 |
Directory | /workspace/49.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_bijection.2002232842 |
Short name | T173 |
Test name | |
Test status | |
Simulation time | 207638669622 ps |
CPU time | 2141.49 seconds |
Started | Jul 11 06:06:55 PM PDT 24 |
Finished | Jul 11 06:42:39 PM PDT 24 |
Peak memory | 203452 kb |
Host | smart-1360f231-ddda-48b8-bdbd-409dd31930ba |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002232842 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection .2002232842 |
Directory | /workspace/49.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_executable.2257360177 |
Short name | T664 |
Test name | |
Test status | |
Simulation time | 4643674215 ps |
CPU time | 149.9 seconds |
Started | Jul 11 06:06:42 PM PDT 24 |
Finished | Jul 11 06:09:13 PM PDT 24 |
Peak memory | 332844 kb |
Host | smart-1b4d2081-f2d5-49e4-8b0e-be4581c5a831 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257360177 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executab le.2257360177 |
Directory | /workspace/49.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_lc_escalation.2787160018 |
Short name | T290 |
Test name | |
Test status | |
Simulation time | 6951310248 ps |
CPU time | 40.85 seconds |
Started | Jul 11 06:06:42 PM PDT 24 |
Finished | Jul 11 06:07:24 PM PDT 24 |
Peak memory | 202940 kb |
Host | smart-bd01d296-09c8-42da-b23f-28c82341c566 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787160018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_es calation.2787160018 |
Directory | /workspace/49.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_max_throughput.4144771361 |
Short name | T334 |
Test name | |
Test status | |
Simulation time | 779100375 ps |
CPU time | 111.52 seconds |
Started | Jul 11 06:06:41 PM PDT 24 |
Finished | Jul 11 06:08:34 PM PDT 24 |
Peak memory | 364560 kb |
Host | smart-dcfebdc5-11ae-43ca-8cda-59e5efb96cd5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144771361 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 49.sram_ctrl_max_throughput.4144771361 |
Directory | /workspace/49.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_mem_partial_access.580077790 |
Short name | T906 |
Test name | |
Test status | |
Simulation time | 957863983 ps |
CPU time | 63.72 seconds |
Started | Jul 11 06:06:47 PM PDT 24 |
Finished | Jul 11 06:07:53 PM PDT 24 |
Peak memory | 210988 kb |
Host | smart-65b6bbe2-5d45-41b8-8453-6fc3c37fffad |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580077790 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49 .sram_ctrl_mem_partial_access.580077790 |
Directory | /workspace/49.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_mem_walk.1189506035 |
Short name | T813 |
Test name | |
Test status | |
Simulation time | 28210838481 ps |
CPU time | 308.44 seconds |
Started | Jul 11 06:06:48 PM PDT 24 |
Finished | Jul 11 06:11:58 PM PDT 24 |
Peak memory | 211024 kb |
Host | smart-3ed9b2d7-fab5-4691-ad7a-bdc12aee5b2c |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189506035 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctr l_mem_walk.1189506035 |
Directory | /workspace/49.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_multiple_keys.1957854411 |
Short name | T304 |
Test name | |
Test status | |
Simulation time | 6234283879 ps |
CPU time | 503.4 seconds |
Started | Jul 11 06:06:55 PM PDT 24 |
Finished | Jul 11 06:15:20 PM PDT 24 |
Peak memory | 378780 kb |
Host | smart-5c85ea07-54d6-43ed-ab38-3105ce657169 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957854411 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multi ple_keys.1957854411 |
Directory | /workspace/49.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_partial_access.3482748716 |
Short name | T545 |
Test name | |
Test status | |
Simulation time | 7147448944 ps |
CPU time | 70.5 seconds |
Started | Jul 11 06:06:43 PM PDT 24 |
Finished | Jul 11 06:07:56 PM PDT 24 |
Peak memory | 331664 kb |
Host | smart-63a7e3c9-93cf-4b58-8acf-f5c1d0daf8b0 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482748716 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49. sram_ctrl_partial_access.3482748716 |
Directory | /workspace/49.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.890219179 |
Short name | T236 |
Test name | |
Test status | |
Simulation time | 12754933538 ps |
CPU time | 338.65 seconds |
Started | Jul 11 06:06:55 PM PDT 24 |
Finished | Jul 11 06:12:35 PM PDT 24 |
Peak memory | 202880 kb |
Host | smart-6b3e0704-047c-4e14-ab10-5ee50c815209 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890219179 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 49.sram_ctrl_partial_access_b2b.890219179 |
Directory | /workspace/49.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_ram_cfg.4086223571 |
Short name | T854 |
Test name | |
Test status | |
Simulation time | 1410584136 ps |
CPU time | 3.49 seconds |
Started | Jul 11 06:06:49 PM PDT 24 |
Finished | Jul 11 06:06:54 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-d45f200f-1371-4e5e-83d9-a8a902b6dd31 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086223571 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.4086223571 |
Directory | /workspace/49.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_regwen.1229104362 |
Short name | T558 |
Test name | |
Test status | |
Simulation time | 11191254623 ps |
CPU time | 940.83 seconds |
Started | Jul 11 06:06:44 PM PDT 24 |
Finished | Jul 11 06:22:27 PM PDT 24 |
Peak memory | 379772 kb |
Host | smart-9cced98c-a11f-459e-82ff-e85e011302bf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229104362 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.1229104362 |
Directory | /workspace/49.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_smoke.3728286361 |
Short name | T361 |
Test name | |
Test status | |
Simulation time | 929483292 ps |
CPU time | 21.12 seconds |
Started | Jul 11 06:06:44 PM PDT 24 |
Finished | Jul 11 06:07:07 PM PDT 24 |
Peak memory | 202788 kb |
Host | smart-37c891fc-7af4-450f-b66f-6ff223478f65 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728286361 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.3728286361 |
Directory | /workspace/49.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_stress_all.873920315 |
Short name | T456 |
Test name | |
Test status | |
Simulation time | 76105650913 ps |
CPU time | 5437.77 seconds |
Started | Jul 11 06:06:47 PM PDT 24 |
Finished | Jul 11 07:37:28 PM PDT 24 |
Peak memory | 382860 kb |
Host | smart-fac5dd97-edfb-4ee0-9b51-fa3662db8923 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873920315 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 49.sram_ctrl_stress_all.873920315 |
Directory | /workspace/49.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1626028580 |
Short name | T799 |
Test name | |
Test status | |
Simulation time | 613992718 ps |
CPU time | 17.99 seconds |
Started | Jul 11 06:06:56 PM PDT 24 |
Finished | Jul 11 06:07:15 PM PDT 24 |
Peak memory | 211024 kb |
Host | smart-2059d2ef-1eec-4733-9def-b112745411cf |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1626028580 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all_with_rand_reset.1626028580 |
Directory | /workspace/49.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_stress_pipeline.3146796951 |
Short name | T779 |
Test name | |
Test status | |
Simulation time | 16227531871 ps |
CPU time | 209.33 seconds |
Started | Jul 11 06:06:55 PM PDT 24 |
Finished | Jul 11 06:10:25 PM PDT 24 |
Peak memory | 202872 kb |
Host | smart-8ff4defb-c419-4c5e-80a1-81ac59c52058 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146796951 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 9.sram_ctrl_stress_pipeline.3146796951 |
Directory | /workspace/49.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.1228581275 |
Short name | T884 |
Test name | |
Test status | |
Simulation time | 1573352000 ps |
CPU time | 32.15 seconds |
Started | Jul 11 06:06:43 PM PDT 24 |
Finished | Jul 11 06:07:16 PM PDT 24 |
Peak memory | 278336 kb |
Host | smart-7eb5d0d9-54cb-4986-86c7-e7160441b9a0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228581275 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 49.sram_ctrl_throughput_w_partial_write.1228581275 |
Directory | /workspace/49.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_access_during_key_req.3870954843 |
Short name | T643 |
Test name | |
Test status | |
Simulation time | 14282566282 ps |
CPU time | 868.91 seconds |
Started | Jul 11 06:03:05 PM PDT 24 |
Finished | Jul 11 06:17:52 PM PDT 24 |
Peak memory | 378704 kb |
Host | smart-446aaf33-b849-4e0f-a93e-85079753c57e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870954843 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 5.sram_ctrl_access_during_key_req.3870954843 |
Directory | /workspace/5.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_alert_test.3576833375 |
Short name | T622 |
Test name | |
Test status | |
Simulation time | 156741281 ps |
CPU time | 0.66 seconds |
Started | Jul 11 06:03:12 PM PDT 24 |
Finished | Jul 11 06:03:28 PM PDT 24 |
Peak memory | 202556 kb |
Host | smart-fce4ed32-6c0a-4549-87c1-82a01035c921 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576833375 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_alert_test.3576833375 |
Directory | /workspace/5.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_bijection.284932085 |
Short name | T402 |
Test name | |
Test status | |
Simulation time | 191887058490 ps |
CPU time | 2094.77 seconds |
Started | Jul 11 06:03:24 PM PDT 24 |
Finished | Jul 11 06:38:32 PM PDT 24 |
Peak memory | 203500 kb |
Host | smart-0255336c-bb79-418c-89e1-3434ca9f5e04 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284932085 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection.284932085 |
Directory | /workspace/5.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_executable.2953230880 |
Short name | T77 |
Test name | |
Test status | |
Simulation time | 10962191181 ps |
CPU time | 719.57 seconds |
Started | Jul 11 06:03:06 PM PDT 24 |
Finished | Jul 11 06:15:23 PM PDT 24 |
Peak memory | 370532 kb |
Host | smart-3232899c-042c-42da-8855-a3a6c9cce473 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953230880 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executabl e.2953230880 |
Directory | /workspace/5.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_lc_escalation.1413031788 |
Short name | T725 |
Test name | |
Test status | |
Simulation time | 4739994616 ps |
CPU time | 30.55 seconds |
Started | Jul 11 06:03:03 PM PDT 24 |
Finished | Jul 11 06:03:52 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-ac060afd-5ebc-4a77-8d2e-5af3071e27bc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413031788 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_esc alation.1413031788 |
Directory | /workspace/5.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_max_throughput.2761128076 |
Short name | T816 |
Test name | |
Test status | |
Simulation time | 771578639 ps |
CPU time | 88.02 seconds |
Started | Jul 11 06:03:26 PM PDT 24 |
Finished | Jul 11 06:05:06 PM PDT 24 |
Peak memory | 338636 kb |
Host | smart-1aafd836-c6fb-49a7-aefb-b6924471d8d7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761128076 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 5.sram_ctrl_max_throughput.2761128076 |
Directory | /workspace/5.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_mem_partial_access.1449349862 |
Short name | T933 |
Test name | |
Test status | |
Simulation time | 4815459806 ps |
CPU time | 82.68 seconds |
Started | Jul 11 06:03:07 PM PDT 24 |
Finished | Jul 11 06:04:47 PM PDT 24 |
Peak memory | 219360 kb |
Host | smart-c5767751-769b-49d5-b090-8693f0858165 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449349862 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5 .sram_ctrl_mem_partial_access.1449349862 |
Directory | /workspace/5.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_mem_walk.3699698928 |
Short name | T653 |
Test name | |
Test status | |
Simulation time | 54417583194 ps |
CPU time | 172.56 seconds |
Started | Jul 11 06:03:25 PM PDT 24 |
Finished | Jul 11 06:06:30 PM PDT 24 |
Peak memory | 210964 kb |
Host | smart-fe4c4d89-a951-4fcc-9388-6f310281de6d |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699698928 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl _mem_walk.3699698928 |
Directory | /workspace/5.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_multiple_keys.3077570252 |
Short name | T234 |
Test name | |
Test status | |
Simulation time | 42417456359 ps |
CPU time | 1745.85 seconds |
Started | Jul 11 06:03:12 PM PDT 24 |
Finished | Jul 11 06:32:34 PM PDT 24 |
Peak memory | 374688 kb |
Host | smart-c8adf167-2ec9-419e-9724-4bac0d57873a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077570252 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multip le_keys.3077570252 |
Directory | /workspace/5.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_partial_access.1780425068 |
Short name | T337 |
Test name | |
Test status | |
Simulation time | 5337110359 ps |
CPU time | 21.43 seconds |
Started | Jul 11 06:03:06 PM PDT 24 |
Finished | Jul 11 06:03:45 PM PDT 24 |
Peak memory | 203036 kb |
Host | smart-98e5629d-7086-445f-859e-5356209c1654 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780425068 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.s ram_ctrl_partial_access.1780425068 |
Directory | /workspace/5.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.3322160090 |
Short name | T326 |
Test name | |
Test status | |
Simulation time | 19077350126 ps |
CPU time | 408.43 seconds |
Started | Jul 11 06:03:24 PM PDT 24 |
Finished | Jul 11 06:10:26 PM PDT 24 |
Peak memory | 202788 kb |
Host | smart-bcc03c11-8bb9-427c-b25d-a2a5ed9e7da7 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322160090 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 5.sram_ctrl_partial_access_b2b.3322160090 |
Directory | /workspace/5.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_ram_cfg.2228003165 |
Short name | T567 |
Test name | |
Test status | |
Simulation time | 345769052 ps |
CPU time | 3.24 seconds |
Started | Jul 11 06:03:14 PM PDT 24 |
Finished | Jul 11 06:03:33 PM PDT 24 |
Peak memory | 202852 kb |
Host | smart-d4a946fa-1076-499b-82be-194593b7064f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228003165 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.2228003165 |
Directory | /workspace/5.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_regwen.2852137969 |
Short name | T280 |
Test name | |
Test status | |
Simulation time | 26064576862 ps |
CPU time | 1365.68 seconds |
Started | Jul 11 06:03:04 PM PDT 24 |
Finished | Jul 11 06:26:08 PM PDT 24 |
Peak memory | 377788 kb |
Host | smart-3e21fdf1-5ac7-4cdd-8cd2-c171892db1b1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852137969 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.2852137969 |
Directory | /workspace/5.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_smoke.3620429138 |
Short name | T172 |
Test name | |
Test status | |
Simulation time | 2614862311 ps |
CPU time | 10.25 seconds |
Started | Jul 11 06:03:14 PM PDT 24 |
Finished | Jul 11 06:03:40 PM PDT 24 |
Peak memory | 202788 kb |
Host | smart-f93ec000-5869-4c75-ad69-32a0243767f4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620429138 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.3620429138 |
Directory | /workspace/5.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_stress_all.2739473237 |
Short name | T578 |
Test name | |
Test status | |
Simulation time | 1855897891794 ps |
CPU time | 7011.59 seconds |
Started | Jul 11 06:03:22 PM PDT 24 |
Finished | Jul 11 08:00:28 PM PDT 24 |
Peak memory | 387948 kb |
Host | smart-0e094900-9aea-41f1-a383-ab533124d192 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739473237 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 5.sram_ctrl_stress_all.2739473237 |
Directory | /workspace/5.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.317693417 |
Short name | T669 |
Test name | |
Test status | |
Simulation time | 2767921704 ps |
CPU time | 37.96 seconds |
Started | Jul 11 06:03:04 PM PDT 24 |
Finished | Jul 11 06:04:00 PM PDT 24 |
Peak memory | 211188 kb |
Host | smart-727c9d3b-60d9-4106-8d97-354b5bd98f85 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=317693417 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all_with_rand_reset.317693417 |
Directory | /workspace/5.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_stress_pipeline.3907046617 |
Short name | T340 |
Test name | |
Test status | |
Simulation time | 49069555697 ps |
CPU time | 343.21 seconds |
Started | Jul 11 06:03:07 PM PDT 24 |
Finished | Jul 11 06:09:07 PM PDT 24 |
Peak memory | 202996 kb |
Host | smart-043b710a-18db-4b51-afb8-aa6b5089be57 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907046617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5 .sram_ctrl_stress_pipeline.3907046617 |
Directory | /workspace/5.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.2240649018 |
Short name | T827 |
Test name | |
Test status | |
Simulation time | 710048063 ps |
CPU time | 8.16 seconds |
Started | Jul 11 06:03:24 PM PDT 24 |
Finished | Jul 11 06:03:45 PM PDT 24 |
Peak memory | 219112 kb |
Host | smart-429f2cfe-2edf-4e2f-a244-6119997c50d3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240649018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 5.sram_ctrl_throughput_w_partial_write.2240649018 |
Directory | /workspace/5.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_access_during_key_req.1189212529 |
Short name | T797 |
Test name | |
Test status | |
Simulation time | 25446302839 ps |
CPU time | 1490.31 seconds |
Started | Jul 11 06:03:11 PM PDT 24 |
Finished | Jul 11 06:28:17 PM PDT 24 |
Peak memory | 378740 kb |
Host | smart-88e65031-1f69-4473-83b6-0abfa2c4341a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189212529 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 6.sram_ctrl_access_during_key_req.1189212529 |
Directory | /workspace/6.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_alert_test.2052995103 |
Short name | T855 |
Test name | |
Test status | |
Simulation time | 16189003 ps |
CPU time | 0.67 seconds |
Started | Jul 11 06:03:13 PM PDT 24 |
Finished | Jul 11 06:03:29 PM PDT 24 |
Peak memory | 202532 kb |
Host | smart-968b5192-f136-42f3-b76c-f1f85dcb5d5e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052995103 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_alert_test.2052995103 |
Directory | /workspace/6.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_executable.1058352103 |
Short name | T710 |
Test name | |
Test status | |
Simulation time | 63557213569 ps |
CPU time | 928.68 seconds |
Started | Jul 11 06:03:30 PM PDT 24 |
Finished | Jul 11 06:19:10 PM PDT 24 |
Peak memory | 369184 kb |
Host | smart-2a469d96-d533-4fcd-a135-e0b70eb33d02 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058352103 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executabl e.1058352103 |
Directory | /workspace/6.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_lc_escalation.3191288737 |
Short name | T7 |
Test name | |
Test status | |
Simulation time | 22483881933 ps |
CPU time | 38.07 seconds |
Started | Jul 11 06:03:22 PM PDT 24 |
Finished | Jul 11 06:04:14 PM PDT 24 |
Peak memory | 202856 kb |
Host | smart-fb00c23f-0ede-478b-81f5-ff7fbb3aec2d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191288737 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_esc alation.3191288737 |
Directory | /workspace/6.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_max_throughput.4126932930 |
Short name | T259 |
Test name | |
Test status | |
Simulation time | 697774009 ps |
CPU time | 10.61 seconds |
Started | Jul 11 06:03:11 PM PDT 24 |
Finished | Jul 11 06:03:37 PM PDT 24 |
Peak memory | 235480 kb |
Host | smart-35203831-2f09-4829-868a-ac1d656b4d92 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126932930 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 6.sram_ctrl_max_throughput.4126932930 |
Directory | /workspace/6.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_mem_partial_access.1565295930 |
Short name | T198 |
Test name | |
Test status | |
Simulation time | 2465792096 ps |
CPU time | 73.59 seconds |
Started | Jul 11 06:03:23 PM PDT 24 |
Finished | Jul 11 06:04:50 PM PDT 24 |
Peak memory | 211100 kb |
Host | smart-5d1f6d88-6065-4f8d-ac42-903a3439769c |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565295930 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6 .sram_ctrl_mem_partial_access.1565295930 |
Directory | /workspace/6.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_mem_walk.820236810 |
Short name | T167 |
Test name | |
Test status | |
Simulation time | 22995097075 ps |
CPU time | 179.7 seconds |
Started | Jul 11 06:03:13 PM PDT 24 |
Finished | Jul 11 06:06:28 PM PDT 24 |
Peak memory | 203768 kb |
Host | smart-ed361189-7260-46c6-86a7-26f0704c14e9 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820236810 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ mem_walk.820236810 |
Directory | /workspace/6.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_multiple_keys.2926545993 |
Short name | T699 |
Test name | |
Test status | |
Simulation time | 27970107060 ps |
CPU time | 597.7 seconds |
Started | Jul 11 06:03:18 PM PDT 24 |
Finished | Jul 11 06:13:31 PM PDT 24 |
Peak memory | 369556 kb |
Host | smart-c7cf744d-1fa2-4062-bba3-1f325dcc7146 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926545993 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multip le_keys.2926545993 |
Directory | /workspace/6.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_partial_access.4144798621 |
Short name | T517 |
Test name | |
Test status | |
Simulation time | 361057946 ps |
CPU time | 3.91 seconds |
Started | Jul 11 06:03:07 PM PDT 24 |
Finished | Jul 11 06:03:28 PM PDT 24 |
Peak memory | 202724 kb |
Host | smart-a9d6eb8e-e054-47ef-8ebb-a9488269b8c1 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144798621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.s ram_ctrl_partial_access.4144798621 |
Directory | /workspace/6.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.3747986303 |
Short name | T213 |
Test name | |
Test status | |
Simulation time | 16730498684 ps |
CPU time | 198.54 seconds |
Started | Jul 11 06:03:09 PM PDT 24 |
Finished | Jul 11 06:06:44 PM PDT 24 |
Peak memory | 202836 kb |
Host | smart-277ea972-1d33-431f-a95c-9d657d61002c |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747986303 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 6.sram_ctrl_partial_access_b2b.3747986303 |
Directory | /workspace/6.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_ram_cfg.4232483998 |
Short name | T306 |
Test name | |
Test status | |
Simulation time | 681182147 ps |
CPU time | 3.62 seconds |
Started | Jul 11 06:03:26 PM PDT 24 |
Finished | Jul 11 06:03:42 PM PDT 24 |
Peak memory | 202816 kb |
Host | smart-3f0d12e5-c767-45ae-af9f-f8c504b2344f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232483998 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.4232483998 |
Directory | /workspace/6.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_regwen.2126573357 |
Short name | T528 |
Test name | |
Test status | |
Simulation time | 15631366562 ps |
CPU time | 328.02 seconds |
Started | Jul 11 06:03:06 PM PDT 24 |
Finished | Jul 11 06:08:51 PM PDT 24 |
Peak memory | 362372 kb |
Host | smart-36c555b5-f787-4cd5-bb8e-1edea16b679c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126573357 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.2126573357 |
Directory | /workspace/6.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_smoke.784364783 |
Short name | T266 |
Test name | |
Test status | |
Simulation time | 2826160770 ps |
CPU time | 27.97 seconds |
Started | Jul 11 06:03:17 PM PDT 24 |
Finished | Jul 11 06:04:00 PM PDT 24 |
Peak memory | 266168 kb |
Host | smart-a06fff5c-7984-4590-9c39-8c1666a9409d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784364783 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.784364783 |
Directory | /workspace/6.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_stress_all.1210369802 |
Short name | T777 |
Test name | |
Test status | |
Simulation time | 419846362683 ps |
CPU time | 4422.97 seconds |
Started | Jul 11 06:03:10 PM PDT 24 |
Finished | Jul 11 07:17:10 PM PDT 24 |
Peak memory | 380752 kb |
Host | smart-482fa8f9-4af3-424a-a403-c34257eba084 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210369802 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 6.sram_ctrl_stress_all.1210369802 |
Directory | /workspace/6.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2951182061 |
Short name | T747 |
Test name | |
Test status | |
Simulation time | 1438303396 ps |
CPU time | 198.99 seconds |
Started | Jul 11 06:03:17 PM PDT 24 |
Finished | Jul 11 06:06:51 PM PDT 24 |
Peak memory | 387968 kb |
Host | smart-dc37c7fb-5f41-495e-b5e0-b0ce44dabd72 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2951182061 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all_with_rand_reset.2951182061 |
Directory | /workspace/6.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_stress_pipeline.4167480466 |
Short name | T668 |
Test name | |
Test status | |
Simulation time | 5202290772 ps |
CPU time | 315.05 seconds |
Started | Jul 11 06:03:06 PM PDT 24 |
Finished | Jul 11 06:08:38 PM PDT 24 |
Peak memory | 202896 kb |
Host | smart-423539af-6c79-4cb5-86fb-108da11ce4cf |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167480466 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6 .sram_ctrl_stress_pipeline.4167480466 |
Directory | /workspace/6.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.3512202528 |
Short name | T719 |
Test name | |
Test status | |
Simulation time | 773379784 ps |
CPU time | 97.78 seconds |
Started | Jul 11 06:03:10 PM PDT 24 |
Finished | Jul 11 06:05:04 PM PDT 24 |
Peak memory | 340744 kb |
Host | smart-609944bb-0c9d-4849-8d7a-73438ef949e9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512202528 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 6.sram_ctrl_throughput_w_partial_write.3512202528 |
Directory | /workspace/6.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_access_during_key_req.3681507477 |
Short name | T885 |
Test name | |
Test status | |
Simulation time | 4871811393 ps |
CPU time | 60.11 seconds |
Started | Jul 11 06:03:17 PM PDT 24 |
Finished | Jul 11 06:04:32 PM PDT 24 |
Peak memory | 307600 kb |
Host | smart-79b5d847-6517-46ed-bd54-28e1ab2cb91e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681507477 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 7.sram_ctrl_access_during_key_req.3681507477 |
Directory | /workspace/7.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_alert_test.1702503392 |
Short name | T293 |
Test name | |
Test status | |
Simulation time | 70743027 ps |
CPU time | 0.64 seconds |
Started | Jul 11 06:03:09 PM PDT 24 |
Finished | Jul 11 06:03:26 PM PDT 24 |
Peak memory | 202348 kb |
Host | smart-8d6becda-960a-4d67-82d3-ac586e08a6b8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702503392 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_alert_test.1702503392 |
Directory | /workspace/7.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_bijection.2174001974 |
Short name | T805 |
Test name | |
Test status | |
Simulation time | 59111733343 ps |
CPU time | 1040.13 seconds |
Started | Jul 11 06:03:09 PM PDT 24 |
Finished | Jul 11 06:20:46 PM PDT 24 |
Peak memory | 203748 kb |
Host | smart-c8523770-753b-4c8f-8392-608c3372cacf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174001974 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection. 2174001974 |
Directory | /workspace/7.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_executable.1005196470 |
Short name | T741 |
Test name | |
Test status | |
Simulation time | 35845755292 ps |
CPU time | 1225.9 seconds |
Started | Jul 11 06:03:06 PM PDT 24 |
Finished | Jul 11 06:23:49 PM PDT 24 |
Peak memory | 378752 kb |
Host | smart-1f629403-39da-49c3-bf5c-afdcdcb69f20 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005196470 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executabl e.1005196470 |
Directory | /workspace/7.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_lc_escalation.918187607 |
Short name | T735 |
Test name | |
Test status | |
Simulation time | 11345066662 ps |
CPU time | 63.39 seconds |
Started | Jul 11 06:03:15 PM PDT 24 |
Finished | Jul 11 06:04:34 PM PDT 24 |
Peak memory | 202828 kb |
Host | smart-3187456b-ac40-46ae-b659-4e73954c52d6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918187607 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_esca lation.918187607 |
Directory | /workspace/7.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_max_throughput.683584714 |
Short name | T537 |
Test name | |
Test status | |
Simulation time | 2862212904 ps |
CPU time | 72.79 seconds |
Started | Jul 11 06:03:17 PM PDT 24 |
Finished | Jul 11 06:04:45 PM PDT 24 |
Peak memory | 310896 kb |
Host | smart-1c2c9be0-e18e-4147-bd2b-4bdcb09b9451 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683584714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 7.sram_ctrl_max_throughput.683584714 |
Directory | /workspace/7.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_mem_partial_access.1885112241 |
Short name | T759 |
Test name | |
Test status | |
Simulation time | 4481564950 ps |
CPU time | 148.13 seconds |
Started | Jul 11 06:03:22 PM PDT 24 |
Finished | Jul 11 06:06:04 PM PDT 24 |
Peak memory | 211088 kb |
Host | smart-cf79cb8b-6118-43b4-ab06-cfc99428e766 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885112241 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7 .sram_ctrl_mem_partial_access.1885112241 |
Directory | /workspace/7.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_mem_walk.2036839641 |
Short name | T887 |
Test name | |
Test status | |
Simulation time | 43124181963 ps |
CPU time | 196.48 seconds |
Started | Jul 11 06:03:13 PM PDT 24 |
Finished | Jul 11 06:06:45 PM PDT 24 |
Peak memory | 211012 kb |
Host | smart-4f7898ff-4859-4e93-ad01-9ca2ed3dc1bd |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036839641 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl _mem_walk.2036839641 |
Directory | /workspace/7.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_multiple_keys.2734750715 |
Short name | T847 |
Test name | |
Test status | |
Simulation time | 13980604310 ps |
CPU time | 1059.39 seconds |
Started | Jul 11 06:03:19 PM PDT 24 |
Finished | Jul 11 06:21:14 PM PDT 24 |
Peak memory | 369512 kb |
Host | smart-683aec3c-7d34-4d6a-a1b3-af670684263f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734750715 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multip le_keys.2734750715 |
Directory | /workspace/7.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_partial_access.1034294152 |
Short name | T170 |
Test name | |
Test status | |
Simulation time | 1006671992 ps |
CPU time | 12.12 seconds |
Started | Jul 11 06:03:15 PM PDT 24 |
Finished | Jul 11 06:03:43 PM PDT 24 |
Peak memory | 202724 kb |
Host | smart-7de4056f-521d-44e5-a1a7-dc20dc645325 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034294152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.s ram_ctrl_partial_access.1034294152 |
Directory | /workspace/7.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.1555391816 |
Short name | T41 |
Test name | |
Test status | |
Simulation time | 35234089287 ps |
CPU time | 434.47 seconds |
Started | Jul 11 06:03:25 PM PDT 24 |
Finished | Jul 11 06:10:52 PM PDT 24 |
Peak memory | 202856 kb |
Host | smart-fd5bf4cb-0181-4481-aefa-74ab175fbcb0 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555391816 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 7.sram_ctrl_partial_access_b2b.1555391816 |
Directory | /workspace/7.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_ram_cfg.425677505 |
Short name | T253 |
Test name | |
Test status | |
Simulation time | 701234183 ps |
CPU time | 3.26 seconds |
Started | Jul 11 06:03:06 PM PDT 24 |
Finished | Jul 11 06:03:26 PM PDT 24 |
Peak memory | 202792 kb |
Host | smart-51c4f176-5b8b-4117-9c13-81e892cd98ab |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425677505 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.425677505 |
Directory | /workspace/7.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_regwen.3171319933 |
Short name | T410 |
Test name | |
Test status | |
Simulation time | 136736035588 ps |
CPU time | 1594.06 seconds |
Started | Jul 11 06:03:19 PM PDT 24 |
Finished | Jul 11 06:30:09 PM PDT 24 |
Peak memory | 378684 kb |
Host | smart-d33fe5b4-c744-4348-af32-3dd8bd336ad6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171319933 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.3171319933 |
Directory | /workspace/7.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_smoke.2502910532 |
Short name | T609 |
Test name | |
Test status | |
Simulation time | 4330323814 ps |
CPU time | 28.5 seconds |
Started | Jul 11 06:03:08 PM PDT 24 |
Finished | Jul 11 06:03:53 PM PDT 24 |
Peak memory | 278504 kb |
Host | smart-6ea14384-2b1c-4874-9cad-763a27ccc3a2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502910532 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.2502910532 |
Directory | /workspace/7.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_stress_all.2570521045 |
Short name | T794 |
Test name | |
Test status | |
Simulation time | 572331300951 ps |
CPU time | 5971.58 seconds |
Started | Jul 11 06:03:22 PM PDT 24 |
Finished | Jul 11 07:43:08 PM PDT 24 |
Peak memory | 380840 kb |
Host | smart-8ecaa99f-ae56-41b3-8b03-babf4decb764 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570521045 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 7.sram_ctrl_stress_all.2570521045 |
Directory | /workspace/7.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.3027371808 |
Short name | T491 |
Test name | |
Test status | |
Simulation time | 3561832638 ps |
CPU time | 141.94 seconds |
Started | Jul 11 06:03:19 PM PDT 24 |
Finished | Jul 11 06:05:56 PM PDT 24 |
Peak memory | 372836 kb |
Host | smart-e071a506-4abd-4568-afab-0cfbc914ef63 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3027371808 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all_with_rand_reset.3027371808 |
Directory | /workspace/7.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_stress_pipeline.25520915 |
Short name | T261 |
Test name | |
Test status | |
Simulation time | 3692275643 ps |
CPU time | 197.14 seconds |
Started | Jul 11 06:03:15 PM PDT 24 |
Finished | Jul 11 06:06:48 PM PDT 24 |
Peak memory | 202788 kb |
Host | smart-85d2229b-787f-4e00-8680-b02de44b05d7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25520915 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.s ram_ctrl_stress_pipeline.25520915 |
Directory | /workspace/7.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.834326116 |
Short name | T374 |
Test name | |
Test status | |
Simulation time | 716943241 ps |
CPU time | 12.27 seconds |
Started | Jul 11 06:03:22 PM PDT 24 |
Finished | Jul 11 06:03:48 PM PDT 24 |
Peak memory | 237776 kb |
Host | smart-d7afd60c-e0ed-4e6d-817e-d38660fc42b9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834326116 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 7.sram_ctrl_throughput_w_partial_write.834326116 |
Directory | /workspace/7.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_access_during_key_req.898081401 |
Short name | T396 |
Test name | |
Test status | |
Simulation time | 86102430003 ps |
CPU time | 1786.36 seconds |
Started | Jul 11 06:03:15 PM PDT 24 |
Finished | Jul 11 06:33:16 PM PDT 24 |
Peak memory | 379868 kb |
Host | smart-ed61991d-8be9-45b4-aa84-0b43b314b042 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898081401 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 8.sram_ctrl_access_during_key_req.898081401 |
Directory | /workspace/8.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_alert_test.2736101586 |
Short name | T786 |
Test name | |
Test status | |
Simulation time | 22400443 ps |
CPU time | 0.66 seconds |
Started | Jul 11 06:03:28 PM PDT 24 |
Finished | Jul 11 06:03:40 PM PDT 24 |
Peak memory | 202572 kb |
Host | smart-b3237c5a-e55c-49f8-bbba-ce8feb670d93 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736101586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_alert_test.2736101586 |
Directory | /workspace/8.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_bijection.1870875337 |
Short name | T80 |
Test name | |
Test status | |
Simulation time | 21086189937 ps |
CPU time | 1241.91 seconds |
Started | Jul 11 06:03:28 PM PDT 24 |
Finished | Jul 11 06:24:22 PM PDT 24 |
Peak memory | 203516 kb |
Host | smart-cfa588f8-1bdc-4d3e-8fd9-cf685143ef69 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870875337 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection. 1870875337 |
Directory | /workspace/8.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_executable.4067800064 |
Short name | T348 |
Test name | |
Test status | |
Simulation time | 4226666046 ps |
CPU time | 30.76 seconds |
Started | Jul 11 06:03:12 PM PDT 24 |
Finished | Jul 11 06:03:58 PM PDT 24 |
Peak memory | 280020 kb |
Host | smart-72bffb6a-93ee-4156-b197-76935441bcb2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067800064 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executabl e.4067800064 |
Directory | /workspace/8.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_lc_escalation.4093103687 |
Short name | T370 |
Test name | |
Test status | |
Simulation time | 18988910007 ps |
CPU time | 118.41 seconds |
Started | Jul 11 06:03:13 PM PDT 24 |
Finished | Jul 11 06:05:27 PM PDT 24 |
Peak memory | 211128 kb |
Host | smart-ee5d0a1b-5532-497a-a318-7ff8206cc642 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093103687 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_esc alation.4093103687 |
Directory | /workspace/8.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_max_throughput.1658238193 |
Short name | T445 |
Test name | |
Test status | |
Simulation time | 3032855100 ps |
CPU time | 112.51 seconds |
Started | Jul 11 06:03:28 PM PDT 24 |
Finished | Jul 11 06:05:32 PM PDT 24 |
Peak memory | 363320 kb |
Host | smart-47f03d2c-4409-4622-8e5f-ada345073778 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658238193 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 8.sram_ctrl_max_throughput.1658238193 |
Directory | /workspace/8.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_mem_partial_access.1370055032 |
Short name | T322 |
Test name | |
Test status | |
Simulation time | 2836130855 ps |
CPU time | 73.14 seconds |
Started | Jul 11 06:03:30 PM PDT 24 |
Finished | Jul 11 06:04:55 PM PDT 24 |
Peak memory | 210764 kb |
Host | smart-31dcc33c-272c-49ee-b9ab-d92f76bd86ff |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370055032 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8 .sram_ctrl_mem_partial_access.1370055032 |
Directory | /workspace/8.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_mem_walk.505979387 |
Short name | T810 |
Test name | |
Test status | |
Simulation time | 14373372024 ps |
CPU time | 319.64 seconds |
Started | Jul 11 06:03:28 PM PDT 24 |
Finished | Jul 11 06:09:00 PM PDT 24 |
Peak memory | 211008 kb |
Host | smart-6ed8283f-37d1-40d0-a90d-f98f9f207c4a |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505979387 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ mem_walk.505979387 |
Directory | /workspace/8.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_multiple_keys.836400095 |
Short name | T505 |
Test name | |
Test status | |
Simulation time | 57349792318 ps |
CPU time | 488.89 seconds |
Started | Jul 11 06:03:20 PM PDT 24 |
Finished | Jul 11 06:11:43 PM PDT 24 |
Peak memory | 372636 kb |
Host | smart-768727b3-7366-4afe-b555-e1f880dbf45d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836400095 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multipl e_keys.836400095 |
Directory | /workspace/8.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_partial_access.3646998831 |
Short name | T587 |
Test name | |
Test status | |
Simulation time | 1697253402 ps |
CPU time | 9.62 seconds |
Started | Jul 11 06:03:15 PM PDT 24 |
Finished | Jul 11 06:03:40 PM PDT 24 |
Peak memory | 202764 kb |
Host | smart-1707150c-cf6f-4916-9a21-fc50be10fb70 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646998831 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.s ram_ctrl_partial_access.3646998831 |
Directory | /workspace/8.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.2561410174 |
Short name | T116 |
Test name | |
Test status | |
Simulation time | 19954849842 ps |
CPU time | 383.24 seconds |
Started | Jul 11 06:03:18 PM PDT 24 |
Finished | Jul 11 06:09:56 PM PDT 24 |
Peak memory | 202848 kb |
Host | smart-0ed9a06d-f98e-4ae2-acb1-c2ebde3169b9 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561410174 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 8.sram_ctrl_partial_access_b2b.2561410174 |
Directory | /workspace/8.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_ram_cfg.3355710391 |
Short name | T723 |
Test name | |
Test status | |
Simulation time | 787008487 ps |
CPU time | 3.34 seconds |
Started | Jul 11 06:03:15 PM PDT 24 |
Finished | Jul 11 06:03:34 PM PDT 24 |
Peak memory | 202840 kb |
Host | smart-7eb317b8-f7c9-47aa-83fb-6d428558e63b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355710391 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.3355710391 |
Directory | /workspace/8.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_regwen.1026911383 |
Short name | T377 |
Test name | |
Test status | |
Simulation time | 512135362 ps |
CPU time | 110.58 seconds |
Started | Jul 11 06:03:17 PM PDT 24 |
Finished | Jul 11 06:05:23 PM PDT 24 |
Peak memory | 344884 kb |
Host | smart-58eac016-50c1-4b53-94af-6785672a42a5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026911383 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.1026911383 |
Directory | /workspace/8.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_smoke.1879232121 |
Short name | T81 |
Test name | |
Test status | |
Simulation time | 776368563 ps |
CPU time | 3.48 seconds |
Started | Jul 11 06:03:14 PM PDT 24 |
Finished | Jul 11 06:03:33 PM PDT 24 |
Peak memory | 202652 kb |
Host | smart-e3a1b601-aeb4-482b-a739-be5871c90d36 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879232121 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.1879232121 |
Directory | /workspace/8.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_stress_all.1533572923 |
Short name | T686 |
Test name | |
Test status | |
Simulation time | 244798673920 ps |
CPU time | 4854.03 seconds |
Started | Jul 11 06:03:19 PM PDT 24 |
Finished | Jul 11 07:24:28 PM PDT 24 |
Peak memory | 379840 kb |
Host | smart-c0046eea-d92c-4fb1-a018-ea8333d00eaf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533572923 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 8.sram_ctrl_stress_all.1533572923 |
Directory | /workspace/8.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3354789645 |
Short name | T387 |
Test name | |
Test status | |
Simulation time | 9172172894 ps |
CPU time | 24.25 seconds |
Started | Jul 11 06:03:12 PM PDT 24 |
Finished | Jul 11 06:03:52 PM PDT 24 |
Peak memory | 211184 kb |
Host | smart-27852a9c-8c20-435f-bba4-cd061932d2eb |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3354789645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all_with_rand_reset.3354789645 |
Directory | /workspace/8.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_stress_pipeline.336572485 |
Short name | T346 |
Test name | |
Test status | |
Simulation time | 46506350537 ps |
CPU time | 255.1 seconds |
Started | Jul 11 06:03:14 PM PDT 24 |
Finished | Jul 11 06:07:45 PM PDT 24 |
Peak memory | 202880 kb |
Host | smart-3f6c9cd5-fc41-428f-8fc8-ce1f186f6f0a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336572485 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8. sram_ctrl_stress_pipeline.336572485 |
Directory | /workspace/8.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.300128233 |
Short name | T516 |
Test name | |
Test status | |
Simulation time | 742100260 ps |
CPU time | 16.06 seconds |
Started | Jul 11 06:03:13 PM PDT 24 |
Finished | Jul 11 06:03:45 PM PDT 24 |
Peak memory | 251800 kb |
Host | smart-021f6fd5-f5e3-473e-9b86-5dec8b8ca0d9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300128233 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 8.sram_ctrl_throughput_w_partial_write.300128233 |
Directory | /workspace/8.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_access_during_key_req.3580216697 |
Short name | T709 |
Test name | |
Test status | |
Simulation time | 47001340453 ps |
CPU time | 801.39 seconds |
Started | Jul 11 06:03:16 PM PDT 24 |
Finished | Jul 11 06:16:53 PM PDT 24 |
Peak memory | 376768 kb |
Host | smart-e7571c2c-5b73-483b-9c0e-ba1a5654d71a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580216697 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 9.sram_ctrl_access_during_key_req.3580216697 |
Directory | /workspace/9.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_alert_test.3408676950 |
Short name | T742 |
Test name | |
Test status | |
Simulation time | 36202609 ps |
CPU time | 0.64 seconds |
Started | Jul 11 06:03:13 PM PDT 24 |
Finished | Jul 11 06:03:29 PM PDT 24 |
Peak memory | 202572 kb |
Host | smart-23a7a328-2724-4252-85ce-4d9ff6aff084 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408676950 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_alert_test.3408676950 |
Directory | /workspace/9.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_bijection.4129249269 |
Short name | T281 |
Test name | |
Test status | |
Simulation time | 94929950641 ps |
CPU time | 2173.3 seconds |
Started | Jul 11 06:03:18 PM PDT 24 |
Finished | Jul 11 06:39:46 PM PDT 24 |
Peak memory | 203128 kb |
Host | smart-103db3da-988d-4674-8845-33e50262035e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129249269 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection. 4129249269 |
Directory | /workspace/9.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_executable.1562749087 |
Short name | T157 |
Test name | |
Test status | |
Simulation time | 33194963591 ps |
CPU time | 603.06 seconds |
Started | Jul 11 06:03:24 PM PDT 24 |
Finished | Jul 11 06:13:40 PM PDT 24 |
Peak memory | 366984 kb |
Host | smart-51f04260-9b38-4f61-96d3-54939c3424ce |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562749087 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executabl e.1562749087 |
Directory | /workspace/9.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_lc_escalation.821447320 |
Short name | T701 |
Test name | |
Test status | |
Simulation time | 11662890751 ps |
CPU time | 38.04 seconds |
Started | Jul 11 06:03:15 PM PDT 24 |
Finished | Jul 11 06:04:09 PM PDT 24 |
Peak memory | 202904 kb |
Host | smart-5ed0a9b5-d816-42c2-b9f3-a7bd7395a463 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821447320 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_esca lation.821447320 |
Directory | /workspace/9.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_max_throughput.1172458039 |
Short name | T229 |
Test name | |
Test status | |
Simulation time | 699611132 ps |
CPU time | 15.36 seconds |
Started | Jul 11 06:03:20 PM PDT 24 |
Finished | Jul 11 06:03:50 PM PDT 24 |
Peak memory | 251000 kb |
Host | smart-65b44c16-f32b-4366-b837-24942063daad |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172458039 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 9.sram_ctrl_max_throughput.1172458039 |
Directory | /workspace/9.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_mem_partial_access.2174196152 |
Short name | T50 |
Test name | |
Test status | |
Simulation time | 29070529574 ps |
CPU time | 95.38 seconds |
Started | Jul 11 06:03:28 PM PDT 24 |
Finished | Jul 11 06:05:16 PM PDT 24 |
Peak memory | 213012 kb |
Host | smart-9089c8dd-5cdc-46ba-a468-9f5cd18d8976 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174196152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9 .sram_ctrl_mem_partial_access.2174196152 |
Directory | /workspace/9.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_mem_walk.867260278 |
Short name | T449 |
Test name | |
Test status | |
Simulation time | 4108437963 ps |
CPU time | 254.56 seconds |
Started | Jul 11 06:03:28 PM PDT 24 |
Finished | Jul 11 06:07:54 PM PDT 24 |
Peak memory | 211448 kb |
Host | smart-440daa86-55eb-4d7a-911d-4c3cc98912ef |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867260278 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ mem_walk.867260278 |
Directory | /workspace/9.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_multiple_keys.1942299121 |
Short name | T548 |
Test name | |
Test status | |
Simulation time | 274278433757 ps |
CPU time | 1597.24 seconds |
Started | Jul 11 06:03:13 PM PDT 24 |
Finished | Jul 11 06:30:06 PM PDT 24 |
Peak memory | 379284 kb |
Host | smart-67eeb981-647d-4a10-8c00-4e39084dee17 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942299121 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multip le_keys.1942299121 |
Directory | /workspace/9.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_partial_access.3898182909 |
Short name | T415 |
Test name | |
Test status | |
Simulation time | 2426242364 ps |
CPU time | 20.48 seconds |
Started | Jul 11 06:03:16 PM PDT 24 |
Finished | Jul 11 06:03:51 PM PDT 24 |
Peak memory | 202784 kb |
Host | smart-7c3991d0-8ae6-4703-91a1-73dcd7cc61ff |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898182909 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.s ram_ctrl_partial_access.3898182909 |
Directory | /workspace/9.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.476005575 |
Short name | T368 |
Test name | |
Test status | |
Simulation time | 11248719452 ps |
CPU time | 392.12 seconds |
Started | Jul 11 06:03:29 PM PDT 24 |
Finished | Jul 11 06:10:13 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-78bcb8b8-5640-4158-9015-48e4306aade2 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476005575 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 9.sram_ctrl_partial_access_b2b.476005575 |
Directory | /workspace/9.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_ram_cfg.3100142202 |
Short name | T688 |
Test name | |
Test status | |
Simulation time | 667886701 ps |
CPU time | 3.59 seconds |
Started | Jul 11 06:03:15 PM PDT 24 |
Finished | Jul 11 06:03:34 PM PDT 24 |
Peak memory | 202868 kb |
Host | smart-2db0a70d-c05b-4a39-81f3-87ca42f6585e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100142202 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.3100142202 |
Directory | /workspace/9.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_regwen.2036299130 |
Short name | T351 |
Test name | |
Test status | |
Simulation time | 3924069565 ps |
CPU time | 1682.7 seconds |
Started | Jul 11 06:03:28 PM PDT 24 |
Finished | Jul 11 06:31:43 PM PDT 24 |
Peak memory | 378748 kb |
Host | smart-544e7d74-0486-4c8d-8538-e544be8ff947 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036299130 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.2036299130 |
Directory | /workspace/9.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_smoke.245968631 |
Short name | T679 |
Test name | |
Test status | |
Simulation time | 1651936596 ps |
CPU time | 22.32 seconds |
Started | Jul 11 06:03:28 PM PDT 24 |
Finished | Jul 11 06:04:03 PM PDT 24 |
Peak memory | 202788 kb |
Host | smart-7de9c11a-e5af-4909-a92e-435b96285774 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245968631 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.245968631 |
Directory | /workspace/9.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_stress_all.4107379886 |
Short name | T365 |
Test name | |
Test status | |
Simulation time | 295801475048 ps |
CPU time | 3541.44 seconds |
Started | Jul 11 06:03:11 PM PDT 24 |
Finished | Jul 11 07:02:28 PM PDT 24 |
Peak memory | 380804 kb |
Host | smart-a4ea7ff8-05bc-41d2-9f1b-2f8123f99e6f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107379886 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 9.sram_ctrl_stress_all.4107379886 |
Directory | /workspace/9.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.2777534148 |
Short name | T130 |
Test name | |
Test status | |
Simulation time | 4517259125 ps |
CPU time | 34.32 seconds |
Started | Jul 11 06:03:15 PM PDT 24 |
Finished | Jul 11 06:04:04 PM PDT 24 |
Peak memory | 211228 kb |
Host | smart-dd64a3d9-1949-4ce9-80e3-739b374a8508 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2777534148 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all_with_rand_reset.2777534148 |
Directory | /workspace/9.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_stress_pipeline.1197487325 |
Short name | T314 |
Test name | |
Test status | |
Simulation time | 15132474766 ps |
CPU time | 265.93 seconds |
Started | Jul 11 06:03:15 PM PDT 24 |
Finished | Jul 11 06:07:56 PM PDT 24 |
Peak memory | 202856 kb |
Host | smart-48e39a60-93a9-4cd2-91aa-1836846ec090 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197487325 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9 .sram_ctrl_stress_pipeline.1197487325 |
Directory | /workspace/9.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.2434176788 |
Short name | T174 |
Test name | |
Test status | |
Simulation time | 2793925898 ps |
CPU time | 14.27 seconds |
Started | Jul 11 06:03:17 PM PDT 24 |
Finished | Jul 11 06:03:46 PM PDT 24 |
Peak memory | 244428 kb |
Host | smart-a05e4300-7fb2-4f0e-a1ec-1875bd13ff39 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434176788 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 9.sram_ctrl_throughput_w_partial_write.2434176788 |
Directory | /workspace/9.sram_ctrl_throughput_w_partial_write/latest |
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