Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16622465	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

175681707

1

T1

6468

T3

1566

T4

3274

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	94868023	1			T1	1902		T3	4339		T4	1786
values[0x0]	47060173	1			T1	2366		T3	1506		T4	870
values[0x1]	50375976	1			T1	2294		T3	2937		T4	958

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8454047	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

183850125

1

T1

6521

T3

5151

T4

3442

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	626023	1			T1	37		T3	34		T4	33
valid_sources[0x01]	611527	1			T1	30		T3	30		T4	83
valid_sources[0x02]	626354	1			T1	39		T3	38		T8	3651
valid_sources[0x03]	606146	1			T1	30		T3	37		T8	3621
valid_sources[0x04]	577316	1			T1	24		T3	36		T8	3614
valid_sources[0x05]	631200	1			T1	18		T3	26		T8	3576
valid_sources[0x06]	600157	1			T1	22		T3	37		T8	3559
valid_sources[0x07]	606406	1			T1	20		T3	39		T8	3590
valid_sources[0x08]	624905	1			T1	27		T3	36		T4	1
valid_sources[0x09]	646887	1			T1	21		T3	31		T8	3640
valid_sources[0x0a]	654951	1			T1	33		T3	27		T8	3602
valid_sources[0x0b]	617878	1			T1	15		T3	36		T8	3612
valid_sources[0x0c]	630105	1			T1	23		T3	34		T8	3524
valid_sources[0x0d]	633545	1			T1	28		T3	27		T4	49
valid_sources[0x0e]	585502	1			T1	30		T3	36		T4	3
valid_sources[0x0f]	1277523	1			T1	30		T3	30		T4	20
valid_sources[0x10]	620099	1			T1	19		T3	25		T4	39
valid_sources[0x11]	596751	1			T1	28		T3	32		T8	3522
valid_sources[0x12]	586839	1			T1	28		T3	33		T4	5
valid_sources[0x13]	605437	1			T1	22		T3	32		T8	3533
valid_sources[0x14]	733182	1			T1	27		T3	35		T8	3596
valid_sources[0x15]	602750	1			T1	28		T3	33		T8	3607
valid_sources[0x16]	574111	1			T1	22		T3	33		T8	3620
valid_sources[0x17]	580005	1			T1	26		T3	45		T8	3594
valid_sources[0x18]	1678452	1			T1	30		T3	41		T8	3657
valid_sources[0x19]	596040	1			T1	28		T3	36		T8	3574
valid_sources[0x1a]	664893	1			T1	31		T3	41		T8	3689
valid_sources[0x1b]	602887	1			T1	23		T3	30		T4	47
valid_sources[0x1c]	573886	1			T1	26		T3	38		T4	89
valid_sources[0x1d]	721474	1			T1	28		T3	36		T8	3634
valid_sources[0x1e]	620689	1			T1	30		T3	38		T8	3534
valid_sources[0x1f]	598191	1			T1	23		T3	42		T8	3578
valid_sources[0x20]	642551	1			T1	21		T3	41		T8	3510
valid_sources[0x21]	632984	1			T1	25		T3	27		T8	3537
valid_sources[0x22]	617036	1			T1	21		T3	32		T4	48
valid_sources[0x23]	596057	1			T1	21		T3	36		T4	12
valid_sources[0x24]	607514	1			T1	30		T3	29		T8	3623
valid_sources[0x25]	1085347	1			T1	24		T3	40		T4	17
valid_sources[0x26]	609833	1			T1	22		T3	39		T4	29
valid_sources[0x27]	672933	1			T1	31		T3	34		T4	28
valid_sources[0x28]	607066	1			T1	32		T3	36		T4	136
valid_sources[0x29]	638588	1			T1	19		T3	35		T8	3577
valid_sources[0x2a]	608552	1			T1	31		T3	38		T8	3513
valid_sources[0x2b]	618420	1			T1	28		T3	39		T8	3578
valid_sources[0x2c]	612052	1			T1	20		T3	33		T8	3700
valid_sources[0x2d]	580705	1			T1	27		T3	29		T8	3517
valid_sources[0x2e]	679108	1			T1	19		T3	46		T4	74
valid_sources[0x2f]	633639	1			T1	15		T3	35		T8	3639
valid_sources[0x30]	582140	1			T1	25		T3	35		T4	3
valid_sources[0x31]	659046	1			T1	20		T3	34		T4	64
valid_sources[0x32]	612929	1			T1	26		T3	35		T8	3548
valid_sources[0x33]	2020022	1			T1	22		T3	32		T8	3620
valid_sources[0x34]	582203	1			T1	24		T3	34		T8	3533
valid_sources[0x35]	650166	1			T1	34		T3	35		T4	53
valid_sources[0x36]	578979	1			T1	29		T3	31		T4	81
valid_sources[0x37]	755473	1			T1	16		T3	32		T8	3458
valid_sources[0x38]	639205	1			T1	38		T3	31		T8	3625
valid_sources[0x39]	602547	1			T1	36		T3	42		T4	34
valid_sources[0x3a]	612759	1			T1	27		T3	36		T8	3566
valid_sources[0x3b]	1583755	1			T1	36		T3	34		T4	38
valid_sources[0x3c]	617148	1			T1	32		T3	35		T8	3672
valid_sources[0x3d]	719502	1			T1	21		T3	40		T4	36
valid_sources[0x3e]	571736	1			T1	32		T3	39		T8	3540
valid_sources[0x3f]	583536	1			T1	27		T3	32		T8	3589
valid_sources[0x40]	606545	1			T1	20		T3	31		T4	24
valid_sources[0x41]	576226	1			T1	36		T3	34		T4	2
valid_sources[0x42]	1832950	1			T1	21		T3	38		T8	3651
valid_sources[0x43]	592597	1			T1	27		T3	30		T8	3642
valid_sources[0x44]	590932	1			T1	23		T3	33		T4	34
valid_sources[0x45]	1409807	1			T1	22		T3	33		T4	21
valid_sources[0x46]	4218788	1			T1	20		T3	31		T8	3632
valid_sources[0x47]	618731	1			T1	24		T3	45		T8	3666
valid_sources[0x48]	627283	1			T1	22		T3	31		T8	3533
valid_sources[0x49]	593263	1			T1	22		T3	28		T8	3596
valid_sources[0x4a]	1635618	1			T1	16		T3	28		T8	3657
valid_sources[0x4b]	585157	1			T1	24		T3	29		T4	2
valid_sources[0x4c]	575803	1			T1	22		T3	27		T8	3491
valid_sources[0x4d]	573768	1			T1	32		T3	38		T4	60
valid_sources[0x4e]	579722	1			T1	29		T3	34		T4	91
valid_sources[0x4f]	1557473	1			T1	22		T3	33		T8	3608
valid_sources[0x50]	593891	1			T1	29		T3	35		T4	1
valid_sources[0x51]	824579	1			T1	19		T3	36		T8	3465
valid_sources[0x52]	577191	1			T1	29		T3	30		T8	3588
valid_sources[0x53]	601232	1			T1	17		T3	25		T4	43
valid_sources[0x54]	596091	1			T1	33		T3	36		T8	3684
valid_sources[0x55]	653468	1			T1	28		T3	30		T8	3574
valid_sources[0x56]	601070	1			T1	20		T3	46		T8	3497
valid_sources[0x57]	624656	1			T1	19		T3	31		T4	66
valid_sources[0x58]	1509762	1			T1	30		T3	30		T4	4
valid_sources[0x59]	1654933	1			T1	24		T3	33		T8	3521
valid_sources[0x5a]	581812	1			T1	21		T3	42		T8	3584
valid_sources[0x5b]	1027767	1			T1	28		T3	32		T8	3658
valid_sources[0x5c]	612094	1			T1	25		T3	26		T4	72
valid_sources[0x5d]	1224710	1			T1	20		T3	38		T4	1
valid_sources[0x5e]	593250	1			T1	24		T3	33		T8	3652
valid_sources[0x5f]	650805	1			T1	27		T3	30		T8	3621
valid_sources[0x60]	655368	1			T1	32		T3	41		T8	3558
valid_sources[0x61]	715352	1			T1	27		T3	33		T8	3555
valid_sources[0x62]	690919	1			T1	28		T3	37		T4	82
valid_sources[0x63]	625741	1			T1	26		T3	38		T8	3664
valid_sources[0x64]	666886	1			T1	23		T3	42		T8	3657
valid_sources[0x65]	605654	1			T1	26		T3	43		T8	3605
valid_sources[0x66]	606687	1			T1	19		T3	43		T4	25
valid_sources[0x67]	649332	1			T1	31		T3	31		T8	3608
valid_sources[0x68]	1792213	1			T1	19		T3	42		T8	3656
valid_sources[0x69]	608757	1			T1	26		T3	35		T8	3691
valid_sources[0x6a]	643777	1			T1	22		T3	33		T8	3596
valid_sources[0x6b]	580416	1			T1	31		T3	45		T4	4
valid_sources[0x6c]	628563	1			T1	20		T3	23		T8	3553
valid_sources[0x6d]	594840	1			T1	17		T3	36		T8	3672
valid_sources[0x6e]	818542	1			T1	18		T3	41		T8	3554
valid_sources[0x6f]	582771	1			T1	34		T3	32		T8	3625
valid_sources[0x70]	582723	1			T1	25		T3	35		T8	3621
valid_sources[0x71]	632669	1			T1	17		T3	37		T4	49
valid_sources[0x72]	584193	1			T1	24		T3	41		T8	3525
valid_sources[0x73]	647768	1			T1	27		T3	36		T8	3558
valid_sources[0x74]	574657	1			T1	33		T3	35		T8	3613
valid_sources[0x75]	595455	1			T1	30		T3	35		T4	49
valid_sources[0x76]	601692	1			T1	31		T3	26		T4	68
valid_sources[0x77]	619267	1			T1	34		T3	44		T4	6
valid_sources[0x78]	604814	1			T1	30		T3	19		T8	3509
valid_sources[0x79]	2022944	1			T1	18		T3	36		T8	3554
valid_sources[0x7a]	611842	1			T1	24		T3	33		T8	3512
valid_sources[0x7b]	584925	1			T1	34		T3	35		T4	106
valid_sources[0x7c]	609557	1			T1	32		T3	37		T8	3619
valid_sources[0x7d]	610364	1			T1	22		T3	27		T4	51
valid_sources[0x7e]	1844651	1			T1	25		T3	33		T8	3686
valid_sources[0x7f]	2064849	1			T1	22		T3	29		T8	3591
valid_sources[0x80]	575849	1			T1	29		T3	33		T4	22

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

86513199

1

T1

1859

T3

770

T4

1627

values[0x0]

all_enables

biggest_size

44579654

1

T1

2354

T3

409

T4

809

values[0x1]

all_enables

biggest_size

44588854

1

T1

2255

T3

387

T4

838

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	45826	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

155749

1

T1

2734

T4

27

T8

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	54591	1			T1	793		T4	34		T21	805
values[0x0]	71171	1			T1	1043		T2	1		T3	1
values[0x1]	75813	1			T1	1170		T2	2		T3	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35572	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

166003

1

T1

2867

T4

31

T8

5

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1388	1			T1	6		T21	4		T6	4
valid_sources[0x01]	1300	1			T1	9		T21	8		T50	3
valid_sources[0x02]	727	1			T1	11		T21	7		T51	2
valid_sources[0x03]	759	1			T1	9		T21	5		T19	1
valid_sources[0x04]	1288	1			T1	19		T21	14		T50	1
valid_sources[0x05]	737	1			T1	15		T21	13		T51	1
valid_sources[0x06]	676	1			T1	15		T21	13		T83	1
valid_sources[0x07]	936	1			T1	19		T21	10		T50	2
valid_sources[0x08]	754	1			T1	8		T21	9		T83	1
valid_sources[0x09]	520	1			T1	8		T21	10		T50	1
valid_sources[0x0a]	996	1			T1	17		T12	3		T21	14
valid_sources[0x0b]	890	1			T1	12		T21	11		T23	7
valid_sources[0x0c]	711	1			T1	12		T21	11		T51	1
valid_sources[0x0d]	1403	1			T1	13		T21	9		T19	2
valid_sources[0x0e]	619	1			T1	12		T21	9		T50	6
valid_sources[0x0f]	635	1			T1	8		T21	10		T23	10
valid_sources[0x10]	737	1			T1	19		T21	7		T50	1
valid_sources[0x11]	749	1			T1	16		T12	2		T21	13
valid_sources[0x12]	811	1			T1	15		T21	11		T23	2
valid_sources[0x13]	923	1			T1	10		T21	8		T83	1
valid_sources[0x14]	648	1			T1	3		T21	15		T51	3
valid_sources[0x15]	525	1			T1	14		T21	11		T50	3
valid_sources[0x16]	678	1			T1	11		T21	13		T50	3
valid_sources[0x17]	869	1			T1	11		T21	11		T51	1
valid_sources[0x18]	693	1			T1	16		T2	1		T21	20
valid_sources[0x19]	935	1			T1	2		T21	17		T19	2
valid_sources[0x1a]	789	1			T1	8		T21	7		T19	2
valid_sources[0x1b]	629	1			T1	7		T21	7		T50	2
valid_sources[0x1c]	1012	1			T1	11		T21	7		T23	9
valid_sources[0x1d]	1109	1			T1	11		T21	14		T23	4
valid_sources[0x1e]	721	1			T1	13		T21	10		T7	1
valid_sources[0x1f]	955	1			T1	9		T21	13		T51	2
valid_sources[0x20]	833	1			T1	22		T21	13		T49	2
valid_sources[0x21]	961	1			T1	21		T21	8		T83	1
valid_sources[0x22]	903	1			T1	16		T21	11		T50	1
valid_sources[0x23]	599	1			T1	8		T21	9		T51	1
valid_sources[0x24]	776	1			T1	12		T21	9		T13	2
valid_sources[0x25]	663	1			T1	17		T21	14		T14	2
valid_sources[0x26]	778	1			T1	5		T21	14		T144	5
valid_sources[0x27]	633	1			T1	8		T21	9		T19	1
valid_sources[0x28]	927	1			T1	9		T21	14		T50	3
valid_sources[0x29]	616	1			T1	6		T21	17		T19	1
valid_sources[0x2a]	625	1			T1	9		T21	8		T7	2
valid_sources[0x2b]	869	1			T1	5		T21	17		T144	6
valid_sources[0x2c]	966	1			T1	13		T21	11		T50	1
valid_sources[0x2d]	888	1			T1	27		T21	14		T51	1
valid_sources[0x2e]	691	1			T1	15		T21	16		T51	2
valid_sources[0x2f]	878	1			T1	14		T12	37		T21	13
valid_sources[0x30]	616	1			T1	17		T21	13		T50	2
valid_sources[0x31]	636	1			T1	16		T40	3		T21	8
valid_sources[0x32]	737	1			T1	18		T21	6		T50	3
valid_sources[0x33]	823	1			T1	7		T21	5		T24	50
valid_sources[0x34]	942	1			T1	18		T21	9		T23	20
valid_sources[0x35]	628	1			T1	10		T21	11		T51	1
valid_sources[0x36]	838	1			T1	16		T21	11		T19	2
valid_sources[0x37]	563	1			T1	6		T21	13		T50	2
valid_sources[0x38]	602	1			T1	6		T10	1		T21	15
valid_sources[0x39]	597	1			T1	14		T21	6		T83	1
valid_sources[0x3a]	940	1			T1	19		T21	7		T13	5
valid_sources[0x3b]	857	1			T1	6		T21	18		T50	2
valid_sources[0x3c]	736	1			T1	12		T21	14		T50	5
valid_sources[0x3d]	1021	1			T1	6		T12	14		T21	14
valid_sources[0x3e]	843	1			T1	17		T10	2		T21	12
valid_sources[0x3f]	777	1			T1	6		T21	19		T19	1
valid_sources[0x40]	874	1			T1	18		T21	14		T19	1
valid_sources[0x41]	572	1			T1	12		T21	11		T19	1
valid_sources[0x42]	888	1			T1	12		T21	8		T50	3
valid_sources[0x43]	1124	1			T1	7		T10	1		T21	15
valid_sources[0x44]	1157	1			T1	9		T10	1		T21	12
valid_sources[0x45]	930	1			T1	15		T21	10		T51	2
valid_sources[0x46]	857	1			T1	4		T21	18		T48	5
valid_sources[0x47]	1038	1			T1	20		T21	13		T50	8
valid_sources[0x48]	838	1			T1	10		T21	9		T50	3
valid_sources[0x49]	705	1			T1	22		T21	9		T50	3
valid_sources[0x4a]	753	1			T1	15		T21	7		T7	2
valid_sources[0x4b]	979	1			T1	5		T21	7		T23	3
valid_sources[0x4c]	694	1			T1	4		T21	13		T50	7
valid_sources[0x4d]	466	1			T1	2		T21	15		T19	1
valid_sources[0x4e]	679	1			T1	19		T12	16		T21	9
valid_sources[0x4f]	701	1			T1	13		T12	3		T21	15
valid_sources[0x50]	855	1			T1	17		T21	11		T7	3
valid_sources[0x51]	647	1			T1	22		T21	11		T51	1
valid_sources[0x52]	1332	1			T1	13		T21	12		T19	1
valid_sources[0x53]	520	1			T1	11		T21	16		T50	1
valid_sources[0x54]	617	1			T1	13		T21	18		T50	3
valid_sources[0x55]	604	1			T1	13		T21	17		T83	1
valid_sources[0x56]	723	1			T1	4		T21	13		T46	1
valid_sources[0x57]	702	1			T1	13		T21	6		T23	12
valid_sources[0x58]	797	1			T1	11		T21	10		T19	1
valid_sources[0x59]	1172	1			T1	9		T21	8		T50	2
valid_sources[0x5a]	824	1			T1	12		T21	13		T6	9
valid_sources[0x5b]	510	1			T1	10		T21	6		T19	1
valid_sources[0x5c]	585	1			T1	14		T21	15		T83	1
valid_sources[0x5d]	713	1			T1	7		T21	10		T50	3
valid_sources[0x5e]	774	1			T1	16		T21	10		T50	2
valid_sources[0x5f]	608	1			T1	16		T21	9		T51	1
valid_sources[0x60]	759	1			T1	7		T10	1		T21	15
valid_sources[0x61]	1009	1			T1	20		T21	9		T51	1
valid_sources[0x62]	1122	1			T1	9		T21	8		T50	1
valid_sources[0x63]	966	1			T1	15		T9	178		T21	9
valid_sources[0x64]	947	1			T1	16		T21	8		T83	1
valid_sources[0x65]	1023	1			T1	6		T21	17		T50	3
valid_sources[0x66]	1120	1			T1	8		T21	7		T50	1
valid_sources[0x67]	579	1			T1	1		T21	15		T62	2
valid_sources[0x68]	891	1			T1	32		T21	21		T23	5
valid_sources[0x69]	726	1			T1	4		T21	15		T51	1
valid_sources[0x6a]	475	1			T1	4		T21	6		T51	2
valid_sources[0x6b]	803	1			T1	11		T21	15		T50	3
valid_sources[0x6c]	646	1			T1	19		T84	2		T21	14
valid_sources[0x6d]	1059	1			T1	7		T21	8		T6	12
valid_sources[0x6e]	934	1			T1	9		T21	17		T51	1
valid_sources[0x6f]	948	1			T1	13		T21	9		T14	1
valid_sources[0x70]	625	1			T1	18		T21	6		T50	1
valid_sources[0x71]	594	1			T1	9		T21	10		T83	1
valid_sources[0x72]	523	1			T1	13		T21	15		T50	1
valid_sources[0x73]	1000	1			T1	19		T21	12		T50	2
valid_sources[0x74]	556	1			T1	16		T21	14		T19	1
valid_sources[0x75]	684	1			T1	9		T21	9		T51	2
valid_sources[0x76]	711	1			T1	13		T21	15		T50	4
valid_sources[0x77]	1018	1			T1	11		T21	14		T50	3
valid_sources[0x78]	926	1			T1	13		T21	18		T7	2
valid_sources[0x79]	900	1			T1	17		T21	15		T51	1
valid_sources[0x7a]	682	1			T1	12		T21	13		T83	2
valid_sources[0x7b]	927	1			T1	16		T12	2		T21	7
valid_sources[0x7c]	753	1			T1	10		T21	11		T46	1
valid_sources[0x7d]	518	1			T1	16		T21	9		T50	5
valid_sources[0x7e]	706	1			T1	11		T21	8		T50	5
valid_sources[0x7f]	600	1			T1	10		T21	7		T6	2
valid_sources[0x80]	543	1			T1	8		T21	10		T51	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

41715

1

T1

712

T4

20

T21

744

values[0x0]

all_enables

biggest_size

58696

1

T1

1014

T4

4

T8

3

values[0x1]

all_enables

biggest_size

55338

1

T1

1008

T4

3

T8

2