Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16496649

1

T1

4960

T3

7216

T4

25

full_word

172274351

1

T1

7030

T3

1566

T4

254

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	188770740	1			T1	11990		T3	8782		T4	279
auto[TlIntgErrCmd]	86	1			T58	4		T59	4		T60	8
auto[TlIntgErrData]	83	1			T58	5		T60	7		T127	3
auto[TlIntgErrBoth]	91	1			T58	11		T59	6		T60	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

91246053

1

T1

2997

T3

4339

T4

141

auto[1]

97524947

1

T1

8993

T3

4443

T4

138

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	8065665	1			T1	995		T3	3569		T4	9
auto[TlIntgErrNone]	partial	auto[1]	8430745	1			T1	3965		T3	3647		T4	16
auto[TlIntgErrNone]	full_word	auto[0]	83180271	1			T1	2002		T3	770		T4	132
auto[TlIntgErrNone]	full_word	auto[1]	89094059	1			T1	5028		T3	796		T4	122
auto[TlIntgErrCmd]	partial	auto[0]	34	1			T60	4		T127	2		T122	3
auto[TlIntgErrCmd]	partial	auto[1]	45	1			T58	3		T59	3		T60	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T59	1		T60	1		T131	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T58	1		T123	1		T128	1
auto[TlIntgErrData]	partial	auto[0]	34	1			T58	1		T60	2		T127	1
auto[TlIntgErrData]	partial	auto[1]	39	1			T58	4		T60	3		T127	2
auto[TlIntgErrData]	full_word	auto[0]	3	1			T132	1		T128	2		-	-
auto[TlIntgErrData]	full_word	auto[1]	7	1			T60	2		T133	1		T130	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T58	2		T59	2		T60	4
auto[TlIntgErrBoth]	partial	auto[1]	46	1			T58	8		T59	4		T60	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T58	1		T134	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T128	1		T126	1		-	-