Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	867855	1			T1	165		T4	34		T5	13841
auto[1]	11246693	1			T1	33		T4	6		T5	14370
auto[2]	649182	1			T1	145		T4	31		T5	12068
auto[3]	10986048	1			T1	18		T4	5		T5	13055

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14752869	1			T1	289		T4	59		T5	1142
auto[1]	2269412	1			T1	36		T4	7		T5	6181
auto[2]	2307099	1			T1	35		T4	8		T5	7630
auto[3]	4420398	1			T1	1		T4	2		T5	38381

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9975610

1

T1

361

T4

76

T5

7

auto[1]

13774168

1

T5

53327

T11

220881

T40

2

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	464089	1			T1	142		T4	28		T22	38
auto[0]	auto[0]	auto[1]	47694	1			T1	11		T4	2		T22	4
auto[0]	auto[0]	auto[2]	47514	1			T1	12		T4	3		T22	4
auto[0]	auto[0]	auto[3]	56179	1			T4	1		T22	1		T40	8676
auto[0]	auto[1]	auto[0]	3474396	1			T1	19		T4	4		T22	443
auto[0]	auto[1]	auto[1]	373975	1			T1	13		T4	2		T22	103
auto[0]	auto[1]	auto[2]	377075	1			T22	51		T40	117		T49	703
auto[0]	auto[1]	auto[3]	326726	1			T1	1		T5	3		T22	13
auto[0]	auto[2]	auto[0]	342187	1			T1	122		T4	27		T39	4
auto[0]	auto[2]	auto[1]	37993	1			T1	12		T4	2		T40	740
auto[0]	auto[2]	auto[2]	36620	1			T1	11		T4	2		T22	33
auto[0]	auto[2]	auto[3]	39440	1			T5	3		T22	4		T40	6131
auto[0]	auto[3]	auto[0]	3319512	1			T1	6		T22	278		T44	3712
auto[0]	auto[3]	auto[1]	358588	1			T4	1		T22	24		T40	59
auto[0]	auto[3]	auto[2]	376607	1			T1	12		T4	3		T22	83
auto[0]	auto[3]	auto[3]	297015	1			T4	1		T5	1		T22	10
auto[1]	auto[0]	auto[0]	8372	1			T5	459		T140	1		T106	939
auto[1]	auto[0]	auto[1]	37370	1			T5	2063		T106	4139		T141	4350
auto[1]	auto[0]	auto[2]	37453	1			T5	2096		T106	4075		T141	4407
auto[1]	auto[0]	auto[3]	169184	1			T5	9223		T40	2		T91	1
auto[1]	auto[1]	auto[0]	3572603	1			T5	300		T11	91789		T48	62889
auto[1]	auto[1]	auto[1]	700290	1			T5	2339		T11	8857		T48	5849
auto[1]	auto[1]	auto[2]	706223	1			T5	1310		T11	9040		T48	6329
auto[1]	auto[1]	auto[3]	1715405	1			T5	10418		T11	869		T48	591
auto[1]	auto[2]	auto[0]	5170	1			T5	264		T106	828		T142	1
auto[1]	auto[2]	auto[1]	23104	1			T5	1250		T106	3864		T143	1
auto[1]	auto[2]	auto[2]	29968	1			T5	1974		T106	2769		T141	2932
auto[1]	auto[2]	auto[3]	134700	1			T5	8577		T106	12577		T141	13448
auto[1]	auto[3]	auto[0]	3566540	1			T5	119		T11	91374		T48	62878
auto[1]	auto[3]	auto[1]	690398	1			T5	529		T11	8947		T48	6376
auto[1]	auto[3]	auto[2]	695639	1			T5	2250		T11	9048		T48	5741
auto[1]	auto[3]	auto[3]	1681749	1			T5	10156		T11	957		T48	604