Unified Coverage Report :: Module :: prim_mubi8_sync

Module : prim_mubi8_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch	100.00	100.00					100.00

---

Module Instance : tb.dut.gen_instr_ctrl.u_prim_mubi8_sync_otp_en_sram_ifetch

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[4].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[5].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[6].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[7].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_mubi8_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Module : prim_mubi8_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	904	904	0	0
OutputsKnown_A	1315372475	1315256608	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	1315372475	1315243234	0	2712

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	904	904	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1315372475	1315256608	0	0
T1	132659	132489	0	0
T2	1586	1515	0	0
T3	152189	152125	0	0
T4	102123	102070	0	0
T5	171090	171084	0	0
T8	187520	187512	0	0
T9	899233	899158	0	0
T10	898705	898696	0	0
T11	439923	439830	0	0
T12	901007	900945	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1315372475	1315243234	0	2712
T1	132659	132456	0	3
T2	1586	1512	0	3
T3	152189	152122	0	3
T4	102123	102060	0	3
T5	171090	171084	0	3
T8	187520	187512	0	3
T9	899233	899155	0	3
T10	898705	898696	0	3
T11	439923	439827	0	3
T12	901007	900942	0	3