Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1327000469	228965	0	0
ctrl_regwen_rd_A	1327000469	4873	0	0
exec_rd_A	1327000469	4400	0	0
exec_regwen_rd_A	1327000469	4970	0	0
readback_rd_A	1327000469	3074	0	0
readback_regwen_rd_A	1327000469	2790	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1327000469	228965	0	0
T1	132659	5239	0	0
T2	1586	0	0	0
T3	152189	0	0	0
T4	102123	0	0	0
T5	171090	0	0	0
T8	187520	0	0	0
T9	899233	0	0	0
T10	898705	0	0	0
T11	439923	0	0	0
T12	901007	0	0	0
T20	0	8356	0	0
T21	0	3857	0	0
T23	0	2993	0	0
T54	0	7693	0	0
T56	0	13284	0	0
T64	0	2652	0	0
T66	0	4313	0	0
T67	0	8595	0	0
T68	0	1566	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1327000469	4873	0	0
T20	278928	0	0	0
T26	33445	0	0	0
T27	35739	0	0	0
T52	525627	0	0	0
T64	83914	237	0	0
T108	0	375	0	0
T109	0	44	0	0
T110	0	81	0	0
T111	0	40	0	0
T112	0	207	0	0
T113	0	221	0	0
T114	0	500	0	0
T115	0	381	0	0
T116	0	209	0	0
T117	62302	0	0	0
T118	131205	0	0	0
T119	194980	0	0	0
T120	103622	0	0	0
T121	765600	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1327000469	4400	0	0
T20	278928	0	0	0
T26	33445	0	0	0
T27	35739	0	0	0
T52	525627	0	0	0
T64	83914	227	0	0
T108	0	328	0	0
T109	0	43	0	0
T110	0	107	0	0
T111	0	34	0	0
T112	0	146	0	0
T113	0	200	0	0
T114	0	363	0	0
T115	0	420	0	0
T116	0	178	0	0
T117	62302	0	0	0
T118	131205	0	0	0
T119	194980	0	0	0
T120	103622	0	0	0
T121	765600	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1327000469	4970	0	0
T20	278928	0	0	0
T26	33445	0	0	0
T27	35739	0	0	0
T52	525627	0	0	0
T64	83914	265	0	0
T108	0	387	0	0
T109	0	36	0	0
T110	0	100	0	0
T111	0	31	0	0
T112	0	217	0	0
T113	0	171	0	0
T114	0	411	0	0
T115	0	292	0	0
T116	0	178	0	0
T117	62302	0	0	0
T118	131205	0	0	0
T119	194980	0	0	0
T120	103622	0	0	0
T121	765600	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1327000469	3074	0	0
T20	278928	0	0	0
T26	33445	0	0	0
T27	35739	0	0	0
T52	525627	0	0	0
T64	83914	220	0	0
T108	0	282	0	0
T109	0	27	0	0
T110	0	109	0	0
T111	0	31	0	0
T112	0	78	0	0
T113	0	186	0	0
T114	0	401	0	0
T115	0	467	0	0
T116	0	193	0	0
T117	62302	0	0	0
T118	131205	0	0	0
T119	194980	0	0	0
T120	103622	0	0	0
T121	765600	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1327000469	2790	0	0
T20	278928	0	0	0
T26	33445	0	0	0
T27	35739	0	0	0
T52	525627	0	0	0
T64	83914	183	0	0
T108	0	313	0	0
T109	0	33	0	0
T110	0	43	0	0
T111	0	4	0	0
T112	0	151	0	0
T113	0	174	0	0
T114	0	329	0	0
T115	0	415	0	0
T116	0	154	0	0
T117	62302	0	0	0
T118	131205	0	0	0
T119	194980	0	0	0
T120	103622	0	0	0
T121	765600	0	0	0