Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	354891956	1			T1	328936		T2	437960		T3	126706
instr_valid_dis	323514946	1			T1	328936		T2	437960		T3	126706
instr_en	20132163	1			T24	422544		T23	13878		T6	4536

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	10609356	1			T24	74972		T23	11434		T6	40014
sram_ifetch_valid_disable	314510528	1			T1	328936		T2	437960		T3	126706
sram_ifetch_enable	29772072	1			T24	190468		T6	251474		T22	130863

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	354891956	1			T1	328936		T2	437960		T3	126706
hw_debug_en_valid_off	311894465	1			T1	328936		T2	437960		T3	126706
hw_debug_en_on	28869391	1			T24	118228		T6	255735		T22	152728

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	314510528	1			T1	328936		T2	437960		T3	126706
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	301379868	1			T1	328936		T2	437960		T3	126706
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	7778785	1			T24	157104		T23	2444		T22	52792
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4101642	1			T24	67360		T23	11434		T6	17094
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	2006014	1			T6	17094		T22	7554		T69	75558
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1701792	1			T24	67360		T23	11434		T132	104196
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4188070	1			T24	7612		T6	638		T22	38500
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1415576	1			T6	638		T22	19340		T42	9518
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1928136	1			T24	7612		T36	17756		T131	8168
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	12101721	1			T24	71760		T6	83694		T22	79408
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	5524242	1			T6	83694		T22	58050		T69	53440
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3344543	1			T24	71760		T22	21358		T42	15330

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	7746540	1			T24	190468		T6	4536		T22	12846
lc_exec_en	12579600	1			T24	38856		T6	247301		T22	34820
valid_exec_dis	316439583	1			T1	328936		T2	437960		T3	126706
invalid_exec_dis	40381428	1			T24	265440		T23	11434		T6	255476