Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	148516925	1			T1	149595		T2	199147		T3	3202
triple_byte_access	2788619	1			T1	3004		T2	3923		T3	7004
halfword_access	4277115	1			T1	4402		T2	6037		T3	13079
byte_access	5971448	1			T1	5914		T2	7868		T3	25308
zero_access	1790389	1			T1	1553		T2	2005		T3	14760

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

81259341

1

T1

82034

T2

109844

T3

31770

auto[1]

82085155

1

T1

82434

T2

109136

T3

31583

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	73717879	1			T1	74624		T2	99942		T3	283
auto[0]	triple_byte_access	1333302	1			T1	1499		T2	1937		T3	1336
auto[0]	halfword_access	2091427	1			T1	2178		T2	3056		T3	4598
auto[0]	byte_access	3054147	1			T1	2939		T2	3888		T3	13655
auto[0]	zero_access	1062586	1			T1	794		T2	1021		T3	11898
auto[1]	word_access	74799046	1			T1	74971		T2	99205		T3	2919
auto[1]	triple_byte_access	1455317	1			T1	1505		T2	1986		T3	5668
auto[1]	halfword_access	2185688	1			T1	2224		T2	2981		T3	8481
auto[1]	byte_access	2917301	1			T1	2975		T2	3980		T3	11653
auto[1]	zero_access	727803	1			T1	759		T2	984		T3	2862