| T796 |
/workspace/coverage/default/22.sram_ctrl_regwen.1747037033 |
|
|
Jul 14 07:23:48 PM PDT 24 |
Jul 14 07:41:05 PM PDT 24 |
26100140700 ps |
| T797 |
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.2962005072 |
|
|
Jul 14 07:23:19 PM PDT 24 |
Jul 14 07:25:36 PM PDT 24 |
1074738229 ps |
| T798 |
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.423505702 |
|
|
Jul 14 07:23:10 PM PDT 24 |
Jul 14 07:24:29 PM PDT 24 |
9161164397 ps |
| T799 |
/workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.4237481419 |
|
|
Jul 14 07:22:54 PM PDT 24 |
Jul 14 07:24:15 PM PDT 24 |
3089956519 ps |
| T800 |
/workspace/coverage/default/19.sram_ctrl_bijection.2412452489 |
|
|
Jul 14 07:23:34 PM PDT 24 |
Jul 14 08:04:36 PM PDT 24 |
189614335448 ps |
| T112 |
/workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.3312895597 |
|
|
Jul 14 07:23:26 PM PDT 24 |
Jul 14 07:24:05 PM PDT 24 |
1322200626 ps |
| T45 |
/workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.3908158642 |
|
|
Jul 14 07:22:58 PM PDT 24 |
Jul 14 07:24:34 PM PDT 24 |
3099158874 ps |
| T801 |
/workspace/coverage/default/17.sram_ctrl_stress_all.1262805595 |
|
|
Jul 14 07:23:26 PM PDT 24 |
Jul 14 08:14:28 PM PDT 24 |
126053694560 ps |
| T802 |
/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.424985792 |
|
|
Jul 14 07:23:43 PM PDT 24 |
Jul 14 07:32:42 PM PDT 24 |
8937203595 ps |
| T803 |
/workspace/coverage/default/29.sram_ctrl_stress_all.3002991907 |
|
|
Jul 14 07:24:12 PM PDT 24 |
Jul 14 08:39:48 PM PDT 24 |
61811116028 ps |
| T804 |
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.1510716926 |
|
|
Jul 14 07:23:02 PM PDT 24 |
Jul 14 07:24:01 PM PDT 24 |
754234219 ps |
| T805 |
/workspace/coverage/default/1.sram_ctrl_partial_access.354070702 |
|
|
Jul 14 07:22:58 PM PDT 24 |
Jul 14 07:23:54 PM PDT 24 |
756189604 ps |
| T806 |
/workspace/coverage/default/18.sram_ctrl_bijection.1533060750 |
|
|
Jul 14 07:23:36 PM PDT 24 |
Jul 14 07:59:26 PM PDT 24 |
116713169996 ps |
| T807 |
/workspace/coverage/default/26.sram_ctrl_mem_walk.2857426736 |
|
|
Jul 14 07:23:59 PM PDT 24 |
Jul 14 07:26:18 PM PDT 24 |
1980447411 ps |
| T808 |
/workspace/coverage/default/9.sram_ctrl_regwen.2676763614 |
|
|
Jul 14 07:23:07 PM PDT 24 |
Jul 14 07:34:04 PM PDT 24 |
31249447267 ps |
| T809 |
/workspace/coverage/default/37.sram_ctrl_executable.3059578268 |
|
|
Jul 14 07:24:54 PM PDT 24 |
Jul 14 07:47:28 PM PDT 24 |
25497408406 ps |
| T810 |
/workspace/coverage/default/17.sram_ctrl_executable.531948623 |
|
|
Jul 14 07:23:43 PM PDT 24 |
Jul 14 07:26:11 PM PDT 24 |
1024335007 ps |
| T811 |
/workspace/coverage/default/46.sram_ctrl_ram_cfg.3457221010 |
|
|
Jul 14 07:25:47 PM PDT 24 |
Jul 14 07:25:51 PM PDT 24 |
350804610 ps |
| T812 |
/workspace/coverage/default/20.sram_ctrl_ram_cfg.1349535000 |
|
|
Jul 14 07:23:42 PM PDT 24 |
Jul 14 07:24:01 PM PDT 24 |
1401694047 ps |
| T813 |
/workspace/coverage/default/2.sram_ctrl_stress_pipeline.760061942 |
|
|
Jul 14 07:22:59 PM PDT 24 |
Jul 14 07:28:10 PM PDT 24 |
35548523150 ps |
| T814 |
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.1761233418 |
|
|
Jul 14 07:26:01 PM PDT 24 |
Jul 14 07:27:21 PM PDT 24 |
2371362231 ps |
| T815 |
/workspace/coverage/default/26.sram_ctrl_ram_cfg.3664588853 |
|
|
Jul 14 07:24:00 PM PDT 24 |
Jul 14 07:24:17 PM PDT 24 |
1410023464 ps |
| T816 |
/workspace/coverage/default/2.sram_ctrl_lc_escalation.1542974575 |
|
|
Jul 14 07:23:01 PM PDT 24 |
Jul 14 07:23:46 PM PDT 24 |
3030430414 ps |
| T817 |
/workspace/coverage/default/16.sram_ctrl_mem_partial_access.580702617 |
|
|
Jul 14 07:23:25 PM PDT 24 |
Jul 14 07:25:01 PM PDT 24 |
5130745975 ps |
| T818 |
/workspace/coverage/default/30.sram_ctrl_mem_partial_access.3472636694 |
|
|
Jul 14 07:24:23 PM PDT 24 |
Jul 14 07:25:50 PM PDT 24 |
2763015020 ps |
| T819 |
/workspace/coverage/default/14.sram_ctrl_stress_all.4073853482 |
|
|
Jul 14 07:23:42 PM PDT 24 |
Jul 14 08:40:36 PM PDT 24 |
139679543812 ps |
| T820 |
/workspace/coverage/default/17.sram_ctrl_max_throughput.3138064906 |
|
|
Jul 14 07:23:40 PM PDT 24 |
Jul 14 07:24:23 PM PDT 24 |
1492855434 ps |
| T821 |
/workspace/coverage/default/15.sram_ctrl_mem_partial_access.1741901159 |
|
|
Jul 14 07:23:27 PM PDT 24 |
Jul 14 07:25:00 PM PDT 24 |
1417695618 ps |
| T822 |
/workspace/coverage/default/42.sram_ctrl_executable.155885418 |
|
|
Jul 14 07:25:20 PM PDT 24 |
Jul 14 07:33:27 PM PDT 24 |
8029880516 ps |
| T823 |
/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.723539325 |
|
|
Jul 14 07:23:46 PM PDT 24 |
Jul 14 07:24:28 PM PDT 24 |
2648861824 ps |
| T824 |
/workspace/coverage/default/0.sram_ctrl_stress_all.1155262361 |
|
|
Jul 14 07:22:58 PM PDT 24 |
Jul 14 08:38:43 PM PDT 24 |
30878717943 ps |
| T825 |
/workspace/coverage/default/5.sram_ctrl_multiple_keys.2411350029 |
|
|
Jul 14 07:23:02 PM PDT 24 |
Jul 14 07:34:53 PM PDT 24 |
13093754966 ps |
| T826 |
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.2737242851 |
|
|
Jul 14 07:25:30 PM PDT 24 |
Jul 14 07:28:08 PM PDT 24 |
21678426697 ps |
| T827 |
/workspace/coverage/default/25.sram_ctrl_stress_pipeline.563767509 |
|
|
Jul 14 07:23:53 PM PDT 24 |
Jul 14 07:27:31 PM PDT 24 |
6650126188 ps |
| T828 |
/workspace/coverage/default/3.sram_ctrl_lc_escalation.564160433 |
|
|
Jul 14 07:23:01 PM PDT 24 |
Jul 14 07:23:58 PM PDT 24 |
4402570292 ps |
| T829 |
/workspace/coverage/default/39.sram_ctrl_lc_escalation.3502304481 |
|
|
Jul 14 07:25:05 PM PDT 24 |
Jul 14 07:26:02 PM PDT 24 |
9572903328 ps |
| T830 |
/workspace/coverage/default/35.sram_ctrl_partial_access.3289713697 |
|
|
Jul 14 07:24:43 PM PDT 24 |
Jul 14 07:25:23 PM PDT 24 |
2738320128 ps |
| T831 |
/workspace/coverage/default/31.sram_ctrl_executable.1756363121 |
|
|
Jul 14 07:24:23 PM PDT 24 |
Jul 14 07:36:38 PM PDT 24 |
50210182415 ps |
| T832 |
/workspace/coverage/default/14.sram_ctrl_executable.959460688 |
|
|
Jul 14 07:23:39 PM PDT 24 |
Jul 14 07:39:04 PM PDT 24 |
13286259111 ps |
| T833 |
/workspace/coverage/default/6.sram_ctrl_smoke.4036077095 |
|
|
Jul 14 07:23:00 PM PDT 24 |
Jul 14 07:24:42 PM PDT 24 |
3278629904 ps |
| T834 |
/workspace/coverage/default/49.sram_ctrl_regwen.225203327 |
|
|
Jul 14 07:26:13 PM PDT 24 |
Jul 14 07:45:50 PM PDT 24 |
2920764815 ps |
| T835 |
/workspace/coverage/default/2.sram_ctrl_regwen.4227810263 |
|
|
Jul 14 07:22:56 PM PDT 24 |
Jul 14 07:30:44 PM PDT 24 |
41723417171 ps |
| T836 |
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.2091099106 |
|
|
Jul 14 07:26:10 PM PDT 24 |
Jul 14 07:51:40 PM PDT 24 |
40166988479 ps |
| T837 |
/workspace/coverage/default/34.sram_ctrl_executable.706620883 |
|
|
Jul 14 07:24:37 PM PDT 24 |
Jul 14 07:36:02 PM PDT 24 |
47677002801 ps |
| T838 |
/workspace/coverage/default/41.sram_ctrl_multiple_keys.752764902 |
|
|
Jul 14 07:25:11 PM PDT 24 |
Jul 14 07:35:32 PM PDT 24 |
18861176044 ps |
| T839 |
/workspace/coverage/default/5.sram_ctrl_alert_test.679264355 |
|
|
Jul 14 07:23:07 PM PDT 24 |
Jul 14 07:23:35 PM PDT 24 |
13807309 ps |
| T840 |
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.3194945279 |
|
|
Jul 14 07:23:09 PM PDT 24 |
Jul 14 07:26:24 PM PDT 24 |
40348965245 ps |
| T841 |
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.3497515025 |
|
|
Jul 14 07:26:05 PM PDT 24 |
Jul 14 07:27:10 PM PDT 24 |
1999971181 ps |
| T842 |
/workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.3675810107 |
|
|
Jul 14 07:23:51 PM PDT 24 |
Jul 14 07:24:30 PM PDT 24 |
753457616 ps |
| T843 |
/workspace/coverage/default/35.sram_ctrl_bijection.3075408388 |
|
|
Jul 14 07:24:44 PM PDT 24 |
Jul 14 07:37:15 PM PDT 24 |
66213950706 ps |
| T844 |
/workspace/coverage/default/47.sram_ctrl_bijection.1179014533 |
|
|
Jul 14 07:25:54 PM PDT 24 |
Jul 14 07:41:17 PM PDT 24 |
100105696731 ps |
| T845 |
/workspace/coverage/default/34.sram_ctrl_ram_cfg.876918351 |
|
|
Jul 14 07:24:39 PM PDT 24 |
Jul 14 07:24:45 PM PDT 24 |
1405834033 ps |
| T846 |
/workspace/coverage/default/49.sram_ctrl_bijection.1141305334 |
|
|
Jul 14 07:26:07 PM PDT 24 |
Jul 14 07:48:35 PM PDT 24 |
60017785777 ps |
| T847 |
/workspace/coverage/default/7.sram_ctrl_bijection.4110769951 |
|
|
Jul 14 07:23:09 PM PDT 24 |
Jul 14 07:38:39 PM PDT 24 |
154383429444 ps |
| T848 |
/workspace/coverage/default/41.sram_ctrl_stress_pipeline.1774781397 |
|
|
Jul 14 07:25:15 PM PDT 24 |
Jul 14 07:29:10 PM PDT 24 |
11785392091 ps |
| T849 |
/workspace/coverage/default/32.sram_ctrl_partial_access.449800316 |
|
|
Jul 14 07:24:29 PM PDT 24 |
Jul 14 07:24:55 PM PDT 24 |
1550393960 ps |
| T850 |
/workspace/coverage/default/28.sram_ctrl_bijection.1344275683 |
|
|
Jul 14 07:24:02 PM PDT 24 |
Jul 14 07:59:40 PM PDT 24 |
59541716186 ps |
| T851 |
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.2186202596 |
|
|
Jul 14 07:25:35 PM PDT 24 |
Jul 14 07:26:52 PM PDT 24 |
1427478897 ps |
| T852 |
/workspace/coverage/default/27.sram_ctrl_ram_cfg.956283396 |
|
|
Jul 14 07:24:02 PM PDT 24 |
Jul 14 07:24:17 PM PDT 24 |
347085771 ps |
| T853 |
/workspace/coverage/default/24.sram_ctrl_lc_escalation.2017934384 |
|
|
Jul 14 07:23:56 PM PDT 24 |
Jul 14 07:25:07 PM PDT 24 |
30879935803 ps |
| T854 |
/workspace/coverage/default/47.sram_ctrl_max_throughput.1121917921 |
|
|
Jul 14 07:25:53 PM PDT 24 |
Jul 14 07:27:20 PM PDT 24 |
2972783127 ps |
| T855 |
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.2019664178 |
|
|
Jul 14 07:25:45 PM PDT 24 |
Jul 14 07:28:13 PM PDT 24 |
3261442041 ps |
| T856 |
/workspace/coverage/default/3.sram_ctrl_partial_access.1488548846 |
|
|
Jul 14 07:22:52 PM PDT 24 |
Jul 14 07:23:38 PM PDT 24 |
4893346228 ps |
| T857 |
/workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.376462187 |
|
|
Jul 14 07:25:00 PM PDT 24 |
Jul 14 07:25:25 PM PDT 24 |
679993047 ps |
| T858 |
/workspace/coverage/default/15.sram_ctrl_alert_test.1506232572 |
|
|
Jul 14 07:23:43 PM PDT 24 |
Jul 14 07:23:59 PM PDT 24 |
32080909 ps |
| T859 |
/workspace/coverage/default/39.sram_ctrl_alert_test.1560280136 |
|
|
Jul 14 07:25:05 PM PDT 24 |
Jul 14 07:25:06 PM PDT 24 |
13124978 ps |
| T860 |
/workspace/coverage/default/36.sram_ctrl_ram_cfg.2866537854 |
|
|
Jul 14 07:24:50 PM PDT 24 |
Jul 14 07:24:57 PM PDT 24 |
2112501335 ps |
| T861 |
/workspace/coverage/default/28.sram_ctrl_ram_cfg.1577320130 |
|
|
Jul 14 07:24:00 PM PDT 24 |
Jul 14 07:24:16 PM PDT 24 |
361210018 ps |
| T862 |
/workspace/coverage/default/27.sram_ctrl_alert_test.1530247757 |
|
|
Jul 14 07:24:04 PM PDT 24 |
Jul 14 07:24:16 PM PDT 24 |
16790092 ps |
| T863 |
/workspace/coverage/default/27.sram_ctrl_stress_pipeline.1588162566 |
|
|
Jul 14 07:23:59 PM PDT 24 |
Jul 14 07:28:30 PM PDT 24 |
59537868852 ps |
| T864 |
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.1837114479 |
|
|
Jul 14 07:23:10 PM PDT 24 |
Jul 14 07:41:25 PM PDT 24 |
48731435795 ps |
| T865 |
/workspace/coverage/default/23.sram_ctrl_regwen.6487194 |
|
|
Jul 14 07:23:56 PM PDT 24 |
Jul 14 07:27:10 PM PDT 24 |
3368245491 ps |
| T866 |
/workspace/coverage/default/31.sram_ctrl_access_during_key_req.3480294382 |
|
|
Jul 14 07:24:22 PM PDT 24 |
Jul 14 07:44:34 PM PDT 24 |
13955466830 ps |
| T867 |
/workspace/coverage/default/39.sram_ctrl_access_during_key_req.3797594974 |
|
|
Jul 14 07:25:05 PM PDT 24 |
Jul 14 07:41:36 PM PDT 24 |
60336525796 ps |
| T868 |
/workspace/coverage/default/23.sram_ctrl_lc_escalation.696690828 |
|
|
Jul 14 07:23:49 PM PDT 24 |
Jul 14 07:25:15 PM PDT 24 |
43759069943 ps |
| T869 |
/workspace/coverage/default/49.sram_ctrl_mem_walk.1409920099 |
|
|
Jul 14 07:26:15 PM PDT 24 |
Jul 14 07:28:20 PM PDT 24 |
3951317575 ps |
| T870 |
/workspace/coverage/default/23.sram_ctrl_bijection.3483432232 |
|
|
Jul 14 07:23:51 PM PDT 24 |
Jul 14 07:48:35 PM PDT 24 |
260702270113 ps |
| T871 |
/workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.2700814482 |
|
|
Jul 14 07:25:17 PM PDT 24 |
Jul 14 07:25:40 PM PDT 24 |
508237600 ps |
| T872 |
/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.49593054 |
|
|
Jul 14 07:24:37 PM PDT 24 |
Jul 14 07:30:11 PM PDT 24 |
34507457752 ps |
| T873 |
/workspace/coverage/default/2.sram_ctrl_multiple_keys.84630475 |
|
|
Jul 14 07:22:49 PM PDT 24 |
Jul 14 07:48:53 PM PDT 24 |
15206112888 ps |
| T874 |
/workspace/coverage/default/41.sram_ctrl_stress_all.1021963518 |
|
|
Jul 14 07:25:15 PM PDT 24 |
Jul 14 09:15:10 PM PDT 24 |
376112856205 ps |
| T86 |
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.4284164064 |
|
|
Jul 14 07:23:00 PM PDT 24 |
Jul 14 07:24:44 PM PDT 24 |
7682481586 ps |
| T875 |
/workspace/coverage/default/46.sram_ctrl_regwen.3742698330 |
|
|
Jul 14 07:25:49 PM PDT 24 |
Jul 14 07:37:49 PM PDT 24 |
9012178230 ps |
| T876 |
/workspace/coverage/default/17.sram_ctrl_mem_walk.3265825953 |
|
|
Jul 14 07:23:38 PM PDT 24 |
Jul 14 07:26:44 PM PDT 24 |
17293613407 ps |
| T877 |
/workspace/coverage/default/41.sram_ctrl_bijection.182991785 |
|
|
Jul 14 07:25:16 PM PDT 24 |
Jul 14 07:47:32 PM PDT 24 |
113042774211 ps |
| T878 |
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.1490678147 |
|
|
Jul 14 07:23:19 PM PDT 24 |
Jul 14 07:26:24 PM PDT 24 |
5413228525 ps |
| T879 |
/workspace/coverage/default/16.sram_ctrl_stress_all.2579839383 |
|
|
Jul 14 07:23:43 PM PDT 24 |
Jul 14 08:26:37 PM PDT 24 |
48173231329 ps |
| T880 |
/workspace/coverage/default/42.sram_ctrl_stress_all.3175704550 |
|
|
Jul 14 07:25:23 PM PDT 24 |
Jul 14 08:39:35 PM PDT 24 |
147193008051 ps |
| T881 |
/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.2411716968 |
|
|
Jul 14 07:24:12 PM PDT 24 |
Jul 14 07:24:37 PM PDT 24 |
2816981237 ps |
| T882 |
/workspace/coverage/default/0.sram_ctrl_executable.1313428967 |
|
|
Jul 14 07:22:56 PM PDT 24 |
Jul 14 07:36:57 PM PDT 24 |
24100508945 ps |
| T883 |
/workspace/coverage/default/29.sram_ctrl_smoke.3136261712 |
|
|
Jul 14 07:24:09 PM PDT 24 |
Jul 14 07:24:22 PM PDT 24 |
401171035 ps |
| T884 |
/workspace/coverage/default/12.sram_ctrl_partial_access.1996521220 |
|
|
Jul 14 07:23:12 PM PDT 24 |
Jul 14 07:23:57 PM PDT 24 |
729585582 ps |
| T885 |
/workspace/coverage/default/3.sram_ctrl_access_during_key_req.3876279762 |
|
|
Jul 14 07:22:52 PM PDT 24 |
Jul 14 07:31:35 PM PDT 24 |
7636102773 ps |
| T886 |
/workspace/coverage/default/1.sram_ctrl_bijection.609625328 |
|
|
Jul 14 07:23:00 PM PDT 24 |
Jul 14 07:38:22 PM PDT 24 |
71443388364 ps |
| T887 |
/workspace/coverage/default/10.sram_ctrl_bijection.4284844511 |
|
|
Jul 14 07:23:10 PM PDT 24 |
Jul 14 07:37:59 PM PDT 24 |
38299140778 ps |
| T888 |
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.72694629 |
|
|
Jul 14 07:23:09 PM PDT 24 |
Jul 14 07:24:41 PM PDT 24 |
3985142393 ps |
| T889 |
/workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.4133922221 |
|
|
Jul 14 07:24:57 PM PDT 24 |
Jul 14 07:25:58 PM PDT 24 |
772337792 ps |
| T890 |
/workspace/coverage/default/7.sram_ctrl_executable.540090350 |
|
|
Jul 14 07:23:09 PM PDT 24 |
Jul 14 07:41:34 PM PDT 24 |
32991455014 ps |
| T891 |
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.543718812 |
|
|
Jul 14 07:25:34 PM PDT 24 |
Jul 14 07:56:03 PM PDT 24 |
58275694039 ps |
| T892 |
/workspace/coverage/default/48.sram_ctrl_multiple_keys.3595203843 |
|
|
Jul 14 07:26:00 PM PDT 24 |
Jul 14 07:56:09 PM PDT 24 |
172424968405 ps |
| T893 |
/workspace/coverage/default/30.sram_ctrl_stress_all.3673196003 |
|
|
Jul 14 07:24:20 PM PDT 24 |
Jul 14 08:45:08 PM PDT 24 |
188213337240 ps |
| T894 |
/workspace/coverage/default/9.sram_ctrl_bijection.2462696831 |
|
|
Jul 14 07:23:08 PM PDT 24 |
Jul 14 08:17:53 PM PDT 24 |
689416587122 ps |
| T895 |
/workspace/coverage/default/34.sram_ctrl_mem_walk.1551008863 |
|
|
Jul 14 07:24:38 PM PDT 24 |
Jul 14 07:27:34 PM PDT 24 |
10678133310 ps |
| T896 |
/workspace/coverage/default/8.sram_ctrl_executable.2317420402 |
|
|
Jul 14 07:23:06 PM PDT 24 |
Jul 14 07:37:38 PM PDT 24 |
17724019853 ps |
| T897 |
/workspace/coverage/default/27.sram_ctrl_smoke.3650733328 |
|
|
Jul 14 07:23:59 PM PDT 24 |
Jul 14 07:25:46 PM PDT 24 |
2284971965 ps |
| T898 |
/workspace/coverage/default/3.sram_ctrl_smoke.1140377795 |
|
|
Jul 14 07:22:57 PM PDT 24 |
Jul 14 07:24:19 PM PDT 24 |
2922903475 ps |
| T899 |
/workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.3817560284 |
|
|
Jul 14 07:24:29 PM PDT 24 |
Jul 14 07:25:10 PM PDT 24 |
1447731339 ps |
| T900 |
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.3699267825 |
|
|
Jul 14 07:23:04 PM PDT 24 |
Jul 14 07:23:50 PM PDT 24 |
526216929 ps |
| T901 |
/workspace/coverage/default/32.sram_ctrl_executable.2709196680 |
|
|
Jul 14 07:24:28 PM PDT 24 |
Jul 14 07:44:06 PM PDT 24 |
31210541405 ps |
| T902 |
/workspace/coverage/default/23.sram_ctrl_executable.3479397496 |
|
|
Jul 14 07:23:47 PM PDT 24 |
Jul 14 07:34:10 PM PDT 24 |
21170983239 ps |
| T903 |
/workspace/coverage/default/20.sram_ctrl_regwen.2749567353 |
|
|
Jul 14 07:23:40 PM PDT 24 |
Jul 14 07:29:41 PM PDT 24 |
20371516344 ps |
| T904 |
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.1253125093 |
|
|
Jul 14 07:25:52 PM PDT 24 |
Jul 14 07:27:56 PM PDT 24 |
3695338770 ps |
| T905 |
/workspace/coverage/default/48.sram_ctrl_smoke.891933198 |
|
|
Jul 14 07:25:59 PM PDT 24 |
Jul 14 07:26:10 PM PDT 24 |
838726909 ps |
| T906 |
/workspace/coverage/default/10.sram_ctrl_lc_escalation.3586126378 |
|
|
Jul 14 07:23:20 PM PDT 24 |
Jul 14 07:24:37 PM PDT 24 |
45058170423 ps |
| T907 |
/workspace/coverage/default/24.sram_ctrl_multiple_keys.2922915888 |
|
|
Jul 14 07:23:46 PM PDT 24 |
Jul 14 07:39:59 PM PDT 24 |
40707495651 ps |
| T908 |
/workspace/coverage/default/23.sram_ctrl_partial_access.123843725 |
|
|
Jul 14 07:23:48 PM PDT 24 |
Jul 14 07:26:05 PM PDT 24 |
5557364053 ps |
| T909 |
/workspace/coverage/default/10.sram_ctrl_multiple_keys.4238491980 |
|
|
Jul 14 07:23:09 PM PDT 24 |
Jul 14 07:38:25 PM PDT 24 |
11352391643 ps |
| T910 |
/workspace/coverage/default/36.sram_ctrl_access_during_key_req.484617949 |
|
|
Jul 14 07:24:48 PM PDT 24 |
Jul 14 07:44:29 PM PDT 24 |
60547163435 ps |
| T87 |
/workspace/coverage/default/21.sram_ctrl_mem_partial_access.2154406881 |
|
|
Jul 14 07:23:49 PM PDT 24 |
Jul 14 07:25:31 PM PDT 24 |
12808980604 ps |
| T911 |
/workspace/coverage/default/6.sram_ctrl_mem_walk.1561354916 |
|
|
Jul 14 07:23:01 PM PDT 24 |
Jul 14 07:25:39 PM PDT 24 |
4295091023 ps |
| T912 |
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.1232748827 |
|
|
Jul 14 07:23:21 PM PDT 24 |
Jul 14 07:28:07 PM PDT 24 |
8756965521 ps |
| T913 |
/workspace/coverage/default/48.sram_ctrl_partial_access.2673123452 |
|
|
Jul 14 07:26:01 PM PDT 24 |
Jul 14 07:26:27 PM PDT 24 |
3223367218 ps |
| T914 |
/workspace/coverage/default/9.sram_ctrl_max_throughput.14565265 |
|
|
Jul 14 07:23:03 PM PDT 24 |
Jul 14 07:24:10 PM PDT 24 |
2580194642 ps |
| T915 |
/workspace/coverage/default/33.sram_ctrl_smoke.3956289510 |
|
|
Jul 14 07:24:39 PM PDT 24 |
Jul 14 07:25:19 PM PDT 24 |
3306224895 ps |
| T916 |
/workspace/coverage/default/12.sram_ctrl_bijection.1758882449 |
|
|
Jul 14 07:23:27 PM PDT 24 |
Jul 14 07:42:23 PM PDT 24 |
184687526807 ps |
| T917 |
/workspace/coverage/default/12.sram_ctrl_multiple_keys.3872846011 |
|
|
Jul 14 07:23:09 PM PDT 24 |
Jul 14 07:29:24 PM PDT 24 |
5543391864 ps |
| T918 |
/workspace/coverage/default/2.sram_ctrl_access_during_key_req.1007475799 |
|
|
Jul 14 07:22:55 PM PDT 24 |
Jul 14 07:26:18 PM PDT 24 |
2211454101 ps |
| T919 |
/workspace/coverage/default/29.sram_ctrl_ram_cfg.2683789974 |
|
|
Jul 14 07:24:16 PM PDT 24 |
Jul 14 07:24:23 PM PDT 24 |
1360678882 ps |
| T920 |
/workspace/coverage/default/33.sram_ctrl_lc_escalation.2733538100 |
|
|
Jul 14 07:24:34 PM PDT 24 |
Jul 14 07:24:54 PM PDT 24 |
11255766297 ps |
| T921 |
/workspace/coverage/default/45.sram_ctrl_bijection.1968968609 |
|
|
Jul 14 07:25:40 PM PDT 24 |
Jul 14 07:40:16 PM PDT 24 |
37844844515 ps |
| T922 |
/workspace/coverage/default/38.sram_ctrl_partial_access_b2b.2285430433 |
|
|
Jul 14 07:24:59 PM PDT 24 |
Jul 14 07:30:39 PM PDT 24 |
56514904270 ps |
| T923 |
/workspace/coverage/default/14.sram_ctrl_lc_escalation.4286248148 |
|
|
Jul 14 07:23:25 PM PDT 24 |
Jul 14 07:25:03 PM PDT 24 |
49625938972 ps |
| T924 |
/workspace/coverage/default/1.sram_ctrl_stress_all.2284634219 |
|
|
Jul 14 07:22:56 PM PDT 24 |
Jul 14 08:13:05 PM PDT 24 |
357191333262 ps |
| T925 |
/workspace/coverage/default/36.sram_ctrl_bijection.1810801223 |
|
|
Jul 14 07:24:52 PM PDT 24 |
Jul 14 07:34:21 PM PDT 24 |
193938341096 ps |
| T926 |
/workspace/coverage/default/44.sram_ctrl_mem_walk.3324228311 |
|
|
Jul 14 07:25:37 PM PDT 24 |
Jul 14 07:28:09 PM PDT 24 |
2717965740 ps |
| T927 |
/workspace/coverage/default/15.sram_ctrl_lc_escalation.4140264104 |
|
|
Jul 14 07:23:34 PM PDT 24 |
Jul 14 07:23:58 PM PDT 24 |
984766783 ps |
| T928 |
/workspace/coverage/default/18.sram_ctrl_stress_all.2568906899 |
|
|
Jul 14 07:23:45 PM PDT 24 |
Jul 14 08:50:34 PM PDT 24 |
1255430936673 ps |
| T929 |
/workspace/coverage/default/43.sram_ctrl_regwen.634316445 |
|
|
Jul 14 07:25:29 PM PDT 24 |
Jul 14 07:56:45 PM PDT 24 |
3440523464 ps |
| T930 |
/workspace/coverage/default/0.sram_ctrl_regwen.3673214254 |
|
|
Jul 14 07:23:01 PM PDT 24 |
Jul 14 07:32:18 PM PDT 24 |
11119686586 ps |
| T931 |
/workspace/coverage/default/41.sram_ctrl_regwen.913692839 |
|
|
Jul 14 07:25:11 PM PDT 24 |
Jul 14 07:58:24 PM PDT 24 |
16946387969 ps |
| T932 |
/workspace/coverage/default/17.sram_ctrl_bijection.947225737 |
|
|
Jul 14 07:23:42 PM PDT 24 |
Jul 14 07:58:26 PM PDT 24 |
29343936559 ps |
| T933 |
/workspace/coverage/default/41.sram_ctrl_max_throughput.3260459327 |
|
|
Jul 14 07:25:12 PM PDT 24 |
Jul 14 07:25:29 PM PDT 24 |
723953119 ps |
| T934 |
/workspace/coverage/default/30.sram_ctrl_max_throughput.1410596716 |
|
|
Jul 14 07:24:16 PM PDT 24 |
Jul 14 07:24:28 PM PDT 24 |
1446659448 ps |
| T935 |
/workspace/coverage/default/23.sram_ctrl_mem_partial_access.25338947 |
|
|
Jul 14 07:23:46 PM PDT 24 |
Jul 14 07:25:25 PM PDT 24 |
2780142757 ps |
| T936 |
/workspace/coverage/default/12.sram_ctrl_max_throughput.1440153722 |
|
|
Jul 14 07:23:12 PM PDT 24 |
Jul 14 07:24:43 PM PDT 24 |
743936282 ps |
| T937 |
/workspace/coverage/default/48.sram_ctrl_stress_all.4045025563 |
|
|
Jul 14 07:26:05 PM PDT 24 |
Jul 14 09:14:26 PM PDT 24 |
1272181273492 ps |
| T938 |
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.1810863011 |
|
|
Jul 14 07:23:23 PM PDT 24 |
Jul 14 07:24:59 PM PDT 24 |
5800053804 ps |
| T939 |
/workspace/coverage/default/15.sram_ctrl_multiple_keys.646661270 |
|
|
Jul 14 07:23:24 PM PDT 24 |
Jul 14 07:34:53 PM PDT 24 |
17820432938 ps |
| T940 |
/workspace/coverage/default/19.sram_ctrl_stress_all.2776034553 |
|
|
Jul 14 07:23:46 PM PDT 24 |
Jul 14 08:28:14 PM PDT 24 |
164458632056 ps |
| T941 |
/workspace/coverage/default/27.sram_ctrl_stress_all.2783551045 |
|
|
Jul 14 07:24:02 PM PDT 24 |
Jul 14 08:45:04 PM PDT 24 |
39308532694 ps |
| T942 |
/workspace/coverage/default/46.sram_ctrl_mem_walk.4293809302 |
|
|
Jul 14 07:25:46 PM PDT 24 |
Jul 14 07:28:29 PM PDT 24 |
6983971254 ps |
| T943 |
/workspace/coverage/default/27.sram_ctrl_access_during_key_req.1482945354 |
|
|
Jul 14 07:24:03 PM PDT 24 |
Jul 14 07:31:25 PM PDT 24 |
14866163109 ps |
| T944 |
/workspace/coverage/default/24.sram_ctrl_bijection.2989339791 |
|
|
Jul 14 07:23:48 PM PDT 24 |
Jul 14 07:38:49 PM PDT 24 |
50559104295 ps |
| T58 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3980509509 |
|
|
Jul 14 06:33:09 PM PDT 24 |
Jul 14 06:34:13 PM PDT 24 |
28179078828 ps |
| T945 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.202114090 |
|
|
Jul 14 06:33:43 PM PDT 24 |
Jul 14 06:33:47 PM PDT 24 |
41359595 ps |
| T59 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1582253703 |
|
|
Jul 14 06:33:20 PM PDT 24 |
Jul 14 06:34:18 PM PDT 24 |
22784408377 ps |
| T55 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2851795390 |
|
|
Jul 14 06:33:23 PM PDT 24 |
Jul 14 06:33:25 PM PDT 24 |
623224776 ps |
| T56 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.754436155 |
|
|
Jul 14 06:33:34 PM PDT 24 |
Jul 14 06:33:36 PM PDT 24 |
367957995 ps |
| T57 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.357568786 |
|
|
Jul 14 06:33:09 PM PDT 24 |
Jul 14 06:33:15 PM PDT 24 |
168413119 ps |
| T70 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3305862140 |
|
|
Jul 14 06:33:09 PM PDT 24 |
Jul 14 06:33:13 PM PDT 24 |
11925337 ps |
| T946 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.784505494 |
|
|
Jul 14 06:33:42 PM PDT 24 |
Jul 14 06:33:47 PM PDT 24 |
219357790 ps |
| T95 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1630020219 |
|
|
Jul 14 06:33:15 PM PDT 24 |
Jul 14 06:33:16 PM PDT 24 |
23577586 ps |
| T104 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2034025708 |
|
|
Jul 14 06:33:00 PM PDT 24 |
Jul 14 06:33:04 PM PDT 24 |
93488219 ps |
| T96 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1598805665 |
|
|
Jul 14 06:33:30 PM PDT 24 |
Jul 14 06:33:32 PM PDT 24 |
60522085 ps |
| T947 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1564482134 |
|
|
Jul 14 06:33:22 PM PDT 24 |
Jul 14 06:33:27 PM PDT 24 |
1489862705 ps |
| T97 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1757591225 |
|
|
Jul 14 06:33:16 PM PDT 24 |
Jul 14 06:33:19 PM PDT 24 |
105904123 ps |
| T948 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.361423703 |
|
|
Jul 14 06:33:30 PM PDT 24 |
Jul 14 06:33:34 PM PDT 24 |
747276134 ps |
| T115 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.4268683752 |
|
|
Jul 14 06:33:21 PM PDT 24 |
Jul 14 06:33:26 PM PDT 24 |
493845610 ps |
| T118 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3489291322 |
|
|
Jul 14 06:33:35 PM PDT 24 |
Jul 14 06:33:37 PM PDT 24 |
161856140 ps |
| T71 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1985345569 |
|
|
Jul 14 06:33:15 PM PDT 24 |
Jul 14 06:34:04 PM PDT 24 |
7384651379 ps |
| T105 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2289887642 |
|
|
Jul 14 06:33:16 PM PDT 24 |
Jul 14 06:33:18 PM PDT 24 |
19731884 ps |
| T949 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3028951072 |
|
|
Jul 14 06:33:20 PM PDT 24 |
Jul 14 06:33:25 PM PDT 24 |
927890839 ps |
| T72 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.79369863 |
|
|
Jul 14 06:33:43 PM PDT 24 |
Jul 14 06:34:13 PM PDT 24 |
7694236379 ps |
| T950 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3314622701 |
|
|
Jul 14 06:33:07 PM PDT 24 |
Jul 14 06:33:12 PM PDT 24 |
1479293658 ps |
| T73 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3799444639 |
|
|
Jul 14 06:33:43 PM PDT 24 |
Jul 14 06:34:10 PM PDT 24 |
7530765937 ps |
| T123 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3556555386 |
|
|
Jul 14 06:33:17 PM PDT 24 |
Jul 14 06:33:21 PM PDT 24 |
362147783 ps |
| T74 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2956084606 |
|
|
Jul 14 06:33:07 PM PDT 24 |
Jul 14 06:33:08 PM PDT 24 |
57225285 ps |
| T75 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2666672470 |
|
|
Jul 14 06:33:22 PM PDT 24 |
Jul 14 06:33:24 PM PDT 24 |
54441434 ps |
| T76 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.314401610 |
|
|
Jul 14 06:33:03 PM PDT 24 |
Jul 14 06:33:34 PM PDT 24 |
15388327874 ps |
| T951 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2705872180 |
|
|
Jul 14 06:33:08 PM PDT 24 |
Jul 14 06:33:12 PM PDT 24 |
179869603 ps |
| T952 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2377092917 |
|
|
Jul 14 06:33:08 PM PDT 24 |
Jul 14 06:33:15 PM PDT 24 |
369448851 ps |
| T114 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2954534907 |
|
|
Jul 14 06:33:45 PM PDT 24 |
Jul 14 06:33:49 PM PDT 24 |
713690803 ps |
| T119 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1639643002 |
|
|
Jul 14 06:33:29 PM PDT 24 |
Jul 14 06:33:32 PM PDT 24 |
188807762 ps |
| T953 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2285739535 |
|
|
Jul 14 06:33:08 PM PDT 24 |
Jul 14 06:33:14 PM PDT 24 |
289638087 ps |
| T954 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3090498185 |
|
|
Jul 14 06:33:11 PM PDT 24 |
Jul 14 06:33:41 PM PDT 24 |
3845204245 ps |
| T955 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.592807875 |
|
|
Jul 14 06:33:08 PM PDT 24 |
Jul 14 06:33:16 PM PDT 24 |
694439690 ps |
| T77 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2188710339 |
|
|
Jul 14 06:33:07 PM PDT 24 |
Jul 14 06:33:10 PM PDT 24 |
63652810 ps |
| T956 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2480694031 |
|
|
Jul 14 06:33:12 PM PDT 24 |
Jul 14 06:33:16 PM PDT 24 |
51901015 ps |
| T78 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2018094380 |
|
|
Jul 14 06:33:27 PM PDT 24 |
Jul 14 06:33:54 PM PDT 24 |
3835028401 ps |
| T79 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1224705726 |
|
|
Jul 14 06:33:38 PM PDT 24 |
Jul 14 06:34:04 PM PDT 24 |
8166842049 ps |
| T957 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3149620120 |
|
|
Jul 14 06:33:45 PM PDT 24 |
Jul 14 06:33:46 PM PDT 24 |
18856450 ps |
| T958 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1408352608 |
|
|
Jul 14 06:33:42 PM PDT 24 |
Jul 14 06:33:47 PM PDT 24 |
1368323032 ps |
| T959 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1647810822 |
|
|
Jul 14 06:33:02 PM PDT 24 |
Jul 14 06:33:05 PM PDT 24 |
17298690 ps |
| T960 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.96938110 |
|
|
Jul 14 06:33:35 PM PDT 24 |
Jul 14 06:33:36 PM PDT 24 |
58228865 ps |
| T961 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1534584354 |
|
|
Jul 14 06:33:20 PM PDT 24 |
Jul 14 06:33:23 PM PDT 24 |
92659624 ps |
| T962 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.658784651 |
|
|
Jul 14 06:33:03 PM PDT 24 |
Jul 14 06:33:09 PM PDT 24 |
340048404 ps |
| T963 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3850378351 |
|
|
Jul 14 06:33:03 PM PDT 24 |
Jul 14 06:33:06 PM PDT 24 |
28088227 ps |
| T964 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.338362561 |
|
|
Jul 14 06:33:29 PM PDT 24 |
Jul 14 06:33:32 PM PDT 24 |
52330402 ps |
| T965 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1394283098 |
|
|
Jul 14 06:33:17 PM PDT 24 |
Jul 14 06:33:22 PM PDT 24 |
349951193 ps |
| T966 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.937262885 |
|
|
Jul 14 06:33:16 PM PDT 24 |
Jul 14 06:33:23 PM PDT 24 |
1416751590 ps |
| T80 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.4009983112 |
|
|
Jul 14 06:33:43 PM PDT 24 |
Jul 14 06:33:45 PM PDT 24 |
89432766 ps |
| T121 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1426292892 |
|
|
Jul 14 06:33:29 PM PDT 24 |
Jul 14 06:33:32 PM PDT 24 |
322661070 ps |
| T967 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2885444027 |
|
|
Jul 14 06:33:10 PM PDT 24 |
Jul 14 06:33:14 PM PDT 24 |
27795865 ps |
| T968 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.417206744 |
|
|
Jul 14 06:33:23 PM PDT 24 |
Jul 14 06:33:28 PM PDT 24 |
912512111 ps |
| T969 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1358787647 |
|
|
Jul 14 06:33:08 PM PDT 24 |
Jul 14 06:33:12 PM PDT 24 |
68780210 ps |
| T970 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1643666343 |
|
|
Jul 14 06:33:42 PM PDT 24 |
Jul 14 06:33:43 PM PDT 24 |
75376446 ps |
| T971 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2405134576 |
|
|
Jul 14 06:33:14 PM PDT 24 |
Jul 14 06:33:19 PM PDT 24 |
128426296 ps |
| T972 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2892237654 |
|
|
Jul 14 06:33:11 PM PDT 24 |
Jul 14 06:33:14 PM PDT 24 |
23835980 ps |
| T973 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3380114933 |
|
|
Jul 14 06:33:20 PM PDT 24 |
Jul 14 06:33:22 PM PDT 24 |
55028748 ps |
| T974 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3780911833 |
|
|
Jul 14 06:33:07 PM PDT 24 |
Jul 14 06:33:09 PM PDT 24 |
42680947 ps |
| T975 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1907882731 |
|
|
Jul 14 06:33:16 PM PDT 24 |
Jul 14 06:33:20 PM PDT 24 |
33587490 ps |
| T976 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1759146504 |
|
|
Jul 14 06:33:09 PM PDT 24 |
Jul 14 06:33:13 PM PDT 24 |
32617299 ps |
| T977 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3580315834 |
|
|
Jul 14 06:33:15 PM PDT 24 |
Jul 14 06:33:17 PM PDT 24 |
19575134 ps |
| T978 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.4023975431 |
|
|
Jul 14 06:33:08 PM PDT 24 |
Jul 14 06:33:11 PM PDT 24 |
53606939 ps |
| T126 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1145795779 |
|
|
Jul 14 06:33:16 PM PDT 24 |
Jul 14 06:33:19 PM PDT 24 |
110836446 ps |
| T120 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2430860684 |
|
|
Jul 14 06:33:09 PM PDT 24 |
Jul 14 06:33:13 PM PDT 24 |
245263289 ps |
| T979 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.49484963 |
|
|
Jul 14 06:33:09 PM PDT 24 |
Jul 14 06:33:13 PM PDT 24 |
18707429 ps |
| T980 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.601483578 |
|
|
Jul 14 06:33:34 PM PDT 24 |
Jul 14 06:33:35 PM PDT 24 |
36898494 ps |
| T981 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1922187577 |
|
|
Jul 14 06:33:44 PM PDT 24 |
Jul 14 06:33:45 PM PDT 24 |
48191624 ps |
| T81 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2895302855 |
|
|
Jul 14 06:33:21 PM PDT 24 |
Jul 14 06:34:25 PM PDT 24 |
58729705066 ps |
| T89 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3061394524 |
|
|
Jul 14 06:33:30 PM PDT 24 |
Jul 14 06:34:38 PM PDT 24 |
117280298546 ps |
| T982 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1730075996 |
|
|
Jul 14 06:33:08 PM PDT 24 |
Jul 14 06:33:12 PM PDT 24 |
86203451 ps |
| T122 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3104291822 |
|
|
Jul 14 06:33:36 PM PDT 24 |
Jul 14 06:33:39 PM PDT 24 |
568649436 ps |
| T983 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1301652502 |
|
|
Jul 14 06:33:08 PM PDT 24 |
Jul 14 06:33:15 PM PDT 24 |
152173927 ps |
| T984 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.690294746 |
|
|
Jul 14 06:33:20 PM PDT 24 |
Jul 14 06:33:22 PM PDT 24 |
51303165 ps |
| T985 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3659813326 |
|
|
Jul 14 06:33:07 PM PDT 24 |
Jul 14 06:33:13 PM PDT 24 |
384985988 ps |
| T986 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1187410732 |
|
|
Jul 14 06:33:20 PM PDT 24 |
Jul 14 06:34:14 PM PDT 24 |
14408966337 ps |
| T987 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1046086487 |
|
|
Jul 14 06:33:42 PM PDT 24 |
Jul 14 06:33:46 PM PDT 24 |
363587633 ps |
| T90 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2792197177 |
|
|
Jul 14 06:33:02 PM PDT 24 |
Jul 14 06:33:30 PM PDT 24 |
3846792604 ps |
| T988 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2542170981 |
|
|
Jul 14 06:33:13 PM PDT 24 |
Jul 14 06:33:18 PM PDT 24 |
3813837988 ps |
| T989 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.789739491 |
|
|
Jul 14 06:33:06 PM PDT 24 |
Jul 14 06:33:11 PM PDT 24 |
371934703 ps |
| T127 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2159407468 |
|
|
Jul 14 06:33:43 PM PDT 24 |
Jul 14 06:33:46 PM PDT 24 |
365058307 ps |
| T990 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.952372490 |
|
|
Jul 14 06:33:43 PM PDT 24 |
Jul 14 06:33:49 PM PDT 24 |
130534052 ps |
| T991 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1432188406 |
|
|
Jul 14 06:33:29 PM PDT 24 |
Jul 14 06:33:30 PM PDT 24 |
18070925 ps |
| T992 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3764643689 |
|
|
Jul 14 06:33:19 PM PDT 24 |
Jul 14 06:33:22 PM PDT 24 |
255559186 ps |
| T993 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.81098850 |
|
|
Jul 14 06:33:20 PM PDT 24 |
Jul 14 06:33:22 PM PDT 24 |
30093068 ps |
| T994 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3530589814 |
|
|
Jul 14 06:33:19 PM PDT 24 |
Jul 14 06:33:21 PM PDT 24 |
43071992 ps |
| T995 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1815207588 |
|
|
Jul 14 06:33:30 PM PDT 24 |
Jul 14 06:33:31 PM PDT 24 |
16711347 ps |
| T996 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.801429826 |
|
|
Jul 14 06:33:44 PM PDT 24 |
Jul 14 06:33:48 PM PDT 24 |
1557263765 ps |
| T997 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2592546841 |
|
|
Jul 14 06:33:43 PM PDT 24 |
Jul 14 06:34:14 PM PDT 24 |
7530369255 ps |
| T998 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2591737543 |
|
|
Jul 14 06:33:44 PM PDT 24 |
Jul 14 06:33:48 PM PDT 24 |
1453636623 ps |
| T999 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.119524211 |
|
|
Jul 14 06:33:08 PM PDT 24 |
Jul 14 06:33:16 PM PDT 24 |
1413882991 ps |
| T1000 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3078544902 |
|
|
Jul 14 06:33:29 PM PDT 24 |
Jul 14 06:33:36 PM PDT 24 |
286383683 ps |
| T1001 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2368840293 |
|
|
Jul 14 06:33:16 PM PDT 24 |
Jul 14 06:33:19 PM PDT 24 |
158269141 ps |
| T1002 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3777015866 |
|
|
Jul 14 06:33:35 PM PDT 24 |
Jul 14 06:33:38 PM PDT 24 |
78773089 ps |
| T1003 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3651045704 |
|
|
Jul 14 06:33:16 PM PDT 24 |
Jul 14 06:33:46 PM PDT 24 |
14779566216 ps |
| T88 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2747412785 |
|
|
Jul 14 06:33:28 PM PDT 24 |
Jul 14 06:33:30 PM PDT 24 |
210475489 ps |
| T1004 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.4289035606 |
|
|
Jul 14 06:33:20 PM PDT 24 |
Jul 14 06:33:21 PM PDT 24 |
102925954 ps |
| T1005 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.634832102 |
|
|
Jul 14 06:33:20 PM PDT 24 |
Jul 14 06:33:25 PM PDT 24 |
223500755 ps |
| T1006 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.970284304 |
|
|
Jul 14 06:33:35 PM PDT 24 |
Jul 14 06:33:40 PM PDT 24 |
714311503 ps |