Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	364056886	1			T1	439594		T2	393212		T4	3616
instr_valid_dis	322502899	1			T1	439594		T2	393212		T4	3616
instr_en	29362401	1			T27	13420		T29	203772		T30	116026

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	12946280	1			T27	13420		T29	17856		T30	66098
sram_ifetch_valid_disable	316630302	1			T1	439594		T2	393212		T4	3616
sram_ifetch_enable	34480304	1			T27	11118		T29	112498		T30	43190

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	364056886	1			T1	439594		T2	393212		T4	3616
hw_debug_en_valid_off	320472256	1			T1	439594		T2	393212		T4	3616
hw_debug_en_on	29910254	1			T27	11118		T29	64174		T30	46908

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	316630302	1			T1	439594		T2	393212		T4	3616
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	301772347	1			T1	439594		T2	393212		T4	3616
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	11068937	1			T29	187138		T30	79112		T7	546284
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4553750	1			T27	13420		T29	17856		T30	11366
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	2275990	1			T29	17856		T30	11366		T24	55070
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1658886	1			T27	13420		T7	10850		T82	20000
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	6167554	1			T7	94476		T21	20000		T24	57106
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1707590	1			T21	20000		T24	20570		T145	15764
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1277038	1			T7	94476		T82	15094		T147	59850
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8862730	1			T29	18660		T30	33748		T7	401646
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3601244	1			T30	33748		T21	140248		T24	36804
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3770542	1			T29	18660		T7	401646		T24	1460

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	14260554	1			T29	16634		T30	36914		T7	191258
lc_exec_en	14879970	1			T27	11118		T29	45514		T30	13160
valid_exec_dis	319129702	1			T1	439594		T2	393212		T4	3616
invalid_exec_dis	47426584	1			T27	24538		T29	130354		T30	109288