Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	150830944	1			T1	200082		T2	196606		T4	1476
triple_byte_access	2896243	1			T1	3998		T4	60		T5	1945
halfword_access	4439825	1			T1	5974		T4	98		T5	2943
byte_access	6192189	1			T1	7788		T4	147		T5	3833
zero_access	1860396	1			T1	1955		T4	27		T5	955

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

82832022

1

T1

109697

T2

65536

T4

870

auto[1]

83387575

1

T1

110100

T2

131070

T4

938

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	75002376	1			T1	99811		T2	65536		T4	727
auto[0]	triple_byte_access	1384373	1			T1	2045		T4	25		T5	981
auto[0]	halfword_access	2171603	1			T1	3008		T4	44		T5	1483
auto[0]	byte_access	3170541	1			T1	3864		T4	64		T5	1902
auto[0]	zero_access	1103129	1			T1	969		T4	10		T5	489
auto[1]	word_access	75828568	1			T1	100271		T2	131070		T4	749
auto[1]	triple_byte_access	1511870	1			T1	1953		T4	35		T5	964
auto[1]	halfword_access	2268222	1			T1	2966		T4	54		T5	1460
auto[1]	byte_access	3021648	1			T1	3924		T4	83		T5	1931
auto[1]	zero_access	757267	1			T1	986		T4	17		T5	466