Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

---

Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	335777458	1			T1	144179		T2	2876		T3	246922
instr_valid_dis	293420288	1			T1	144179		T2	2876		T3	55462
instr_en	30396691	1			T3	77652		T26	278878		T129	155628

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	24729052	1			T3	79012		T26	98982		T22	58364
sram_ifetch_valid_disable	286688838	1			T1	144179		T2	2876		T3	76792
sram_ifetch_enable	24359568	1			T3	91118		T26	119238		T21	56350

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	335777458	1			T1	144179		T2	2876		T3	246922
hw_debug_en_valid_off	286500466	1			T1	144179		T2	2876		T3	112072
hw_debug_en_on	28034550	1			T3	67336		T26	101484		T21	16624

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	286688838	1			T1	144179		T2	2876		T3	76792
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	270769068	1			T1	144179		T2	2876		T3	17314
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9630025	1			T3	25150		T26	60658		T129	66338
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	8878284	1			T3	41562		T26	32696		T22	30164
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	2071540	1			T3	38148		T22	30164		T129	20000
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	6149260	1			T3	3414		T26	32696		T129	13026
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	5013374	1			T26	5360		T22	28200		T129	39528
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1886964	1			T22	28200		T24	12862		T102	3738
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	2197606	1			T26	5360		T129	39528		T102	9872
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	13045884	1			T3	18248		T26	60658		T22	85284
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	4671480	1			T3	17314		T22	85284		T63	22256
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	4126292	1			T3	934		T26	60658		T129	59450

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	8494898	1			T3	49088		T26	119238		T129	36736
lc_exec_en	9975292	1			T3	49088		T26	35466		T21	16624
valid_exec_dis	280530304	1			T1	144179		T2	2876		T3	58544
invalid_exec_dis	49088620	1			T3	170130		T26	218220		T21	56350