Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	137502331	1			T1	720896		T2	404		T3	50888
triple_byte_access	2783366	1			T2	9		T3	1033		T4	15
halfword_access	4268289	1			T2	17		T3	1520		T4	23
byte_access	5964475	1			T2	26		T3	2057		T4	41
zero_access	1801818	1			T2	4		T3	517		T4	3

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

75891133

1

T1

360448

T2

239

T3

31310

auto[1]

76429146

1

T1

360448

T2

221

T3

24705

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	68340918	1			T1	360448		T2	206		T3	28482
auto[0]	triple_byte_access	1329328	1			T2	8		T3	572		T4	5
auto[0]	halfword_access	2087988	1			T2	9		T3	846		T4	8
auto[0]	byte_access	3058422	1			T2	14		T3	1125		T4	19
auto[0]	zero_access	1074477	1			T2	2		T3	285		T4	2
auto[1]	word_access	69161413	1			T1	360448		T2	198		T3	22406
auto[1]	triple_byte_access	1454038	1			T2	1		T3	461		T4	10
auto[1]	halfword_access	2180301	1			T2	8		T3	674		T4	15
auto[1]	byte_access	2906053	1			T2	12		T3	932		T4	22
auto[1]	zero_access	727341	1			T2	2		T3	232		T4	1