| T793 |
/workspace/coverage/default/43.sram_ctrl_mem_walk.1734249827 |
|
|
Jul 16 07:32:18 PM PDT 24 |
Jul 16 07:36:47 PM PDT 24 |
3986423352 ps |
| T794 |
/workspace/coverage/default/10.sram_ctrl_alert_test.2566141051 |
|
|
Jul 16 07:28:19 PM PDT 24 |
Jul 16 07:28:34 PM PDT 24 |
33378867 ps |
| T795 |
/workspace/coverage/default/41.sram_ctrl_mem_partial_access.256689653 |
|
|
Jul 16 07:32:10 PM PDT 24 |
Jul 16 07:33:52 PM PDT 24 |
9756498358 ps |
| T796 |
/workspace/coverage/default/27.sram_ctrl_alert_test.2556904105 |
|
|
Jul 16 07:29:56 PM PDT 24 |
Jul 16 07:30:00 PM PDT 24 |
23604111 ps |
| T797 |
/workspace/coverage/default/23.sram_ctrl_stress_all.1859931835 |
|
|
Jul 16 07:29:10 PM PDT 24 |
Jul 16 08:42:39 PM PDT 24 |
63962412961 ps |
| T798 |
/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.1656289986 |
|
|
Jul 16 07:28:59 PM PDT 24 |
Jul 16 07:31:48 PM PDT 24 |
1902768165 ps |
| T799 |
/workspace/coverage/default/37.sram_ctrl_stress_pipeline.134182534 |
|
|
Jul 16 07:31:31 PM PDT 24 |
Jul 16 07:37:05 PM PDT 24 |
9064984732 ps |
| T800 |
/workspace/coverage/default/47.sram_ctrl_mem_walk.2030731161 |
|
|
Jul 16 07:32:51 PM PDT 24 |
Jul 16 07:35:50 PM PDT 24 |
7518717246 ps |
| T801 |
/workspace/coverage/default/42.sram_ctrl_ram_cfg.3597801994 |
|
|
Jul 16 07:32:04 PM PDT 24 |
Jul 16 07:32:26 PM PDT 24 |
379390120 ps |
| T802 |
/workspace/coverage/default/36.sram_ctrl_executable.84275915 |
|
|
Jul 16 07:31:30 PM PDT 24 |
Jul 16 07:42:16 PM PDT 24 |
26330299124 ps |
| T803 |
/workspace/coverage/default/40.sram_ctrl_regwen.466168706 |
|
|
Jul 16 07:31:51 PM PDT 24 |
Jul 16 07:35:35 PM PDT 24 |
10750352913 ps |
| T804 |
/workspace/coverage/default/4.sram_ctrl_max_throughput.207216728 |
|
|
Jul 16 07:28:09 PM PDT 24 |
Jul 16 07:30:16 PM PDT 24 |
801340698 ps |
| T805 |
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.1515374438 |
|
|
Jul 16 07:33:28 PM PDT 24 |
Jul 16 07:34:00 PM PDT 24 |
689096485 ps |
| T806 |
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.1039636342 |
|
|
Jul 16 07:32:23 PM PDT 24 |
Jul 16 07:34:11 PM PDT 24 |
11741666782 ps |
| T807 |
/workspace/coverage/default/6.sram_ctrl_regwen.3850293654 |
|
|
Jul 16 07:28:08 PM PDT 24 |
Jul 16 07:29:37 PM PDT 24 |
978287472 ps |
| T808 |
/workspace/coverage/default/32.sram_ctrl_partial_access.4031208666 |
|
|
Jul 16 07:30:27 PM PDT 24 |
Jul 16 07:30:37 PM PDT 24 |
5074715654 ps |
| T809 |
/workspace/coverage/default/33.sram_ctrl_lc_escalation.3425790912 |
|
|
Jul 16 07:30:41 PM PDT 24 |
Jul 16 07:31:53 PM PDT 24 |
107267393463 ps |
| T810 |
/workspace/coverage/default/48.sram_ctrl_lc_escalation.2638277534 |
|
|
Jul 16 07:33:10 PM PDT 24 |
Jul 16 07:34:04 PM PDT 24 |
9256400508 ps |
| T811 |
/workspace/coverage/default/22.sram_ctrl_regwen.2476055168 |
|
|
Jul 16 07:29:01 PM PDT 24 |
Jul 16 07:41:23 PM PDT 24 |
22457395762 ps |
| T812 |
/workspace/coverage/default/36.sram_ctrl_smoke.276922255 |
|
|
Jul 16 07:31:28 PM PDT 24 |
Jul 16 07:32:44 PM PDT 24 |
4696918716 ps |
| T813 |
/workspace/coverage/default/15.sram_ctrl_max_throughput.3406846207 |
|
|
Jul 16 07:28:41 PM PDT 24 |
Jul 16 07:31:10 PM PDT 24 |
1566099028 ps |
| T814 |
/workspace/coverage/default/7.sram_ctrl_regwen.982458241 |
|
|
Jul 16 07:28:12 PM PDT 24 |
Jul 16 07:52:56 PM PDT 24 |
53840371829 ps |
| T815 |
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.1932998042 |
|
|
Jul 16 07:33:17 PM PDT 24 |
Jul 16 07:40:41 PM PDT 24 |
21024230035 ps |
| T816 |
/workspace/coverage/default/49.sram_ctrl_lc_escalation.1284589144 |
|
|
Jul 16 07:33:29 PM PDT 24 |
Jul 16 07:34:51 PM PDT 24 |
35643243410 ps |
| T817 |
/workspace/coverage/default/29.sram_ctrl_access_during_key_req.2504621016 |
|
|
Jul 16 07:30:13 PM PDT 24 |
Jul 16 07:47:24 PM PDT 24 |
13257856300 ps |
| T818 |
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.4202135711 |
|
|
Jul 16 07:32:54 PM PDT 24 |
Jul 16 07:33:41 PM PDT 24 |
3908858035 ps |
| T819 |
/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.2323194193 |
|
|
Jul 16 07:28:39 PM PDT 24 |
Jul 16 07:34:13 PM PDT 24 |
25857204253 ps |
| T820 |
/workspace/coverage/default/31.sram_ctrl_regwen.3409028516 |
|
|
Jul 16 07:30:26 PM PDT 24 |
Jul 16 07:48:59 PM PDT 24 |
12559953807 ps |
| T821 |
/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.3338747073 |
|
|
Jul 16 07:28:56 PM PDT 24 |
Jul 16 07:34:18 PM PDT 24 |
14218163188 ps |
| T822 |
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.337435664 |
|
|
Jul 16 07:32:04 PM PDT 24 |
Jul 16 07:37:27 PM PDT 24 |
13167073533 ps |
| T823 |
/workspace/coverage/default/34.sram_ctrl_alert_test.1750016380 |
|
|
Jul 16 07:31:01 PM PDT 24 |
Jul 16 07:31:06 PM PDT 24 |
20501824 ps |
| T824 |
/workspace/coverage/default/1.sram_ctrl_ram_cfg.3259143972 |
|
|
Jul 16 07:27:53 PM PDT 24 |
Jul 16 07:28:12 PM PDT 24 |
3339095376 ps |
| T825 |
/workspace/coverage/default/38.sram_ctrl_mem_partial_access.1245828018 |
|
|
Jul 16 07:31:52 PM PDT 24 |
Jul 16 07:34:08 PM PDT 24 |
1620385081 ps |
| T826 |
/workspace/coverage/default/16.sram_ctrl_regwen.3290673108 |
|
|
Jul 16 07:28:50 PM PDT 24 |
Jul 16 07:41:07 PM PDT 24 |
11171864453 ps |
| T827 |
/workspace/coverage/default/47.sram_ctrl_bijection.398787785 |
|
|
Jul 16 07:32:50 PM PDT 24 |
Jul 16 08:11:30 PM PDT 24 |
967339780068 ps |
| T828 |
/workspace/coverage/default/33.sram_ctrl_smoke.1786638170 |
|
|
Jul 16 07:30:29 PM PDT 24 |
Jul 16 07:30:39 PM PDT 24 |
415348995 ps |
| T829 |
/workspace/coverage/default/13.sram_ctrl_access_during_key_req.344637534 |
|
|
Jul 16 07:28:40 PM PDT 24 |
Jul 16 07:35:28 PM PDT 24 |
17587718222 ps |
| T830 |
/workspace/coverage/default/41.sram_ctrl_smoke.3899389923 |
|
|
Jul 16 07:31:56 PM PDT 24 |
Jul 16 07:34:23 PM PDT 24 |
1298731586 ps |
| T831 |
/workspace/coverage/default/6.sram_ctrl_max_throughput.4068671457 |
|
|
Jul 16 07:28:09 PM PDT 24 |
Jul 16 07:30:17 PM PDT 24 |
12698589737 ps |
| T832 |
/workspace/coverage/default/4.sram_ctrl_lc_escalation.4229579172 |
|
|
Jul 16 07:28:07 PM PDT 24 |
Jul 16 07:29:54 PM PDT 24 |
28508754301 ps |
| T833 |
/workspace/coverage/default/48.sram_ctrl_ram_cfg.1836674538 |
|
|
Jul 16 07:33:11 PM PDT 24 |
Jul 16 07:33:40 PM PDT 24 |
358329003 ps |
| T834 |
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.2691787896 |
|
|
Jul 16 07:28:13 PM PDT 24 |
Jul 16 07:29:48 PM PDT 24 |
2812825116 ps |
| T835 |
/workspace/coverage/default/21.sram_ctrl_stress_all.3573562049 |
|
|
Jul 16 07:29:05 PM PDT 24 |
Jul 16 08:15:52 PM PDT 24 |
112577444105 ps |
| T836 |
/workspace/coverage/default/30.sram_ctrl_mem_walk.298299747 |
|
|
Jul 16 07:30:14 PM PDT 24 |
Jul 16 07:36:37 PM PDT 24 |
86241093197 ps |
| T837 |
/workspace/coverage/default/41.sram_ctrl_stress_all.2891302800 |
|
|
Jul 16 07:32:00 PM PDT 24 |
Jul 16 09:55:11 PM PDT 24 |
244729593969 ps |
| T838 |
/workspace/coverage/default/35.sram_ctrl_stress_pipeline.4198038685 |
|
|
Jul 16 07:30:58 PM PDT 24 |
Jul 16 07:34:44 PM PDT 24 |
6377663403 ps |
| T839 |
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.1144586851 |
|
|
Jul 16 07:28:09 PM PDT 24 |
Jul 16 07:29:34 PM PDT 24 |
5354155738 ps |
| T840 |
/workspace/coverage/default/46.sram_ctrl_smoke.4194365021 |
|
|
Jul 16 07:32:37 PM PDT 24 |
Jul 16 07:33:46 PM PDT 24 |
777534460 ps |
| T841 |
/workspace/coverage/default/15.sram_ctrl_lc_escalation.911860467 |
|
|
Jul 16 07:28:39 PM PDT 24 |
Jul 16 07:29:58 PM PDT 24 |
21830821299 ps |
| T842 |
/workspace/coverage/default/15.sram_ctrl_alert_test.64408901 |
|
|
Jul 16 07:28:52 PM PDT 24 |
Jul 16 07:29:04 PM PDT 24 |
12441301 ps |
| T843 |
/workspace/coverage/default/19.sram_ctrl_bijection.3915542114 |
|
|
Jul 16 07:28:54 PM PDT 24 |
Jul 16 07:53:46 PM PDT 24 |
499788947881 ps |
| T844 |
/workspace/coverage/default/49.sram_ctrl_max_throughput.3846252003 |
|
|
Jul 16 07:33:28 PM PDT 24 |
Jul 16 07:36:13 PM PDT 24 |
3192664369 ps |
| T845 |
/workspace/coverage/default/22.sram_ctrl_stress_pipeline.2550327970 |
|
|
Jul 16 07:29:01 PM PDT 24 |
Jul 16 07:32:36 PM PDT 24 |
7537593617 ps |
| T846 |
/workspace/coverage/default/41.sram_ctrl_multiple_keys.377724776 |
|
|
Jul 16 07:31:50 PM PDT 24 |
Jul 16 07:49:09 PM PDT 24 |
48856639590 ps |
| T847 |
/workspace/coverage/default/16.sram_ctrl_partial_access.1620244883 |
|
|
Jul 16 07:28:57 PM PDT 24 |
Jul 16 07:30:19 PM PDT 24 |
1750174569 ps |
| T848 |
/workspace/coverage/default/31.sram_ctrl_bijection.2054745402 |
|
|
Jul 16 07:30:12 PM PDT 24 |
Jul 16 07:53:04 PM PDT 24 |
21181787719 ps |
| T849 |
/workspace/coverage/default/36.sram_ctrl_lc_escalation.460060840 |
|
|
Jul 16 07:31:31 PM PDT 24 |
Jul 16 07:32:01 PM PDT 24 |
3898208821 ps |
| T850 |
/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.3684471306 |
|
|
Jul 16 07:31:55 PM PDT 24 |
Jul 16 07:34:31 PM PDT 24 |
3128885252 ps |
| T851 |
/workspace/coverage/default/3.sram_ctrl_stress_pipeline.1264151938 |
|
|
Jul 16 07:27:55 PM PDT 24 |
Jul 16 07:32:05 PM PDT 24 |
4598928530 ps |
| T852 |
/workspace/coverage/default/35.sram_ctrl_multiple_keys.1554741016 |
|
|
Jul 16 07:31:00 PM PDT 24 |
Jul 16 07:32:41 PM PDT 24 |
3422652451 ps |
| T853 |
/workspace/coverage/default/12.sram_ctrl_lc_escalation.2915067278 |
|
|
Jul 16 07:28:40 PM PDT 24 |
Jul 16 07:29:22 PM PDT 24 |
6474323177 ps |
| T854 |
/workspace/coverage/default/15.sram_ctrl_stress_pipeline.1388670557 |
|
|
Jul 16 07:28:40 PM PDT 24 |
Jul 16 07:35:16 PM PDT 24 |
6663861938 ps |
| T855 |
/workspace/coverage/default/21.sram_ctrl_ram_cfg.4192286903 |
|
|
Jul 16 07:29:08 PM PDT 24 |
Jul 16 07:29:22 PM PDT 24 |
753128090 ps |
| T856 |
/workspace/coverage/default/32.sram_ctrl_regwen.3572027375 |
|
|
Jul 16 07:30:30 PM PDT 24 |
Jul 16 07:36:04 PM PDT 24 |
3417422088 ps |
| T857 |
/workspace/coverage/default/40.sram_ctrl_alert_test.160373883 |
|
|
Jul 16 07:31:55 PM PDT 24 |
Jul 16 07:32:10 PM PDT 24 |
38564876 ps |
| T858 |
/workspace/coverage/default/27.sram_ctrl_executable.357286831 |
|
|
Jul 16 07:29:54 PM PDT 24 |
Jul 16 07:57:48 PM PDT 24 |
71932866685 ps |
| T859 |
/workspace/coverage/default/18.sram_ctrl_mem_walk.3174884838 |
|
|
Jul 16 07:28:58 PM PDT 24 |
Jul 16 07:32:17 PM PDT 24 |
39005196845 ps |
| T860 |
/workspace/coverage/default/2.sram_ctrl_partial_access_b2b.2104915786 |
|
|
Jul 16 07:27:54 PM PDT 24 |
Jul 16 07:34:34 PM PDT 24 |
17682578256 ps |
| T861 |
/workspace/coverage/default/21.sram_ctrl_max_throughput.912035219 |
|
|
Jul 16 07:28:56 PM PDT 24 |
Jul 16 07:29:17 PM PDT 24 |
2722332874 ps |
| T862 |
/workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.23666005 |
|
|
Jul 16 07:29:01 PM PDT 24 |
Jul 16 07:30:40 PM PDT 24 |
6761000287 ps |
| T863 |
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.2119704729 |
|
|
Jul 16 07:28:03 PM PDT 24 |
Jul 16 07:29:06 PM PDT 24 |
794949285 ps |
| T864 |
/workspace/coverage/default/34.sram_ctrl_smoke.2193586934 |
|
|
Jul 16 07:30:42 PM PDT 24 |
Jul 16 07:30:59 PM PDT 24 |
1650031052 ps |
| T865 |
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.759855884 |
|
|
Jul 16 07:28:06 PM PDT 24 |
Jul 16 07:29:06 PM PDT 24 |
2287445935 ps |
| T866 |
/workspace/coverage/default/45.sram_ctrl_executable.2877999998 |
|
|
Jul 16 07:32:36 PM PDT 24 |
Jul 16 07:42:37 PM PDT 24 |
10582697098 ps |
| T867 |
/workspace/coverage/default/11.sram_ctrl_executable.140903158 |
|
|
Jul 16 07:28:21 PM PDT 24 |
Jul 16 07:31:43 PM PDT 24 |
24349509423 ps |
| T84 |
/workspace/coverage/default/23.sram_ctrl_mem_partial_access.2305687909 |
|
|
Jul 16 07:29:09 PM PDT 24 |
Jul 16 07:31:41 PM PDT 24 |
2447433651 ps |
| T868 |
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.3044738138 |
|
|
Jul 16 07:33:10 PM PDT 24 |
Jul 16 07:34:08 PM PDT 24 |
1402970200 ps |
| T869 |
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1510958585 |
|
|
Jul 16 07:32:22 PM PDT 24 |
Jul 16 07:37:52 PM PDT 24 |
12309530694 ps |
| T870 |
/workspace/coverage/default/37.sram_ctrl_mem_walk.1785803108 |
|
|
Jul 16 07:31:30 PM PDT 24 |
Jul 16 07:34:35 PM PDT 24 |
35909467944 ps |
| T871 |
/workspace/coverage/default/43.sram_ctrl_max_throughput.1573914117 |
|
|
Jul 16 07:32:18 PM PDT 24 |
Jul 16 07:32:56 PM PDT 24 |
731852852 ps |
| T872 |
/workspace/coverage/default/3.sram_ctrl_multiple_keys.4206182302 |
|
|
Jul 16 07:27:53 PM PDT 24 |
Jul 16 07:47:35 PM PDT 24 |
18499926502 ps |
| T873 |
/workspace/coverage/default/38.sram_ctrl_access_during_key_req.612264841 |
|
|
Jul 16 07:31:34 PM PDT 24 |
Jul 16 07:34:16 PM PDT 24 |
13154736740 ps |
| T874 |
/workspace/coverage/default/48.sram_ctrl_executable.1846193345 |
|
|
Jul 16 07:33:10 PM PDT 24 |
Jul 16 07:58:59 PM PDT 24 |
25893089998 ps |
| T875 |
/workspace/coverage/default/20.sram_ctrl_max_throughput.1052981119 |
|
|
Jul 16 07:28:59 PM PDT 24 |
Jul 16 07:31:50 PM PDT 24 |
801715638 ps |
| T876 |
/workspace/coverage/default/2.sram_ctrl_smoke.2409969818 |
|
|
Jul 16 07:27:54 PM PDT 24 |
Jul 16 07:30:23 PM PDT 24 |
815625560 ps |
| T877 |
/workspace/coverage/default/22.sram_ctrl_mem_walk.2111293897 |
|
|
Jul 16 07:28:57 PM PDT 24 |
Jul 16 07:34:33 PM PDT 24 |
14455799356 ps |
| T878 |
/workspace/coverage/default/2.sram_ctrl_access_during_key_req.2136197833 |
|
|
Jul 16 07:27:55 PM PDT 24 |
Jul 16 07:36:17 PM PDT 24 |
14612775304 ps |
| T879 |
/workspace/coverage/default/23.sram_ctrl_lc_escalation.3525469186 |
|
|
Jul 16 07:29:10 PM PDT 24 |
Jul 16 07:30:28 PM PDT 24 |
14289214203 ps |
| T880 |
/workspace/coverage/default/34.sram_ctrl_bijection.3070691912 |
|
|
Jul 16 07:30:42 PM PDT 24 |
Jul 16 08:17:54 PM PDT 24 |
179776415363 ps |
| T881 |
/workspace/coverage/default/3.sram_ctrl_access_during_key_req.3594419362 |
|
|
Jul 16 07:27:58 PM PDT 24 |
Jul 16 07:40:06 PM PDT 24 |
70837868562 ps |
| T31 |
/workspace/coverage/default/4.sram_ctrl_sec_cm.2785511551 |
|
|
Jul 16 07:28:05 PM PDT 24 |
Jul 16 07:28:20 PM PDT 24 |
171662942 ps |
| T882 |
/workspace/coverage/default/0.sram_ctrl_ram_cfg.1913732849 |
|
|
Jul 16 07:27:55 PM PDT 24 |
Jul 16 07:28:12 PM PDT 24 |
381885502 ps |
| T883 |
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.3870209773 |
|
|
Jul 16 07:28:19 PM PDT 24 |
Jul 16 07:28:46 PM PDT 24 |
720955211 ps |
| T884 |
/workspace/coverage/default/46.sram_ctrl_mem_walk.3901365485 |
|
|
Jul 16 07:32:51 PM PDT 24 |
Jul 16 07:36:10 PM PDT 24 |
9401040635 ps |
| T885 |
/workspace/coverage/default/14.sram_ctrl_mem_walk.3290411584 |
|
|
Jul 16 07:28:40 PM PDT 24 |
Jul 16 07:34:17 PM PDT 24 |
21624824016 ps |
| T886 |
/workspace/coverage/default/44.sram_ctrl_alert_test.1422696644 |
|
|
Jul 16 07:32:19 PM PDT 24 |
Jul 16 07:32:45 PM PDT 24 |
18498926 ps |
| T887 |
/workspace/coverage/default/32.sram_ctrl_access_during_key_req.3686947532 |
|
|
Jul 16 07:30:29 PM PDT 24 |
Jul 16 07:37:06 PM PDT 24 |
103006677730 ps |
| T888 |
/workspace/coverage/default/13.sram_ctrl_mem_walk.797279344 |
|
|
Jul 16 07:28:43 PM PDT 24 |
Jul 16 07:31:56 PM PDT 24 |
37486110117 ps |
| T889 |
/workspace/coverage/default/39.sram_ctrl_partial_access_b2b.3274639606 |
|
|
Jul 16 07:31:54 PM PDT 24 |
Jul 16 07:42:06 PM PDT 24 |
93221286850 ps |
| T890 |
/workspace/coverage/default/20.sram_ctrl_executable.1551152474 |
|
|
Jul 16 07:29:00 PM PDT 24 |
Jul 16 07:31:01 PM PDT 24 |
4390115936 ps |
| T891 |
/workspace/coverage/default/37.sram_ctrl_max_throughput.196027549 |
|
|
Jul 16 07:31:30 PM PDT 24 |
Jul 16 07:32:44 PM PDT 24 |
783539630 ps |
| T892 |
/workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.891223598 |
|
|
Jul 16 07:29:16 PM PDT 24 |
Jul 16 07:29:29 PM PDT 24 |
275709038 ps |
| T893 |
/workspace/coverage/default/19.sram_ctrl_ram_cfg.2531092901 |
|
|
Jul 16 07:28:56 PM PDT 24 |
Jul 16 07:29:12 PM PDT 24 |
1056836747 ps |
| T894 |
/workspace/coverage/default/3.sram_ctrl_stress_all.1744241571 |
|
|
Jul 16 07:27:57 PM PDT 24 |
Jul 16 07:52:25 PM PDT 24 |
130257027421 ps |
| T895 |
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.832931563 |
|
|
Jul 16 07:28:07 PM PDT 24 |
Jul 16 07:29:36 PM PDT 24 |
2724740767 ps |
| T896 |
/workspace/coverage/default/5.sram_ctrl_executable.233163071 |
|
|
Jul 16 07:28:07 PM PDT 24 |
Jul 16 07:43:46 PM PDT 24 |
29274995215 ps |
| T897 |
/workspace/coverage/default/13.sram_ctrl_mem_partial_access.3013953929 |
|
|
Jul 16 07:28:43 PM PDT 24 |
Jul 16 07:30:15 PM PDT 24 |
2694946578 ps |
| T898 |
/workspace/coverage/default/19.sram_ctrl_mem_walk.1631596823 |
|
|
Jul 16 07:28:56 PM PDT 24 |
Jul 16 07:31:40 PM PDT 24 |
10522771531 ps |
| T899 |
/workspace/coverage/default/31.sram_ctrl_mem_partial_access.4186039453 |
|
|
Jul 16 07:30:27 PM PDT 24 |
Jul 16 07:31:56 PM PDT 24 |
12178643210 ps |
| T900 |
/workspace/coverage/default/3.sram_ctrl_mem_partial_access.893504783 |
|
|
Jul 16 07:27:57 PM PDT 24 |
Jul 16 07:30:17 PM PDT 24 |
6327030223 ps |
| T901 |
/workspace/coverage/default/20.sram_ctrl_multiple_keys.38583395 |
|
|
Jul 16 07:29:00 PM PDT 24 |
Jul 16 07:42:36 PM PDT 24 |
6902005476 ps |
| T902 |
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.2898875756 |
|
|
Jul 16 07:32:39 PM PDT 24 |
Jul 16 07:33:18 PM PDT 24 |
975273541 ps |
| T903 |
/workspace/coverage/default/34.sram_ctrl_access_during_key_req.3346875552 |
|
|
Jul 16 07:30:42 PM PDT 24 |
Jul 16 07:47:29 PM PDT 24 |
11773671522 ps |
| T904 |
/workspace/coverage/default/39.sram_ctrl_multiple_keys.643722133 |
|
|
Jul 16 07:31:49 PM PDT 24 |
Jul 16 07:46:25 PM PDT 24 |
4772269671 ps |
| T905 |
/workspace/coverage/default/40.sram_ctrl_bijection.2695977151 |
|
|
Jul 16 07:31:50 PM PDT 24 |
Jul 16 08:03:52 PM PDT 24 |
54198562812 ps |
| T906 |
/workspace/coverage/default/41.sram_ctrl_executable.3855412915 |
|
|
Jul 16 07:31:57 PM PDT 24 |
Jul 16 07:41:36 PM PDT 24 |
9818690235 ps |
| T907 |
/workspace/coverage/default/26.sram_ctrl_stress_pipeline.335643762 |
|
|
Jul 16 07:29:34 PM PDT 24 |
Jul 16 07:32:51 PM PDT 24 |
5437123971 ps |
| T908 |
/workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.2095313305 |
|
|
Jul 16 07:28:59 PM PDT 24 |
Jul 16 07:29:21 PM PDT 24 |
1370696962 ps |
| T909 |
/workspace/coverage/default/23.sram_ctrl_stress_pipeline.1536253167 |
|
|
Jul 16 07:29:10 PM PDT 24 |
Jul 16 07:32:15 PM PDT 24 |
3320609441 ps |
| T910 |
/workspace/coverage/default/42.sram_ctrl_lc_escalation.2077541955 |
|
|
Jul 16 07:31:59 PM PDT 24 |
Jul 16 07:32:37 PM PDT 24 |
6083111584 ps |
| T911 |
/workspace/coverage/default/4.sram_ctrl_partial_access_b2b.1071491883 |
|
|
Jul 16 07:28:03 PM PDT 24 |
Jul 16 07:35:23 PM PDT 24 |
22659373346 ps |
| T912 |
/workspace/coverage/default/18.sram_ctrl_stress_all.4280221911 |
|
|
Jul 16 07:28:51 PM PDT 24 |
Jul 16 09:00:50 PM PDT 24 |
226814575461 ps |
| T913 |
/workspace/coverage/default/24.sram_ctrl_lc_escalation.570089831 |
|
|
Jul 16 07:29:21 PM PDT 24 |
Jul 16 07:30:28 PM PDT 24 |
45353819292 ps |
| T914 |
/workspace/coverage/default/20.sram_ctrl_ram_cfg.1127885873 |
|
|
Jul 16 07:28:57 PM PDT 24 |
Jul 16 07:29:13 PM PDT 24 |
3045603970 ps |
| T915 |
/workspace/coverage/default/33.sram_ctrl_partial_access_b2b.2200081549 |
|
|
Jul 16 07:30:42 PM PDT 24 |
Jul 16 07:34:28 PM PDT 24 |
5910830500 ps |
| T916 |
/workspace/coverage/default/15.sram_ctrl_ram_cfg.773524512 |
|
|
Jul 16 07:28:51 PM PDT 24 |
Jul 16 07:29:04 PM PDT 24 |
2412435241 ps |
| T917 |
/workspace/coverage/default/11.sram_ctrl_smoke.321839642 |
|
|
Jul 16 07:28:18 PM PDT 24 |
Jul 16 07:30:30 PM PDT 24 |
3115083658 ps |
| T918 |
/workspace/coverage/default/32.sram_ctrl_alert_test.2272241588 |
|
|
Jul 16 07:30:32 PM PDT 24 |
Jul 16 07:30:37 PM PDT 24 |
34015289 ps |
| T919 |
/workspace/coverage/default/43.sram_ctrl_partial_access.102315721 |
|
|
Jul 16 07:32:02 PM PDT 24 |
Jul 16 07:33:36 PM PDT 24 |
1574249329 ps |
| T920 |
/workspace/coverage/default/28.sram_ctrl_mem_partial_access.3251453009 |
|
|
Jul 16 07:30:11 PM PDT 24 |
Jul 16 07:31:42 PM PDT 24 |
2625152976 ps |
| T921 |
/workspace/coverage/default/6.sram_ctrl_multiple_keys.1149625114 |
|
|
Jul 16 07:28:06 PM PDT 24 |
Jul 16 07:50:30 PM PDT 24 |
68739318617 ps |
| T922 |
/workspace/coverage/default/7.sram_ctrl_mem_walk.4048374554 |
|
|
Jul 16 07:28:11 PM PDT 24 |
Jul 16 07:32:28 PM PDT 24 |
7879518875 ps |
| T923 |
/workspace/coverage/default/23.sram_ctrl_partial_access.2192175889 |
|
|
Jul 16 07:29:09 PM PDT 24 |
Jul 16 07:29:24 PM PDT 24 |
363529625 ps |
| T924 |
/workspace/coverage/default/49.sram_ctrl_partial_access.4022563606 |
|
|
Jul 16 07:33:10 PM PDT 24 |
Jul 16 07:35:10 PM PDT 24 |
1033293737 ps |
| T925 |
/workspace/coverage/default/29.sram_ctrl_executable.1725689639 |
|
|
Jul 16 07:30:11 PM PDT 24 |
Jul 16 07:39:02 PM PDT 24 |
36190475401 ps |
| T926 |
/workspace/coverage/default/8.sram_ctrl_stress_all.3515384509 |
|
|
Jul 16 07:28:16 PM PDT 24 |
Jul 16 08:03:11 PM PDT 24 |
613470731017 ps |
| T927 |
/workspace/coverage/default/38.sram_ctrl_max_throughput.911176885 |
|
|
Jul 16 07:31:30 PM PDT 24 |
Jul 16 07:31:51 PM PDT 24 |
1453822313 ps |
| T928 |
/workspace/coverage/default/12.sram_ctrl_mem_walk.2815931712 |
|
|
Jul 16 07:28:42 PM PDT 24 |
Jul 16 07:31:22 PM PDT 24 |
2636915519 ps |
| T929 |
/workspace/coverage/default/30.sram_ctrl_stress_all.1257461120 |
|
|
Jul 16 07:30:14 PM PDT 24 |
Jul 16 08:14:21 PM PDT 24 |
58224936660 ps |
| T930 |
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.527699027 |
|
|
Jul 16 07:32:00 PM PDT 24 |
Jul 16 07:32:35 PM PDT 24 |
3217292783 ps |
| T931 |
/workspace/coverage/default/23.sram_ctrl_bijection.3803367843 |
|
|
Jul 16 07:29:10 PM PDT 24 |
Jul 16 08:14:27 PM PDT 24 |
172652100999 ps |
| T932 |
/workspace/coverage/default/32.sram_ctrl_mem_partial_access.3945429175 |
|
|
Jul 16 07:30:29 PM PDT 24 |
Jul 16 07:33:08 PM PDT 24 |
19049379819 ps |
| T933 |
/workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.3221059050 |
|
|
Jul 16 07:31:01 PM PDT 24 |
Jul 16 07:33:33 PM PDT 24 |
1558299395 ps |
| T934 |
/workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.3681890167 |
|
|
Jul 16 07:29:56 PM PDT 24 |
Jul 16 07:31:37 PM PDT 24 |
809811251 ps |
| T935 |
/workspace/coverage/default/2.sram_ctrl_multiple_keys.3582900331 |
|
|
Jul 16 07:27:54 PM PDT 24 |
Jul 16 07:52:37 PM PDT 24 |
58012278581 ps |
| T936 |
/workspace/coverage/default/3.sram_ctrl_max_throughput.2114789660 |
|
|
Jul 16 07:27:56 PM PDT 24 |
Jul 16 07:28:17 PM PDT 24 |
2782435984 ps |
| T937 |
/workspace/coverage/default/39.sram_ctrl_bijection.1504133195 |
|
|
Jul 16 07:31:51 PM PDT 24 |
Jul 16 08:04:55 PM PDT 24 |
146646911284 ps |
| T938 |
/workspace/coverage/default/25.sram_ctrl_partial_access_b2b.1264200331 |
|
|
Jul 16 07:29:22 PM PDT 24 |
Jul 16 07:34:22 PM PDT 24 |
5577994688 ps |
| T60 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3848315019 |
|
|
Jul 16 07:24:53 PM PDT 24 |
Jul 16 07:25:50 PM PDT 24 |
17111715 ps |
| T939 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1393752367 |
|
|
Jul 16 07:25:36 PM PDT 24 |
Jul 16 07:26:35 PM PDT 24 |
1438362850 ps |
| T61 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1277110000 |
|
|
Jul 16 07:25:38 PM PDT 24 |
Jul 16 07:27:22 PM PDT 24 |
14683001840 ps |
| T940 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.937588520 |
|
|
Jul 16 07:25:34 PM PDT 24 |
Jul 16 07:26:31 PM PDT 24 |
110809346 ps |
| T62 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.949297523 |
|
|
Jul 16 07:25:16 PM PDT 24 |
Jul 16 07:26:15 PM PDT 24 |
92978338 ps |
| T941 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.343334827 |
|
|
Jul 16 07:25:12 PM PDT 24 |
Jul 16 07:26:12 PM PDT 24 |
279147890 ps |
| T95 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2903328931 |
|
|
Jul 16 07:25:34 PM PDT 24 |
Jul 16 07:26:29 PM PDT 24 |
49599287 ps |
| T942 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1528494212 |
|
|
Jul 16 07:25:14 PM PDT 24 |
Jul 16 07:26:11 PM PDT 24 |
362968601 ps |
| T67 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2899920036 |
|
|
Jul 16 07:25:23 PM PDT 24 |
Jul 16 07:27:14 PM PDT 24 |
30603246389 ps |
| T96 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1642848633 |
|
|
Jul 16 07:25:12 PM PDT 24 |
Jul 16 07:26:08 PM PDT 24 |
21013058 ps |
| T68 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.308660195 |
|
|
Jul 16 07:24:53 PM PDT 24 |
Jul 16 07:26:40 PM PDT 24 |
14668251562 ps |
| T69 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.488490881 |
|
|
Jul 16 07:25:14 PM PDT 24 |
Jul 16 07:26:56 PM PDT 24 |
25185901209 ps |
| T70 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1492373416 |
|
|
Jul 16 07:25:41 PM PDT 24 |
Jul 16 07:26:33 PM PDT 24 |
21376475 ps |
| T71 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2394892452 |
|
|
Jul 16 07:25:32 PM PDT 24 |
Jul 16 07:26:28 PM PDT 24 |
85050358 ps |
| T72 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1035500385 |
|
|
Jul 16 07:25:06 PM PDT 24 |
Jul 16 07:26:54 PM PDT 24 |
28196442845 ps |
| T943 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3924499485 |
|
|
Jul 16 07:25:23 PM PDT 24 |
Jul 16 07:26:25 PM PDT 24 |
3107371819 ps |
| T944 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1689343969 |
|
|
Jul 16 07:25:12 PM PDT 24 |
Jul 16 07:26:09 PM PDT 24 |
489687639 ps |
| T945 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3872385263 |
|
|
Jul 16 07:25:16 PM PDT 24 |
Jul 16 07:26:17 PM PDT 24 |
378125693 ps |
| T73 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.882962233 |
|
|
Jul 16 07:25:28 PM PDT 24 |
Jul 16 07:27:21 PM PDT 24 |
32101388741 ps |
| T946 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1869962436 |
|
|
Jul 16 07:25:27 PM PDT 24 |
Jul 16 07:26:25 PM PDT 24 |
125582135 ps |
| T947 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3485725426 |
|
|
Jul 16 07:25:17 PM PDT 24 |
Jul 16 07:26:19 PM PDT 24 |
714565997 ps |
| T54 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.958572735 |
|
|
Jul 16 07:25:09 PM PDT 24 |
Jul 16 07:26:08 PM PDT 24 |
152424664 ps |
| T74 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2630689016 |
|
|
Jul 16 07:25:06 PM PDT 24 |
Jul 16 07:26:01 PM PDT 24 |
45587917 ps |
| T948 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2175498627 |
|
|
Jul 16 07:25:12 PM PDT 24 |
Jul 16 07:26:09 PM PDT 24 |
336997647 ps |
| T75 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2673761644 |
|
|
Jul 16 07:25:09 PM PDT 24 |
Jul 16 07:26:07 PM PDT 24 |
12460621 ps |
| T949 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2698276470 |
|
|
Jul 16 07:25:35 PM PDT 24 |
Jul 16 07:26:31 PM PDT 24 |
103006085 ps |
| T950 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3865909132 |
|
|
Jul 16 07:25:16 PM PDT 24 |
Jul 16 07:26:17 PM PDT 24 |
162179531 ps |
| T951 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.690124498 |
|
|
Jul 16 07:25:38 PM PDT 24 |
Jul 16 07:26:31 PM PDT 24 |
30551863 ps |
| T952 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1395887558 |
|
|
Jul 16 07:25:27 PM PDT 24 |
Jul 16 07:27:25 PM PDT 24 |
88078305735 ps |
| T953 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.852612114 |
|
|
Jul 16 07:25:38 PM PDT 24 |
Jul 16 07:26:33 PM PDT 24 |
20150951 ps |
| T954 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2495654400 |
|
|
Jul 16 07:25:38 PM PDT 24 |
Jul 16 07:26:36 PM PDT 24 |
1470203699 ps |
| T955 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2713272174 |
|
|
Jul 16 07:25:06 PM PDT 24 |
Jul 16 07:26:02 PM PDT 24 |
130757433 ps |
| T956 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3273631719 |
|
|
Jul 16 07:25:26 PM PDT 24 |
Jul 16 07:26:24 PM PDT 24 |
75964184 ps |
| T957 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.89446619 |
|
|
Jul 16 07:25:42 PM PDT 24 |
Jul 16 07:26:34 PM PDT 24 |
34197081 ps |
| T958 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1840057431 |
|
|
Jul 16 07:25:09 PM PDT 24 |
Jul 16 07:26:07 PM PDT 24 |
43615657 ps |
| T78 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.841710815 |
|
|
Jul 16 07:25:37 PM PDT 24 |
Jul 16 07:26:32 PM PDT 24 |
27336399 ps |
| T79 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.214503059 |
|
|
Jul 16 07:25:16 PM PDT 24 |
Jul 16 07:27:02 PM PDT 24 |
73776797735 ps |
| T959 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2256471698 |
|
|
Jul 16 07:25:35 PM PDT 24 |
Jul 16 07:26:34 PM PDT 24 |
1455609708 ps |
| T80 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3035925265 |
|
|
Jul 16 07:25:05 PM PDT 24 |
Jul 16 07:26:01 PM PDT 24 |
112774159 ps |
| T55 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2675998490 |
|
|
Jul 16 07:25:27 PM PDT 24 |
Jul 16 07:26:26 PM PDT 24 |
97278261 ps |
| T960 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1774083386 |
|
|
Jul 16 07:25:13 PM PDT 24 |
Jul 16 07:26:12 PM PDT 24 |
351706764 ps |
| T961 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3856174596 |
|
|
Jul 16 07:25:14 PM PDT 24 |
Jul 16 07:26:08 PM PDT 24 |
43172237 ps |
| T962 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.336459386 |
|
|
Jul 16 07:25:39 PM PDT 24 |
Jul 16 07:26:31 PM PDT 24 |
186632233 ps |
| T963 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2012369253 |
|
|
Jul 16 07:25:30 PM PDT 24 |
Jul 16 07:26:25 PM PDT 24 |
13737751 ps |
| T964 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1881732303 |
|
|
Jul 16 07:24:54 PM PDT 24 |
Jul 16 07:25:51 PM PDT 24 |
12954076 ps |
| T965 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2223657201 |
|
|
Jul 16 07:25:09 PM PDT 24 |
Jul 16 07:26:08 PM PDT 24 |
119640916 ps |
| T966 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.493949342 |
|
|
Jul 16 07:25:35 PM PDT 24 |
Jul 16 07:26:33 PM PDT 24 |
63624847 ps |
| T967 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2884771666 |
|
|
Jul 16 07:25:08 PM PDT 24 |
Jul 16 07:26:06 PM PDT 24 |
58528080 ps |
| T56 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.469447559 |
|
|
Jul 16 07:25:13 PM PDT 24 |
Jul 16 07:26:11 PM PDT 24 |
560622085 ps |
| T968 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1673218606 |
|
|
Jul 16 07:24:56 PM PDT 24 |
Jul 16 07:25:55 PM PDT 24 |
40269657 ps |
| T969 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3192248208 |
|
|
Jul 16 07:25:33 PM PDT 24 |
Jul 16 07:26:29 PM PDT 24 |
32559904 ps |
| T109 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3315809894 |
|
|
Jul 16 07:25:15 PM PDT 24 |
Jul 16 07:26:13 PM PDT 24 |
370293876 ps |
| T970 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1891565953 |
|
|
Jul 16 07:25:13 PM PDT 24 |
Jul 16 07:26:11 PM PDT 24 |
700529226 ps |
| T971 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3119431914 |
|
|
Jul 16 07:25:40 PM PDT 24 |
Jul 16 07:26:35 PM PDT 24 |
62480505 ps |
| T119 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2822143959 |
|
|
Jul 16 07:25:16 PM PDT 24 |
Jul 16 07:26:16 PM PDT 24 |
282185709 ps |
| T972 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.666910300 |
|
|
Jul 16 07:24:57 PM PDT 24 |
Jul 16 07:25:50 PM PDT 24 |
25139981 ps |
| T118 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.4122573581 |
|
|
Jul 16 07:25:25 PM PDT 24 |
Jul 16 07:26:24 PM PDT 24 |
95447310 ps |
| T973 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1536816875 |
|
|
Jul 16 07:25:34 PM PDT 24 |
Jul 16 07:26:29 PM PDT 24 |
57898508 ps |
| T85 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1962900461 |
|
|
Jul 16 07:25:33 PM PDT 24 |
Jul 16 07:27:21 PM PDT 24 |
7100595700 ps |
| T974 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2670115202 |
|
|
Jul 16 07:25:07 PM PDT 24 |
Jul 16 07:26:06 PM PDT 24 |
1444225734 ps |
| T975 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.348078340 |
|
|
Jul 16 07:25:29 PM PDT 24 |
Jul 16 07:26:30 PM PDT 24 |
3268463325 ps |
| T976 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3209073290 |
|
|
Jul 16 07:25:09 PM PDT 24 |
Jul 16 07:26:09 PM PDT 24 |
171575073 ps |
| T86 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1587599940 |
|
|
Jul 16 07:25:37 PM PDT 24 |
Jul 16 07:27:24 PM PDT 24 |
47167973735 ps |
| T977 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3076645107 |
|
|
Jul 16 07:25:42 PM PDT 24 |
Jul 16 07:27:01 PM PDT 24 |
8258201486 ps |
| T87 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1631194265 |
|
|
Jul 16 07:24:55 PM PDT 24 |
Jul 16 07:25:51 PM PDT 24 |
42229310 ps |
| T978 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3615429100 |
|
|
Jul 16 07:25:14 PM PDT 24 |
Jul 16 07:26:09 PM PDT 24 |
118774620 ps |
| T112 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1370577230 |
|
|
Jul 16 07:25:51 PM PDT 24 |
Jul 16 07:26:45 PM PDT 24 |
417490774 ps |
| T979 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3009554304 |
|
|
Jul 16 07:25:17 PM PDT 24 |
Jul 16 07:26:15 PM PDT 24 |
17509687 ps |
| T980 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2757485167 |
|
|
Jul 16 07:25:05 PM PDT 24 |
Jul 16 07:26:01 PM PDT 24 |
52906350 ps |
| T981 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.649496038 |
|
|
Jul 16 07:25:15 PM PDT 24 |
Jul 16 07:26:09 PM PDT 24 |
48738900 ps |
| T982 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2865711297 |
|
|
Jul 16 07:25:07 PM PDT 24 |
Jul 16 07:26:04 PM PDT 24 |
131761653 ps |
| T110 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2866217850 |
|
|
Jul 16 07:25:17 PM PDT 24 |
Jul 16 07:26:16 PM PDT 24 |
502288950 ps |
| T983 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2534001099 |
|
|
Jul 16 07:25:37 PM PDT 24 |
Jul 16 07:26:34 PM PDT 24 |
34862174 ps |
| T984 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.931094995 |
|
|
Jul 16 07:25:23 PM PDT 24 |
Jul 16 07:26:22 PM PDT 24 |
16376759 ps |
| T985 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1164584355 |
|
|
Jul 16 07:25:17 PM PDT 24 |
Jul 16 07:26:15 PM PDT 24 |
12456239 ps |
| T111 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.33522507 |
|
|
Jul 16 07:25:41 PM PDT 24 |
Jul 16 07:26:34 PM PDT 24 |
326481767 ps |
| T986 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2749673855 |
|
|
Jul 16 07:25:04 PM PDT 24 |
Jul 16 07:26:03 PM PDT 24 |
93723921 ps |
| T113 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.4185125696 |
|
|
Jul 16 07:25:12 PM PDT 24 |
Jul 16 07:26:10 PM PDT 24 |
177386583 ps |
| T115 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2091222898 |
|
|
Jul 16 07:25:06 PM PDT 24 |
Jul 16 07:26:03 PM PDT 24 |
133034015 ps |
| T987 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.721988593 |
|
|
Jul 16 07:25:36 PM PDT 24 |
Jul 16 07:26:35 PM PDT 24 |
823608168 ps |
| T988 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3659707649 |
|
|
Jul 16 07:25:14 PM PDT 24 |
Jul 16 07:26:09 PM PDT 24 |
19857613 ps |
| T989 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.871718928 |
|
|
Jul 16 07:25:08 PM PDT 24 |
Jul 16 07:26:09 PM PDT 24 |
120410241 ps |
| T990 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3884078048 |
|
|
Jul 16 07:25:39 PM PDT 24 |
Jul 16 07:26:34 PM PDT 24 |
316075389 ps |
| T991 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3639151953 |
|
|
Jul 16 07:25:15 PM PDT 24 |
Jul 16 07:26:09 PM PDT 24 |
50179250 ps |
| T992 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.250479464 |
|
|
Jul 16 07:25:07 PM PDT 24 |
Jul 16 07:26:01 PM PDT 24 |
15899615 ps |
| T993 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.60161756 |
|
|
Jul 16 07:25:18 PM PDT 24 |
Jul 16 07:26:17 PM PDT 24 |
43982151 ps |
| T994 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1228778817 |
|
|
Jul 16 07:25:37 PM PDT 24 |
Jul 16 07:26:35 PM PDT 24 |
689168513 ps |
| T995 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1468776622 |
|
|
Jul 16 07:25:08 PM PDT 24 |
Jul 16 07:26:07 PM PDT 24 |
341824784 ps |
| T996 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1928965057 |
|
|
Jul 16 07:25:49 PM PDT 24 |
Jul 16 07:26:42 PM PDT 24 |
48297235 ps |
| T997 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2752288806 |
|
|
Jul 16 07:25:06 PM PDT 24 |
Jul 16 07:26:30 PM PDT 24 |
15381909888 ps |
| T998 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1350054407 |
|
|
Jul 16 07:25:08 PM PDT 24 |
Jul 16 07:26:06 PM PDT 24 |
70058697 ps |
| T116 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3590935070 |
|
|
Jul 16 07:25:29 PM PDT 24 |
Jul 16 07:26:28 PM PDT 24 |
366820319 ps |
| T999 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2706594780 |
|
|
Jul 16 07:25:38 PM PDT 24 |
Jul 16 07:26:31 PM PDT 24 |
39738810 ps |
| T1000 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2125543217 |
|
|
Jul 16 07:25:32 PM PDT 24 |
Jul 16 07:26:57 PM PDT 24 |
3853343801 ps |
| T1001 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.4248076969 |
|
|
Jul 16 07:25:14 PM PDT 24 |
Jul 16 07:26:09 PM PDT 24 |
62406862 ps |
| T1002 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1678083238 |
|
|
Jul 16 07:25:12 PM PDT 24 |
Jul 16 07:26:08 PM PDT 24 |
27479826 ps |
| T88 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1008420725 |
|
|
Jul 16 07:25:49 PM PDT 24 |
Jul 16 07:26:41 PM PDT 24 |
40017625 ps |
| T1003 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.4058334173 |
|
|
Jul 16 07:25:40 PM PDT 24 |
Jul 16 07:26:35 PM PDT 24 |
379490604 ps |
| T1004 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.847015535 |
|
|
Jul 16 07:25:26 PM PDT 24 |
Jul 16 07:26:23 PM PDT 24 |
97279311 ps |
| T1005 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2160152622 |
|
|
Jul 16 07:25:14 PM PDT 24 |
Jul 16 07:26:09 PM PDT 24 |
45219330 ps |
| T1006 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.184724443 |
|
|
Jul 16 07:25:27 PM PDT 24 |
Jul 16 07:26:28 PM PDT 24 |
1382544616 ps |
| T1007 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1017782865 |
|
|
Jul 16 07:24:54 PM PDT 24 |
Jul 16 07:25:52 PM PDT 24 |
633728416 ps |