Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16455052	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

177662486

1

T1

2202

T2

109538

T3

10000

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	95752723	1			T1	549		T2	60349		T3	4950
values[0x0]	47533138	1			T1	864		T2	28897		T3	2512
values[0x1]	50831677	1			T1	789		T2	31235		T3	2538

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8361617	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

185755921

1

T1

2202

T2

115015

T3

10000

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	729126	1			T1	8		T2	230		T3	48
valid_sources[0x01]	662381	1			T1	14		T2	433		T3	51
valid_sources[0x02]	1131747	1			T1	12		T2	387		T3	24
valid_sources[0x03]	2058107	1			T1	13		T2	465		T3	43
valid_sources[0x04]	677521	1			T1	9		T2	417		T3	29
valid_sources[0x05]	662088	1			T1	5		T2	579		T3	42
valid_sources[0x06]	673586	1			T1	7		T2	485		T3	55
valid_sources[0x07]	659913	1			T1	7		T2	731		T3	24
valid_sources[0x08]	707272	1			T1	4		T2	436		T3	35
valid_sources[0x09]	702543	1			T1	11		T2	985		T3	43
valid_sources[0x0a]	673845	1			T1	8		T2	544		T3	43
valid_sources[0x0b]	685830	1			T1	4		T2	142		T3	60
valid_sources[0x0c]	691268	1			T1	11		T2	254		T3	48
valid_sources[0x0d]	672109	1			T1	6		T2	247		T3	40
valid_sources[0x0e]	711223	1			T1	6		T2	223		T3	33
valid_sources[0x0f]	738950	1			T1	6		T2	286		T3	27
valid_sources[0x10]	676067	1			T1	13		T2	668		T3	30
valid_sources[0x11]	709941	1			T1	9		T2	358		T3	43
valid_sources[0x12]	697611	1			T1	6		T2	1049		T3	22
valid_sources[0x13]	1610052	1			T1	6		T2	475		T3	10
valid_sources[0x14]	676939	1			T1	8		T2	514		T3	42
valid_sources[0x15]	716043	1			T1	3		T2	452		T3	45
valid_sources[0x16]	701862	1			T1	14		T2	328		T3	48
valid_sources[0x17]	687740	1			T1	7		T2	361		T3	70
valid_sources[0x18]	674759	1			T1	5		T2	919		T3	73
valid_sources[0x19]	674268	1			T1	8		T2	364		T3	43
valid_sources[0x1a]	685982	1			T1	11		T2	508		T3	39
valid_sources[0x1b]	671100	1			T1	11		T2	670		T3	28
valid_sources[0x1c]	669344	1			T1	10		T2	611		T3	71
valid_sources[0x1d]	674308	1			T1	9		T2	319		T3	29
valid_sources[0x1e]	684452	1			T1	10		T2	370		T3	63
valid_sources[0x1f]	1650464	1			T1	11		T2	121		T3	28
valid_sources[0x20]	727543	1			T1	9		T2	219		T3	44
valid_sources[0x21]	694732	1			T1	7		T2	396		T3	36
valid_sources[0x22]	670836	1			T1	9		T2	322		T3	30
valid_sources[0x23]	688330	1			T1	7		T2	489		T3	51
valid_sources[0x24]	914177	1			T1	6		T2	160		T3	27
valid_sources[0x25]	673738	1			T1	7		T2	395		T3	26
valid_sources[0x26]	731868	1			T1	8		T2	408		T3	29
valid_sources[0x27]	711046	1			T1	9		T2	592		T3	37
valid_sources[0x28]	741673	1			T1	4		T2	429		T3	23
valid_sources[0x29]	691946	1			T1	17		T2	413		T3	18
valid_sources[0x2a]	661059	1			T1	8		T2	676		T3	21
valid_sources[0x2b]	1660329	1			T1	6		T2	120		T3	8
valid_sources[0x2c]	676866	1			T1	14		T2	326		T3	31
valid_sources[0x2d]	718412	1			T1	10		T2	423		T3	84
valid_sources[0x2e]	687257	1			T1	4		T2	260		T3	18
valid_sources[0x2f]	672123	1			T1	9		T2	714		T3	38
valid_sources[0x30]	681587	1			T1	10		T2	187		T3	30
valid_sources[0x31]	676771	1			T1	12		T2	237		T3	28
valid_sources[0x32]	669296	1			T1	8		T2	295		T3	22
valid_sources[0x33]	759578	1			T1	7		T2	423		T3	31
valid_sources[0x34]	671139	1			T1	6		T2	278		T3	37
valid_sources[0x35]	677818	1			T1	19		T2	531		T3	36
valid_sources[0x36]	700016	1			T1	12		T2	631		T3	47
valid_sources[0x37]	709292	1			T1	9		T2	498		T3	37
valid_sources[0x38]	701291	1			T1	10		T2	417		T3	39
valid_sources[0x39]	814951	1			T1	4		T2	311		T3	35
valid_sources[0x3a]	674924	1			T1	12		T2	551		T3	47
valid_sources[0x3b]	762044	1			T1	16		T2	522		T3	38
valid_sources[0x3c]	667253	1			T1	11		T2	263		T3	55
valid_sources[0x3d]	663194	1			T1	10		T2	301		T3	16
valid_sources[0x3e]	683808	1			T1	11		T2	438		T3	28
valid_sources[0x3f]	676005	1			T1	8		T2	450		T3	66
valid_sources[0x40]	662993	1			T1	7		T2	978		T3	59
valid_sources[0x41]	659611	1			T1	5		T2	319		T3	50
valid_sources[0x42]	1408229	1			T1	14		T2	690		T3	18
valid_sources[0x43]	700679	1			T1	5		T2	224		T3	37
valid_sources[0x44]	661320	1			T1	6		T2	182		T3	70
valid_sources[0x45]	679150	1			T1	8		T2	438		T3	53
valid_sources[0x46]	670190	1			T1	9		T2	327		T3	68
valid_sources[0x47]	666512	1			T1	8		T2	381		T3	30
valid_sources[0x48]	693244	1			T1	3		T2	1185		T3	77
valid_sources[0x49]	696075	1			T1	16		T2	464		T3	53
valid_sources[0x4a]	678180	1			T1	6		T2	659		T3	33
valid_sources[0x4b]	700574	1			T1	2		T2	145		T3	41
valid_sources[0x4c]	675398	1			T1	6		T2	370		T3	40
valid_sources[0x4d]	662016	1			T1	14		T2	363		T3	48
valid_sources[0x4e]	670891	1			T1	11		T2	296		T3	52
valid_sources[0x4f]	690085	1			T1	10		T2	402		T3	19
valid_sources[0x50]	656828	1			T1	16		T2	683		T3	18
valid_sources[0x51]	668734	1			T1	9		T2	382		T3	36
valid_sources[0x52]	698392	1			T1	9		T2	608		T3	66
valid_sources[0x53]	686109	1			T1	12		T2	921		T3	43
valid_sources[0x54]	1807440	1			T1	14		T2	193		T3	20
valid_sources[0x55]	660543	1			T1	10		T2	611		T3	38
valid_sources[0x56]	713245	1			T1	6		T2	326		T3	42
valid_sources[0x57]	699619	1			T1	8		T2	174		T3	53
valid_sources[0x58]	658146	1			T1	7		T2	472		T3	49
valid_sources[0x59]	678566	1			T1	11		T2	572		T3	10
valid_sources[0x5a]	878325	1			T1	7		T2	213		T3	35
valid_sources[0x5b]	692721	1			T1	18		T2	481		T3	38
valid_sources[0x5c]	707060	1			T1	8		T2	701		T3	36
valid_sources[0x5d]	700773	1			T1	5		T2	794		T3	53
valid_sources[0x5e]	692460	1			T1	7		T2	573		T3	11
valid_sources[0x5f]	773147	1			T1	11		T2	1202		T3	31
valid_sources[0x60]	674899	1			T1	12		T2	831		T3	25
valid_sources[0x61]	699477	1			T1	10		T2	538		T3	44
valid_sources[0x62]	682134	1			T1	9		T2	476		T3	58
valid_sources[0x63]	675784	1			T1	8		T2	399		T3	47
valid_sources[0x64]	696423	1			T1	9		T2	450		T3	18
valid_sources[0x65]	752140	1			T1	6		T2	368		T3	31
valid_sources[0x66]	701601	1			T1	7		T2	567		T3	45
valid_sources[0x67]	682284	1			T1	5		T2	206		T3	53
valid_sources[0x68]	670105	1			T1	5		T2	256		T3	51
valid_sources[0x69]	690110	1			T1	6		T2	224		T3	53
valid_sources[0x6a]	677497	1			T1	5		T2	92		T3	27
valid_sources[0x6b]	671553	1			T1	7		T2	402		T3	38
valid_sources[0x6c]	672493	1			T1	7		T2	360		T3	31
valid_sources[0x6d]	865857	1			T1	7		T2	435		T3	56
valid_sources[0x6e]	665660	1			T1	17		T2	506		T3	18
valid_sources[0x6f]	666742	1			T1	9		T2	649		T3	57
valid_sources[0x70]	705393	1			T1	9		T2	357		T3	29
valid_sources[0x71]	690263	1			T1	10		T2	524		T3	19
valid_sources[0x72]	686874	1			T1	10		T2	621		T3	37
valid_sources[0x73]	790110	1			T1	9		T2	239		T3	39
valid_sources[0x74]	730131	1			T1	15		T2	385		T3	65
valid_sources[0x75]	665264	1			T1	13		T2	362		T3	66
valid_sources[0x76]	693527	1			T1	10		T2	636		T3	29
valid_sources[0x77]	664788	1			T1	10		T2	249		T3	29
valid_sources[0x78]	727087	1			T1	8		T2	720		T3	46
valid_sources[0x79]	1532635	1			T1	12		T2	301		T3	57
valid_sources[0x7a]	764519	1			T1	11		T2	616		T3	50
valid_sources[0x7b]	679015	1			T1	8		T2	695		T3	9
valid_sources[0x7c]	699667	1			T1	7		T2	828		T3	18
valid_sources[0x7d]	664948	1			T1	8		T2	356		T3	36
valid_sources[0x7e]	798911	1			T1	8		T2	301		T3	22
valid_sources[0x7f]	705276	1			T1	10		T2	366		T3	38
valid_sources[0x80]	687398	1			T1	12		T2	464		T3	29

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

87482320

1

T1

549

T2

54762

T3

4950

values[0x0]

all_enables

biggest_size

45077883

1

T1

864

T2

27263

T3

2512

values[0x1]

all_enables

biggest_size

45102283

1

T1

789

T2

27513

T3

2538

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	46317	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

174552

1

T1

1391

T2

9

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	59356	1			T1	348		T8	12		T5	37
values[0x0]	77892	1			T1	516		T2	9		T3	1
values[0x1]	83621	1			T1	611		T2	9		T3	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35322	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

185547

1

T1

1429

T2

10

T3

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	755	1			T1	6		T23	10		T24	2
valid_sources[0x01]	1028	1			T1	9		T23	20		T24	119
valid_sources[0x02]	947	1			T1	1		T23	22		T24	23
valid_sources[0x03]	842	1			T1	7		T23	40		T24	3
valid_sources[0x04]	609	1			T1	4		T55	2		T7	1
valid_sources[0x05]	738	1			T6	1		T23	14		T140	1
valid_sources[0x06]	679	1			T1	5		T23	24		T24	3
valid_sources[0x07]	1125	1			T1	5		T2	1		T23	24
valid_sources[0x08]	740	1			T1	13		T23	22		T24	4
valid_sources[0x09]	686	1			T1	1		T23	11		T19	1
valid_sources[0x0a]	944	1			T1	10		T53	1		T6	2
valid_sources[0x0b]	715	1			T1	6		T53	1		T23	6
valid_sources[0x0c]	1040	1			T1	5		T23	21		T24	1
valid_sources[0x0d]	1031	1			T1	2		T23	29		T47	1
valid_sources[0x0e]	1016	1			T1	5		T23	8		T140	4
valid_sources[0x0f]	780	1			T1	2		T23	21		T24	112
valid_sources[0x10]	1074	1			T1	6		T23	13		T24	75
valid_sources[0x11]	996	1			T23	29		T43	1		T47	3
valid_sources[0x12]	1040	1			T1	9		T23	14		T24	1
valid_sources[0x13]	1149	1			T1	5		T57	2		T13	1
valid_sources[0x14]	695	1			T1	7		T23	43		T47	1
valid_sources[0x15]	1082	1			T1	3		T23	11		T24	128
valid_sources[0x16]	798	1			T1	9		T10	1		T23	14
valid_sources[0x17]	1278	1			T1	2		T42	2		T6	1
valid_sources[0x18]	805	1			T1	10		T6	2		T7	3
valid_sources[0x19]	798	1			T1	11		T53	1		T23	14
valid_sources[0x1a]	691	1			T1	4		T23	16		T24	6
valid_sources[0x1b]	648	1			T1	5		T3	1		T23	16
valid_sources[0x1c]	688	1			T1	3		T7	4		T23	19
valid_sources[0x1d]	848	1			T1	8		T2	1		T42	4
valid_sources[0x1e]	671	1			T1	8		T6	1		T23	24
valid_sources[0x1f]	956	1			T1	12		T23	17		T24	87
valid_sources[0x20]	966	1			T1	11		T23	47		T24	2
valid_sources[0x21]	848	1			T1	3		T23	20		T24	4
valid_sources[0x22]	757	1			T1	6		T23	20		T24	14
valid_sources[0x23]	610	1			T1	7		T26	4		T23	16
valid_sources[0x24]	850	1			T1	11		T23	23		T24	4
valid_sources[0x25]	681	1			T1	3		T23	19		T52	1
valid_sources[0x26]	924	1			T1	7		T134	1		T23	28
valid_sources[0x27]	623	1			T1	10		T7	3		T23	11
valid_sources[0x28]	732	1			T1	9		T23	10		T24	3
valid_sources[0x29]	788	1			T1	12		T10	1		T23	25
valid_sources[0x2a]	735	1			T1	2		T23	26		T24	1
valid_sources[0x2b]	773	1			T1	6		T6	2		T23	26
valid_sources[0x2c]	1091	1			T1	6		T26	4		T6	1
valid_sources[0x2d]	619	1			T1	6		T6	3		T23	11
valid_sources[0x2e]	860	1			T1	2		T53	1		T23	9
valid_sources[0x2f]	1102	1			T1	6		T23	16		T24	194
valid_sources[0x30]	938	1			T1	2		T134	1		T23	13
valid_sources[0x31]	609	1			T1	4		T23	28		T47	2
valid_sources[0x32]	640	1			T1	9		T23	9		T52	1
valid_sources[0x33]	757	1			T1	4		T23	32		T52	1
valid_sources[0x34]	731	1			T1	4		T23	8		T24	1
valid_sources[0x35]	766	1			T1	3		T53	1		T42	7
valid_sources[0x36]	748	1			T1	7		T23	14		T47	1
valid_sources[0x37]	662	1			T1	11		T9	1		T6	1
valid_sources[0x38]	957	1			T1	10		T134	1		T23	27
valid_sources[0x39]	571	1			T1	6		T6	1		T7	6
valid_sources[0x3a]	891	1			T1	13		T7	1		T23	19
valid_sources[0x3b]	839	1			T1	3		T23	15		T24	21
valid_sources[0x3c]	1497	1			T1	3		T23	15		T24	49
valid_sources[0x3d]	912	1			T1	2		T23	32		T24	2
valid_sources[0x3e]	757	1			T1	5		T9	1		T6	2
valid_sources[0x3f]	1075	1			T1	3		T23	26		T47	1
valid_sources[0x40]	776	1			T1	6		T6	1		T23	40
valid_sources[0x41]	914	1			T1	5		T134	1		T23	23
valid_sources[0x42]	945	1			T1	5		T6	1		T23	19
valid_sources[0x43]	833	1			T1	5		T10	4		T7	8
valid_sources[0x44]	1061	1			T1	9		T42	1		T7	3
valid_sources[0x45]	883	1			T1	6		T23	8		T47	1
valid_sources[0x46]	585	1			T1	8		T53	1		T23	29
valid_sources[0x47]	721	1			T1	4		T23	22		T24	3
valid_sources[0x48]	921	1			T1	6		T23	21		T16	1
valid_sources[0x49]	834	1			T1	7		T6	1		T23	34
valid_sources[0x4a]	796	1			T1	7		T23	29		T24	13
valid_sources[0x4b]	844	1			T1	6		T23	25		T24	22
valid_sources[0x4c]	1011	1			T1	6		T23	19		T24	1
valid_sources[0x4d]	907	1			T1	7		T12	1		T23	32
valid_sources[0x4e]	798	1			T1	5		T11	6		T53	4
valid_sources[0x4f]	1174	1			T1	10		T25	10		T23	22
valid_sources[0x50]	607	1			T1	2		T23	16		T24	1
valid_sources[0x51]	954	1			T1	2		T23	19		T43	1
valid_sources[0x52]	766	1			T1	10		T7	1		T23	39
valid_sources[0x53]	805	1			T1	1		T10	3		T23	21
valid_sources[0x54]	1306	1			T1	2		T23	40		T24	171
valid_sources[0x55]	1011	1			T1	3		T23	36		T52	1
valid_sources[0x56]	727	1			T1	16		T53	1		T7	1
valid_sources[0x57]	1015	1			T53	2		T23	27		T24	2
valid_sources[0x58]	933	1			T1	8		T23	26		T24	122
valid_sources[0x59]	1334	1			T1	4		T53	2		T23	46
valid_sources[0x5a]	709	1			T1	5		T2	2		T10	3
valid_sources[0x5b]	899	1			T1	6		T23	61		T47	2
valid_sources[0x5c]	698	1			T1	9		T23	30		T24	2
valid_sources[0x5d]	681	1			T1	3		T23	15		T52	1
valid_sources[0x5e]	656	1			T1	7		T53	3		T23	38
valid_sources[0x5f]	830	1			T1	7		T6	1		T23	37
valid_sources[0x60]	1019	1			T1	7		T23	36		T24	3
valid_sources[0x61]	767	1			T1	2		T7	2		T23	28
valid_sources[0x62]	711	1			T1	14		T53	1		T23	29
valid_sources[0x63]	984	1			T1	5		T23	22		T24	43
valid_sources[0x64]	1222	1			T1	1		T6	1		T23	12
valid_sources[0x65]	739	1			T1	6		T7	4		T23	19
valid_sources[0x66]	1279	1			T1	11		T23	32		T24	2
valid_sources[0x67]	882	1			T1	8		T23	25		T24	117
valid_sources[0x68]	804	1			T1	4		T9	1		T134	1
valid_sources[0x69]	697	1			T1	11		T23	13		T24	3
valid_sources[0x6a]	1013	1			T1	4		T23	26		T24	4
valid_sources[0x6b]	993	1			T1	2		T6	2		T23	16
valid_sources[0x6c]	686	1			T1	10		T6	2		T23	24
valid_sources[0x6d]	862	1			T1	7		T40	53		T6	1
valid_sources[0x6e]	728	1			T1	5		T23	30		T24	32
valid_sources[0x6f]	768	1			T1	2		T23	3		T24	77
valid_sources[0x70]	607	1			T1	3		T23	25		T24	1
valid_sources[0x71]	1017	1			T1	4		T23	16		T24	2
valid_sources[0x72]	1295	1			T1	3		T23	41		T19	1
valid_sources[0x73]	565	1			T1	4		T2	2		T23	20
valid_sources[0x74]	791	1			T1	9		T23	35		T24	16
valid_sources[0x75]	542	1			T1	7		T23	10		T24	1
valid_sources[0x76]	754	1			T1	2		T23	18		T15	10
valid_sources[0x77]	984	1			T1	6		T51	20		T134	1
valid_sources[0x78]	1051	1			T1	4		T23	22		T24	331
valid_sources[0x79]	747	1			T1	9		T23	17		T24	3
valid_sources[0x7a]	828	1			T1	9		T53	1		T23	31
valid_sources[0x7b]	1154	1			T1	8		T23	32		T24	92
valid_sources[0x7c]	1237	1			T1	8		T23	53		T24	1
valid_sources[0x7d]	971	1			T1	2		T23	50		T47	2
valid_sources[0x7e]	1016	1			T1	6		T10	1		T23	34
valid_sources[0x7f]	560	1			T1	7		T23	40		T47	1
valid_sources[0x80]	790	1			T1	9		T23	21		T24	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

46068

1

T1

324

T8

5

T5

18

values[0x0]

all_enables

biggest_size

65714

1

T1

508

T2

6

T3

1

values[0x1]

all_enables

biggest_size

62770

1

T1

559

T2

3

T8

9