Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16386717

1

T1

1953

T2

8911

T4

695

full_word

174435340

1

T1

2448

T2

90279

T3

10000

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	190821737	1			T1	4401		T2	99190		T3	10000
auto[TlIntgErrCmd]	109	1			T67	4		T68	8		T69	7
auto[TlIntgErrData]	113	1			T67	4		T68	6		T69	2
auto[TlIntgErrBoth]	98	1			T67	2		T68	6		T69	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

92339365

1

T1

999

T2

39058

T3

4950

auto[1]

98482692

1

T1

3402

T2

60132

T3

5050

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	8006547	1			T1	387		T2	3555		T4	336
auto[TlIntgErrNone]	partial	auto[1]	8379878	1			T1	1566		T2	5356		T4	359
auto[TlIntgErrNone]	full_word	auto[0]	84332666	1			T1	612		T2	35503		T3	4950
auto[TlIntgErrNone]	full_word	auto[1]	90102646	1			T1	1836		T2	54776		T3	5050
auto[TlIntgErrCmd]	partial	auto[0]	49	1			T67	1		T68	4		T69	5
auto[TlIntgErrCmd]	partial	auto[1]	53	1			T67	1		T68	4		T69	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T67	1		T118	1		T120	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T67	1		T121	1		T119	1
auto[TlIntgErrData]	partial	auto[0]	53	1			T67	1		T68	3		T69	2
auto[TlIntgErrData]	partial	auto[1]	48	1			T67	3		T68	2		T118	1
auto[TlIntgErrData]	full_word	auto[0]	7	1			T119	1		T124	1		T125	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T68	1		T120	1		T123	1
auto[TlIntgErrBoth]	partial	auto[0]	36	1			T67	1		T68	3		T118	1
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T67	1		T68	3		T118	5
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T69	1		T126	1		T127	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T121	1		T128	2		T124	1