Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	990839	1			T8	21		T9	109		T5	14
auto[1]	10407406	1			T2	3626		T3	4950		T4	1
auto[2]	752300	1			T8	28		T9	63		T5	8
auto[3]	10124095	1			T2	2778		T3	5049		T4	2

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14525645	1			T2	5393		T3	9999		T4	3
auto[1]	2043327	1			T2	449		T8	68		T9	236
auto[2]	2084558	1			T2	508		T8	106		T9	365
auto[3]	3621110	1			T2	54		T8	13		T9	40

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9063661

1

T2

6403

T3

9998

T4

3

auto[1]

13210979

1

T2

1

T3

1

T10

2

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	395778	1			T8	18		T9	90		T5	14
auto[0]	auto[0]	auto[1]	41655	1			T8	1		T9	9		T51	33
auto[0]	auto[0]	auto[2]	41107	1			T8	2		T9	10		T51	38
auto[0]	auto[0]	auto[3]	62079	1			T51	5		T56	1		T6	1
auto[0]	auto[1]	auto[0]	3180029	1			T2	3030		T3	4950		T4	1
auto[0]	auto[1]	auto[1]	339677	1			T2	258		T8	45		T9	165
auto[0]	auto[1]	auto[2]	342608	1			T2	306		T8	25		T9	91
auto[0]	auto[1]	auto[3]	299498	1			T2	32		T8	3		T9	14
auto[0]	auto[2]	auto[0]	282671	1			T5	6		T6	23		T39	6
auto[0]	auto[2]	auto[1]	31953	1			T6	6		T134	430		T24	31
auto[0]	auto[2]	auto[2]	34790	1			T8	25		T9	59		T5	2
auto[0]	auto[2]	auto[3]	43402	1			T8	3		T9	4		T51	28
auto[0]	auto[3]	auto[0]	3029928	1			T2	2362		T3	5048		T4	2
auto[0]	auto[3]	auto[1]	323150	1			T2	191		T8	22		T9	62
auto[0]	auto[3]	auto[2]	346634	1			T2	202		T8	54		T9	205
auto[0]	auto[3]	auto[3]	268702	1			T2	22		T8	7		T9	22
auto[1]	auto[0]	auto[0]	14894	1			T63	116		T106	143		T135	239
auto[1]	auto[0]	auto[1]	67199	1			T63	591		T106	659		T135	1008
auto[1]	auto[0]	auto[2]	66715	1			T63	551		T106	570		T135	990
auto[1]	auto[0]	auto[3]	301412	1			T63	2710		T85	1		T86	2
auto[1]	auto[1]	auto[0]	3808508	1			T10	2		T41	94333		T51	1
auto[1]	auto[1]	auto[1]	622949	1			T41	8465		T54	12095		T63	1689
auto[1]	auto[1]	auto[2]	588519	1			T41	9434		T54	13105		T63	1038
auto[1]	auto[1]	auto[3]	1225618	1			T41	857		T54	54413		T63	8031
auto[1]	auto[2]	auto[0]	10678	1			T136	517		T137	139		T138	1
auto[1]	auto[2]	auto[1]	47707	1			T136	2240		T137	534		T139	1087
auto[1]	auto[2]	auto[2]	55153	1			T63	553		T106	564		T135	908
auto[1]	auto[2]	auto[3]	245946	1			T63	2254		T106	2454		T135	4081
auto[1]	auto[3]	auto[0]	3803159	1			T2	1		T3	1		T41	94613
auto[1]	auto[3]	auto[1]	569037	1			T41	9555		T54	13147		T63	446
auto[1]	auto[3]	auto[2]	609032	1			T11	1		T41	8628		T54	11840
auto[1]	auto[3]	auto[3]	1174453	1			T41	841		T54	54231		T63	7630