Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1360801276	267453	0	0
ctrl_regwen_rd_A	1360801276	4778	0	0
exec_rd_A	1360801276	4469	0	0
exec_regwen_rd_A	1360801276	5053	0	0
readback_rd_A	1360801276	3503	0	0
readback_regwen_rd_A	1360801276	3223	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1360801276	267453	0	0
T1	26479	1868	0	0
T2	491710	0	0	0
T3	77136	0	0	0
T4	90634	0	0	0
T5	156449	0	0	0
T8	104697	0	0	0
T9	616382	0	0	0
T10	158022	0	0	0
T11	420435	0	0	0
T12	71776	0	0	0
T23	0	10805	0	0
T24	0	9639	0	0
T48	0	6626	0	0
T50	0	6236	0	0
T58	0	3160	0	0
T59	0	6630	0	0
T74	0	3323	0	0
T75	0	806	0	0
T76	0	5026	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1360801276	4778	0	0
T14	1425	0	0	0
T15	1086	0	0	0
T24	387227	685	0	0
T27	33947	0	0	0
T43	837770	0	0	0
T48	0	482	0	0
T61	0	225	0	0
T63	133808	0	0	0
T64	69218	0	0	0
T65	827228	0	0	0
T66	680594	0	0	0
T74	0	350	0	0
T75	0	85	0	0
T85	236595	0	0	0
T113	0	127	0	0
T114	0	203	0	0
T115	0	317	0	0
T116	0	77	0	0
T117	0	142	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1360801276	4469	0	0
T14	1425	0	0	0
T15	1086	0	0	0
T24	387227	636	0	0
T27	33947	0	0	0
T43	837770	0	0	0
T48	0	538	0	0
T61	0	229	0	0
T63	133808	0	0	0
T64	69218	0	0	0
T65	827228	0	0	0
T66	680594	0	0	0
T74	0	227	0	0
T75	0	41	0	0
T85	236595	0	0	0
T113	0	174	0	0
T114	0	223	0	0
T115	0	337	0	0
T116	0	39	0	0
T117	0	99	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1360801276	5053	0	0
T14	1425	0	0	0
T15	1086	0	0	0
T24	387227	735	0	0
T27	33947	0	0	0
T43	837770	0	0	0
T48	0	567	0	0
T61	0	270	0	0
T63	133808	0	0	0
T64	69218	0	0	0
T65	827228	0	0	0
T66	680594	0	0	0
T74	0	299	0	0
T75	0	55	0	0
T85	236595	0	0	0
T113	0	176	0	0
T114	0	257	0	0
T115	0	444	0	0
T116	0	72	0	0
T117	0	112	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1360801276	3503	0	0
T14	1425	0	0	0
T15	1086	0	0	0
T24	387227	710	0	0
T27	33947	0	0	0
T43	837770	0	0	0
T48	0	519	0	0
T61	0	173	0	0
T63	133808	0	0	0
T64	69218	0	0	0
T65	827228	0	0	0
T66	680594	0	0	0
T74	0	260	0	0
T75	0	19	0	0
T85	236595	0	0	0
T113	0	119	0	0
T114	0	248	0	0
T115	0	360	0	0
T116	0	19	0	0
T117	0	64	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1360801276	3223	0	0
T14	1425	0	0	0
T15	1086	0	0	0
T24	387227	571	0	0
T27	33947	0	0	0
T43	837770	0	0	0
T48	0	476	0	0
T61	0	176	0	0
T63	133808	0	0	0
T64	69218	0	0	0
T65	827228	0	0	0
T66	680594	0	0	0
T74	0	218	0	0
T75	0	33	0	0
T85	236595	0	0	0
T113	0	146	0	0
T114	0	216	0	0
T115	0	324	0	0
T116	0	35	0	0
T117	0	101	0	0