Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	329901808	1			T1	202408		T2	11552		T3	11136
instr_valid_dis	292374865	1			T1	202408		T2	11552		T3	11136
instr_en	23997642	1			T11	16206		T25	140788		T26	169038

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	12772280	1			T5	73624		T25	95886		T26	29074
sram_ifetch_valid_disable	290235030	1			T1	202408		T2	11552		T3	11136
sram_ifetch_enable	26894498	1			T5	8878		T11	9814		T25	45468

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	329901808	1			T1	202408		T2	11552		T3	11136
hw_debug_en_valid_off	293371296	1			T1	202408		T2	11552		T3	11136
hw_debug_en_on	24592024	1			T5	140664		T11	9814		T25	171144

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	290235030	1			T1	202408		T2	11552		T3	11136
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	273729729	1			T1	202408		T2	11552		T3	11136
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9240686	1			T11	16206		T25	70552		T26	58362
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	5979396	1			T5	25268		T25	27758		T7	72320
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	4165456	1			T25	9766		T7	72320		T126	4950
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1050344	1			T25	17992		T131	23466		T22	17696
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4963998	1			T5	46032		T25	36008		T26	29074
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1754820	1			T26	29074		T7	70638		T128	13518
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1963930	1			T25	36008		T7	22884		T127	16130
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	10166546	1			T5	91362		T25	105764		T26	58362
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3079548	1			T25	49714		T7	14630		T127	48388
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	5156650	1			T25	56050		T26	58362		T7	59626

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	10957542	1			T25	16236		T26	110676		T7	30314
lc_exec_en	9461480	1			T5	3270		T11	9814		T25	29372
valid_exec_dis	288154056	1			T1	202408		T2	11552		T3	11136
invalid_exec_dis	39666778	1			T5	82502		T11	9814		T25	141354