| Name |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.86991303 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2965693486 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2268047301 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3637011111 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.85674890 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.4067623378 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2018376753 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1657601811 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3200915603 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1357304805 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3447440022 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.233036158 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2192249120 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1765458800 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.846280342 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1712091076 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3291573160 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2820476091 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3134946671 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1900779296 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1535019185 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3132974552 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1473007595 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2170257769 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2092684287 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1619164166 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1749208609 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1754881810 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.271670345 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2208493842 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3557928361 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2528250565 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2892300288 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.4250490423 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3209724482 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.937138079 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3856755288 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2188575980 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3111965282 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.507134483 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.117622433 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3407965646 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.68893118 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2860355109 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2929963627 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2752097647 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3365628251 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3541514035 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.565831984 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.951584941 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2838432818 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.254289377 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.616141625 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2078309947 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1211913361 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3720518964 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.293540699 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1459826187 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.749695360 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3263471866 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.4188322892 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2886158373 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.948654216 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1093020363 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.676091772 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.262215183 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.90940149 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.464128160 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1474574328 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3995435342 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1126862017 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1916304239 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.940627438 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1872591315 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1404272510 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.946536127 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.282386246 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2136565294 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3429521340 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.329794626 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1571090209 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.877846934 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2005330079 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2355167950 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2797386207 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.4139271273 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3027132368 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3649880079 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.648110743 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2760372689 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3683710598 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1087453697 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.662265861 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3635564837 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2880354916 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1072759556 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.4146014613 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3038405798 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3926491641 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3449950763 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.194478689 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3220608784 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1036513886 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2286449669 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2576025851 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2829191752 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.881307337 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3883938545 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3559350829 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.914467860 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1738840803 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2270089289 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2967165524 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2385264420 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.454340834 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3146077515 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1849217216 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2699703907 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2712263561 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1868427435 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.588877574 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1689117202 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1183982756 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1016492013 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2478360935 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2134656891 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1629333516 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2161230557 |
| /workspace/coverage/default/0.sram_ctrl_access_during_key_req.2888253490 |
| /workspace/coverage/default/0.sram_ctrl_alert_test.2502303970 |
| /workspace/coverage/default/0.sram_ctrl_bijection.2405665149 |
| /workspace/coverage/default/0.sram_ctrl_executable.122453272 |
| /workspace/coverage/default/0.sram_ctrl_lc_escalation.13101093 |
| /workspace/coverage/default/0.sram_ctrl_max_throughput.1859360923 |
| /workspace/coverage/default/0.sram_ctrl_mem_partial_access.1001923675 |
| /workspace/coverage/default/0.sram_ctrl_mem_walk.2911160414 |
| /workspace/coverage/default/0.sram_ctrl_multiple_keys.3098006557 |
| /workspace/coverage/default/0.sram_ctrl_partial_access.2899943033 |
| /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2370213097 |
| /workspace/coverage/default/0.sram_ctrl_ram_cfg.858976927 |
| /workspace/coverage/default/0.sram_ctrl_regwen.1787804821 |
| /workspace/coverage/default/0.sram_ctrl_smoke.3297974650 |
| /workspace/coverage/default/0.sram_ctrl_stress_all.60101326 |
| /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.3360318077 |
| /workspace/coverage/default/0.sram_ctrl_stress_pipeline.1765292749 |
| /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.800389280 |
| /workspace/coverage/default/1.sram_ctrl_access_during_key_req.2225059051 |
| /workspace/coverage/default/1.sram_ctrl_alert_test.2733909683 |
| /workspace/coverage/default/1.sram_ctrl_bijection.552728483 |
| /workspace/coverage/default/1.sram_ctrl_executable.2237265417 |
| /workspace/coverage/default/1.sram_ctrl_lc_escalation.1914026600 |
| /workspace/coverage/default/1.sram_ctrl_max_throughput.1001417580 |
| /workspace/coverage/default/1.sram_ctrl_mem_partial_access.1909229855 |
| /workspace/coverage/default/1.sram_ctrl_mem_walk.3185642649 |
| /workspace/coverage/default/1.sram_ctrl_multiple_keys.1772327035 |
| /workspace/coverage/default/1.sram_ctrl_partial_access.1389776620 |
| /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.2149678468 |
| /workspace/coverage/default/1.sram_ctrl_ram_cfg.3906116099 |
| /workspace/coverage/default/1.sram_ctrl_regwen.2447603530 |
| /workspace/coverage/default/1.sram_ctrl_sec_cm.2151412687 |
| /workspace/coverage/default/1.sram_ctrl_smoke.3129814214 |
| /workspace/coverage/default/1.sram_ctrl_stress_all.488188919 |
| /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.767857569 |
| /workspace/coverage/default/1.sram_ctrl_stress_pipeline.76721280 |
| /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.239871410 |
| /workspace/coverage/default/10.sram_ctrl_access_during_key_req.1637147139 |
| /workspace/coverage/default/10.sram_ctrl_alert_test.2551032325 |
| /workspace/coverage/default/10.sram_ctrl_bijection.712301974 |
| /workspace/coverage/default/10.sram_ctrl_executable.3024793743 |
| /workspace/coverage/default/10.sram_ctrl_lc_escalation.1790563806 |
| /workspace/coverage/default/10.sram_ctrl_max_throughput.3168657334 |
| /workspace/coverage/default/10.sram_ctrl_mem_partial_access.2405732363 |
| /workspace/coverage/default/10.sram_ctrl_mem_walk.3170426596 |
| /workspace/coverage/default/10.sram_ctrl_multiple_keys.1943909150 |
| /workspace/coverage/default/10.sram_ctrl_partial_access.2824620329 |
| /workspace/coverage/default/10.sram_ctrl_ram_cfg.2922725348 |
| /workspace/coverage/default/10.sram_ctrl_smoke.3752704480 |
| /workspace/coverage/default/10.sram_ctrl_stress_all.3774807462 |
| /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1617155818 |
| /workspace/coverage/default/10.sram_ctrl_stress_pipeline.702800774 |
| /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2654237036 |
| /workspace/coverage/default/11.sram_ctrl_access_during_key_req.1391428668 |
| /workspace/coverage/default/11.sram_ctrl_bijection.2438398351 |
| /workspace/coverage/default/11.sram_ctrl_executable.2430493115 |
| /workspace/coverage/default/11.sram_ctrl_lc_escalation.4000878569 |
| /workspace/coverage/default/11.sram_ctrl_max_throughput.3550300001 |
| /workspace/coverage/default/11.sram_ctrl_mem_partial_access.2666069690 |
| /workspace/coverage/default/11.sram_ctrl_mem_walk.4280285652 |
| /workspace/coverage/default/11.sram_ctrl_multiple_keys.2658472367 |
| /workspace/coverage/default/11.sram_ctrl_partial_access.1631361321 |
| /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.3815456379 |
| /workspace/coverage/default/11.sram_ctrl_ram_cfg.2818539427 |
| /workspace/coverage/default/11.sram_ctrl_regwen.338698961 |
| /workspace/coverage/default/11.sram_ctrl_smoke.1605304111 |
| /workspace/coverage/default/11.sram_ctrl_stress_all.2029921509 |
| /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.550185016 |
| /workspace/coverage/default/11.sram_ctrl_stress_pipeline.3036325943 |
| /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.3265811895 |
| /workspace/coverage/default/12.sram_ctrl_access_during_key_req.3012520714 |
| /workspace/coverage/default/12.sram_ctrl_alert_test.3543705678 |
| /workspace/coverage/default/12.sram_ctrl_bijection.1011713154 |
| /workspace/coverage/default/12.sram_ctrl_executable.4197777192 |
| /workspace/coverage/default/12.sram_ctrl_lc_escalation.1355197135 |
| /workspace/coverage/default/12.sram_ctrl_max_throughput.4180950632 |
| /workspace/coverage/default/12.sram_ctrl_mem_partial_access.1078385198 |
| /workspace/coverage/default/12.sram_ctrl_mem_walk.1478646485 |
| /workspace/coverage/default/12.sram_ctrl_multiple_keys.3568048174 |
| /workspace/coverage/default/12.sram_ctrl_partial_access.3282749497 |
| /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.2864640815 |
| /workspace/coverage/default/12.sram_ctrl_ram_cfg.1260396875 |
| /workspace/coverage/default/12.sram_ctrl_regwen.1319265334 |
| /workspace/coverage/default/12.sram_ctrl_smoke.697577340 |
| /workspace/coverage/default/12.sram_ctrl_stress_all.90033631 |
| /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.2749248202 |
| /workspace/coverage/default/12.sram_ctrl_stress_pipeline.2503812552 |
| /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.1728847311 |
| /workspace/coverage/default/13.sram_ctrl_access_during_key_req.3289779609 |
| /workspace/coverage/default/13.sram_ctrl_alert_test.3582740119 |
| /workspace/coverage/default/13.sram_ctrl_bijection.2082635726 |
| /workspace/coverage/default/13.sram_ctrl_executable.4225355604 |
| /workspace/coverage/default/13.sram_ctrl_lc_escalation.2787593225 |
| /workspace/coverage/default/13.sram_ctrl_max_throughput.2684925285 |
| /workspace/coverage/default/13.sram_ctrl_mem_partial_access.3100030734 |
| /workspace/coverage/default/13.sram_ctrl_mem_walk.1051714047 |
| /workspace/coverage/default/13.sram_ctrl_multiple_keys.1048606722 |
| /workspace/coverage/default/13.sram_ctrl_partial_access.3389846048 |
| /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.671232588 |
| /workspace/coverage/default/13.sram_ctrl_regwen.1747403107 |
| /workspace/coverage/default/13.sram_ctrl_smoke.817876085 |
| /workspace/coverage/default/13.sram_ctrl_stress_all.1664244118 |
| /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.1890762175 |
| /workspace/coverage/default/13.sram_ctrl_stress_pipeline.2327473770 |
| /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.3070394820 |
| /workspace/coverage/default/14.sram_ctrl_access_during_key_req.3732857703 |
| /workspace/coverage/default/14.sram_ctrl_alert_test.2289391087 |
| /workspace/coverage/default/14.sram_ctrl_bijection.1445481013 |
| /workspace/coverage/default/14.sram_ctrl_executable.3908766678 |
| /workspace/coverage/default/14.sram_ctrl_lc_escalation.842373717 |
| /workspace/coverage/default/14.sram_ctrl_max_throughput.801029943 |
| /workspace/coverage/default/14.sram_ctrl_mem_partial_access.1500057071 |
| /workspace/coverage/default/14.sram_ctrl_mem_walk.3090686344 |
| /workspace/coverage/default/14.sram_ctrl_multiple_keys.2375535915 |
| /workspace/coverage/default/14.sram_ctrl_partial_access.3172676159 |
| /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.3271596273 |
| /workspace/coverage/default/14.sram_ctrl_ram_cfg.2971042242 |
| /workspace/coverage/default/14.sram_ctrl_regwen.2542731143 |
| /workspace/coverage/default/14.sram_ctrl_smoke.3683019745 |
| /workspace/coverage/default/14.sram_ctrl_stress_all.2694382013 |
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| /workspace/coverage/default/43.sram_ctrl_executable.183335723 |
| /workspace/coverage/default/43.sram_ctrl_lc_escalation.3464970028 |
| /workspace/coverage/default/43.sram_ctrl_max_throughput.1058444829 |
| /workspace/coverage/default/43.sram_ctrl_mem_partial_access.2580702488 |
| /workspace/coverage/default/43.sram_ctrl_mem_walk.3438637320 |
| /workspace/coverage/default/43.sram_ctrl_multiple_keys.2745708361 |
| /workspace/coverage/default/43.sram_ctrl_partial_access.3424091731 |
| /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.1698240634 |
| /workspace/coverage/default/43.sram_ctrl_ram_cfg.790539419 |
| /workspace/coverage/default/43.sram_ctrl_regwen.2223278712 |
| /workspace/coverage/default/43.sram_ctrl_smoke.519819636 |
| /workspace/coverage/default/43.sram_ctrl_stress_all.3154508826 |
| /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.1094038264 |
| /workspace/coverage/default/43.sram_ctrl_stress_pipeline.151872936 |
| /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.1236681933 |
| /workspace/coverage/default/44.sram_ctrl_access_during_key_req.3584547574 |
| /workspace/coverage/default/44.sram_ctrl_alert_test.2824977850 |
| /workspace/coverage/default/44.sram_ctrl_bijection.3834476771 |
| /workspace/coverage/default/44.sram_ctrl_executable.3916162863 |
| /workspace/coverage/default/44.sram_ctrl_lc_escalation.3824392576 |
| /workspace/coverage/default/44.sram_ctrl_max_throughput.1557086973 |
| /workspace/coverage/default/44.sram_ctrl_mem_partial_access.2147976956 |
| /workspace/coverage/default/44.sram_ctrl_mem_walk.3533368186 |
| /workspace/coverage/default/44.sram_ctrl_multiple_keys.834250261 |
| /workspace/coverage/default/44.sram_ctrl_partial_access.2025862878 |
| /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.2638682721 |
| /workspace/coverage/default/44.sram_ctrl_ram_cfg.3856942514 |
| /workspace/coverage/default/44.sram_ctrl_regwen.3084313992 |
| /workspace/coverage/default/44.sram_ctrl_smoke.3359069245 |
| /workspace/coverage/default/44.sram_ctrl_stress_all.294890058 |
| /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.3822370417 |
| /workspace/coverage/default/44.sram_ctrl_stress_pipeline.1051687715 |
| /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.1147821965 |
| /workspace/coverage/default/45.sram_ctrl_access_during_key_req.2256688583 |
| /workspace/coverage/default/45.sram_ctrl_alert_test.1673423361 |
| /workspace/coverage/default/45.sram_ctrl_bijection.3331396272 |
| /workspace/coverage/default/45.sram_ctrl_executable.2106192055 |
| /workspace/coverage/default/45.sram_ctrl_lc_escalation.1625513696 |
| /workspace/coverage/default/45.sram_ctrl_max_throughput.3049392954 |
| /workspace/coverage/default/45.sram_ctrl_mem_partial_access.3559592477 |
| /workspace/coverage/default/45.sram_ctrl_mem_walk.279189683 |
| /workspace/coverage/default/45.sram_ctrl_multiple_keys.189104975 |
| /workspace/coverage/default/45.sram_ctrl_partial_access.3636991069 |
| /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.2562387281 |
| /workspace/coverage/default/45.sram_ctrl_ram_cfg.1589540864 |
| /workspace/coverage/default/45.sram_ctrl_regwen.3416825103 |
| /workspace/coverage/default/45.sram_ctrl_smoke.2488575627 |
| /workspace/coverage/default/45.sram_ctrl_stress_all.1720842777 |
| /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.1752998132 |
| /workspace/coverage/default/45.sram_ctrl_stress_pipeline.3656811353 |
| /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.191168088 |
| /workspace/coverage/default/46.sram_ctrl_access_during_key_req.777294522 |
| /workspace/coverage/default/46.sram_ctrl_alert_test.2199932064 |
| /workspace/coverage/default/46.sram_ctrl_bijection.3945137320 |
| /workspace/coverage/default/46.sram_ctrl_executable.117555331 |
| /workspace/coverage/default/46.sram_ctrl_lc_escalation.509892823 |
| /workspace/coverage/default/46.sram_ctrl_max_throughput.1539749177 |
| /workspace/coverage/default/46.sram_ctrl_mem_partial_access.3452946470 |
| /workspace/coverage/default/46.sram_ctrl_mem_walk.3241371291 |
| /workspace/coverage/default/46.sram_ctrl_partial_access.3426961839 |
| /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.1022237060 |
| /workspace/coverage/default/46.sram_ctrl_ram_cfg.1617691814 |
| /workspace/coverage/default/46.sram_ctrl_regwen.1221596841 |
| /workspace/coverage/default/46.sram_ctrl_smoke.693646557 |
| /workspace/coverage/default/46.sram_ctrl_stress_all.303354912 |
| /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.1336148952 |
| /workspace/coverage/default/46.sram_ctrl_stress_pipeline.1539772759 |
| /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.644563544 |
| /workspace/coverage/default/47.sram_ctrl_access_during_key_req.3052741401 |
| /workspace/coverage/default/47.sram_ctrl_alert_test.270377268 |
| /workspace/coverage/default/47.sram_ctrl_bijection.948307344 |
| /workspace/coverage/default/47.sram_ctrl_executable.3792395075 |
| /workspace/coverage/default/47.sram_ctrl_lc_escalation.1296480321 |
| /workspace/coverage/default/47.sram_ctrl_max_throughput.3903613238 |
| /workspace/coverage/default/47.sram_ctrl_mem_partial_access.2392978066 |
| /workspace/coverage/default/47.sram_ctrl_mem_walk.284651811 |
| /workspace/coverage/default/47.sram_ctrl_multiple_keys.931119482 |
| /workspace/coverage/default/47.sram_ctrl_partial_access.381236157 |
| /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.1062536767 |
| /workspace/coverage/default/47.sram_ctrl_ram_cfg.2650161697 |
| /workspace/coverage/default/47.sram_ctrl_regwen.35332494 |
| /workspace/coverage/default/47.sram_ctrl_smoke.1501242211 |
| /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.4117516085 |
| /workspace/coverage/default/47.sram_ctrl_stress_pipeline.3185632659 |
| /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.300551386 |
| /workspace/coverage/default/48.sram_ctrl_access_during_key_req.2497424037 |
| /workspace/coverage/default/48.sram_ctrl_alert_test.1953219115 |
| /workspace/coverage/default/48.sram_ctrl_bijection.2932028276 |
| /workspace/coverage/default/48.sram_ctrl_executable.3291478942 |
| /workspace/coverage/default/48.sram_ctrl_lc_escalation.4165587576 |
| /workspace/coverage/default/48.sram_ctrl_max_throughput.1607338684 |
| /workspace/coverage/default/48.sram_ctrl_mem_partial_access.3794675461 |
| /workspace/coverage/default/48.sram_ctrl_mem_walk.2769177096 |
| /workspace/coverage/default/48.sram_ctrl_multiple_keys.3783431059 |
| /workspace/coverage/default/48.sram_ctrl_partial_access.2002613999 |
| /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.1226867540 |
| /workspace/coverage/default/48.sram_ctrl_ram_cfg.2092459871 |
| /workspace/coverage/default/48.sram_ctrl_regwen.1452538357 |
| /workspace/coverage/default/48.sram_ctrl_smoke.3249875261 |
| /workspace/coverage/default/48.sram_ctrl_stress_all.4115810706 |
| /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.3635709003 |
| /workspace/coverage/default/48.sram_ctrl_stress_pipeline.1153354000 |
| /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.1834883795 |
| /workspace/coverage/default/49.sram_ctrl_access_during_key_req.2856924072 |
| /workspace/coverage/default/49.sram_ctrl_alert_test.2720715078 |
| /workspace/coverage/default/49.sram_ctrl_bijection.2037728142 |
| /workspace/coverage/default/49.sram_ctrl_executable.439610675 |
| /workspace/coverage/default/49.sram_ctrl_lc_escalation.3507021150 |
| /workspace/coverage/default/49.sram_ctrl_max_throughput.1471500016 |
| /workspace/coverage/default/49.sram_ctrl_mem_partial_access.1153827453 |
| /workspace/coverage/default/49.sram_ctrl_mem_walk.3395911224 |
| /workspace/coverage/default/49.sram_ctrl_multiple_keys.821709902 |
| /workspace/coverage/default/49.sram_ctrl_partial_access.1237434738 |
| /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.3569344501 |
| /workspace/coverage/default/49.sram_ctrl_ram_cfg.1878196788 |
| /workspace/coverage/default/49.sram_ctrl_regwen.1769790687 |
| /workspace/coverage/default/49.sram_ctrl_smoke.3144770946 |
| /workspace/coverage/default/49.sram_ctrl_stress_all.3406633304 |
| /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1876225574 |
| /workspace/coverage/default/49.sram_ctrl_stress_pipeline.3282134525 |
| /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.3267056161 |
| /workspace/coverage/default/5.sram_ctrl_access_during_key_req.2287761528 |
| /workspace/coverage/default/5.sram_ctrl_alert_test.814965588 |
| /workspace/coverage/default/5.sram_ctrl_bijection.365948568 |
| /workspace/coverage/default/5.sram_ctrl_executable.290557252 |
| /workspace/coverage/default/5.sram_ctrl_lc_escalation.3687253900 |
| /workspace/coverage/default/5.sram_ctrl_max_throughput.2367856088 |
| /workspace/coverage/default/5.sram_ctrl_mem_partial_access.2752902737 |
| /workspace/coverage/default/5.sram_ctrl_mem_walk.2701515578 |
| /workspace/coverage/default/5.sram_ctrl_multiple_keys.2355927439 |
| /workspace/coverage/default/5.sram_ctrl_partial_access.812123896 |
| /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.3477502818 |
| /workspace/coverage/default/5.sram_ctrl_ram_cfg.3412457167 |
| /workspace/coverage/default/5.sram_ctrl_regwen.2364520512 |
| /workspace/coverage/default/5.sram_ctrl_smoke.2866284940 |
| /workspace/coverage/default/5.sram_ctrl_stress_all.357825492 |
| /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2647487935 |
| /workspace/coverage/default/5.sram_ctrl_stress_pipeline.3141030820 |
| /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.289271043 |
| /workspace/coverage/default/6.sram_ctrl_access_during_key_req.1856792333 |
| /workspace/coverage/default/6.sram_ctrl_alert_test.3506297921 |
| /workspace/coverage/default/6.sram_ctrl_bijection.1371179112 |
| /workspace/coverage/default/6.sram_ctrl_executable.3211577548 |
| /workspace/coverage/default/6.sram_ctrl_lc_escalation.3522380964 |
| /workspace/coverage/default/6.sram_ctrl_max_throughput.896628326 |
| /workspace/coverage/default/6.sram_ctrl_mem_partial_access.2793783322 |
| /workspace/coverage/default/6.sram_ctrl_mem_walk.1376747862 |
| /workspace/coverage/default/6.sram_ctrl_multiple_keys.3603074297 |
| /workspace/coverage/default/6.sram_ctrl_partial_access.3726711213 |
| /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.4270031328 |
| /workspace/coverage/default/6.sram_ctrl_ram_cfg.1468654290 |
| /workspace/coverage/default/6.sram_ctrl_regwen.433269868 |
| /workspace/coverage/default/6.sram_ctrl_smoke.456470446 |
| /workspace/coverage/default/6.sram_ctrl_stress_all.208866125 |
| /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.4004039033 |
| /workspace/coverage/default/6.sram_ctrl_stress_pipeline.2965495357 |
| /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.1916865328 |
| /workspace/coverage/default/7.sram_ctrl_access_during_key_req.2516888412 |
| /workspace/coverage/default/7.sram_ctrl_alert_test.2366860741 |
| /workspace/coverage/default/7.sram_ctrl_bijection.2913197594 |
| /workspace/coverage/default/7.sram_ctrl_executable.3398468862 |
| /workspace/coverage/default/7.sram_ctrl_lc_escalation.256075786 |
| /workspace/coverage/default/7.sram_ctrl_max_throughput.2071696154 |
| /workspace/coverage/default/7.sram_ctrl_mem_partial_access.1374121626 |
| /workspace/coverage/default/7.sram_ctrl_mem_walk.2462476215 |
| /workspace/coverage/default/7.sram_ctrl_multiple_keys.3952618538 |
| /workspace/coverage/default/7.sram_ctrl_partial_access.2787853637 |
| /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.3013557905 |
| /workspace/coverage/default/7.sram_ctrl_ram_cfg.2732425141 |
| /workspace/coverage/default/7.sram_ctrl_regwen.2101426170 |
| /workspace/coverage/default/7.sram_ctrl_smoke.889157825 |
| /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.299111753 |
| /workspace/coverage/default/7.sram_ctrl_stress_pipeline.4276414284 |
| /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.1171948222 |
| /workspace/coverage/default/8.sram_ctrl_access_during_key_req.2627946048 |
| /workspace/coverage/default/8.sram_ctrl_alert_test.2056804014 |
| /workspace/coverage/default/8.sram_ctrl_executable.2638145953 |
| /workspace/coverage/default/8.sram_ctrl_lc_escalation.530884111 |
| /workspace/coverage/default/8.sram_ctrl_max_throughput.854887063 |
| /workspace/coverage/default/8.sram_ctrl_mem_partial_access.3994236360 |
| /workspace/coverage/default/8.sram_ctrl_mem_walk.1475025253 |
| /workspace/coverage/default/8.sram_ctrl_multiple_keys.46199859 |
| /workspace/coverage/default/8.sram_ctrl_partial_access.2333369974 |
| /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.3487410332 |
| /workspace/coverage/default/8.sram_ctrl_ram_cfg.3154885403 |
| /workspace/coverage/default/8.sram_ctrl_regwen.1044430869 |
| /workspace/coverage/default/8.sram_ctrl_smoke.3735459743 |
| /workspace/coverage/default/8.sram_ctrl_stress_all.292482465 |
| /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.224521188 |
| /workspace/coverage/default/8.sram_ctrl_stress_pipeline.1916113436 |
| /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.1764561448 |
| /workspace/coverage/default/9.sram_ctrl_access_during_key_req.1241887153 |
| /workspace/coverage/default/9.sram_ctrl_alert_test.464745886 |
| /workspace/coverage/default/9.sram_ctrl_bijection.3945060455 |
| /workspace/coverage/default/9.sram_ctrl_executable.2200050327 |
| /workspace/coverage/default/9.sram_ctrl_lc_escalation.415947743 |
| /workspace/coverage/default/9.sram_ctrl_max_throughput.3074691081 |
| /workspace/coverage/default/9.sram_ctrl_mem_partial_access.1404573212 |
| /workspace/coverage/default/9.sram_ctrl_mem_walk.3135116665 |
| /workspace/coverage/default/9.sram_ctrl_multiple_keys.668740219 |
| /workspace/coverage/default/9.sram_ctrl_partial_access.2666182007 |
| /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.2985818737 |
| /workspace/coverage/default/9.sram_ctrl_ram_cfg.1372237672 |
| /workspace/coverage/default/9.sram_ctrl_regwen.2101817504 |
| /workspace/coverage/default/9.sram_ctrl_smoke.865598319 |
| /workspace/coverage/default/9.sram_ctrl_stress_all.2279103735 |
| /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.2730505537 |
| /workspace/coverage/default/9.sram_ctrl_stress_pipeline.3122257821 |
| /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.2143437459 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
| T1 |
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2020994162 |
|
|
Jul 18 07:11:52 PM PDT 24 |
Jul 18 07:15:04 PM PDT 24 |
31469888862 ps |
| T2 |
/workspace/coverage/default/24.sram_ctrl_partial_access.2628988313 |
|
|
Jul 18 07:14:41 PM PDT 24 |
Jul 18 07:14:58 PM PDT 24 |
964654595 ps |
| T3 |
/workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.579230445 |
|
|
Jul 18 07:14:38 PM PDT 24 |
Jul 18 07:14:58 PM PDT 24 |
2701092448 ps |
| T4 |
/workspace/coverage/default/24.sram_ctrl_multiple_keys.3552686878 |
|
|
Jul 18 07:14:38 PM PDT 24 |
Jul 18 07:28:21 PM PDT 24 |
25709344943 ps |
| T8 |
/workspace/coverage/default/29.sram_ctrl_mem_partial_access.2038522625 |
|
|
Jul 18 07:15:59 PM PDT 24 |
Jul 18 07:17:06 PM PDT 24 |
3550910033 ps |
| T9 |
/workspace/coverage/default/31.sram_ctrl_mem_walk.654292146 |
|
|
Jul 18 07:16:29 PM PDT 24 |
Jul 18 07:19:12 PM PDT 24 |
6917572852 ps |
| T10 |
/workspace/coverage/default/11.sram_ctrl_mem_walk.4280285652 |
|
|
Jul 18 07:11:44 PM PDT 24 |
Jul 18 07:16:59 PM PDT 24 |
5712151114 ps |
| T5 |
/workspace/coverage/default/7.sram_ctrl_stress_all.153812998 |
|
|
Jul 18 07:11:40 PM PDT 24 |
Jul 18 07:52:59 PM PDT 24 |
60093525213 ps |
| T11 |
/workspace/coverage/default/9.sram_ctrl_regwen.2101817504 |
|
|
Jul 18 07:11:47 PM PDT 24 |
Jul 18 07:12:29 PM PDT 24 |
3663990010 ps |
| T12 |
/workspace/coverage/default/12.sram_ctrl_multiple_keys.3568048174 |
|
|
Jul 18 07:12:12 PM PDT 24 |
Jul 18 07:25:38 PM PDT 24 |
4914966654 ps |
| T44 |
/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.3578247519 |
|
|
Jul 18 07:15:11 PM PDT 24 |
Jul 18 07:15:53 PM PDT 24 |
732996175 ps |
| T25 |
/workspace/coverage/default/10.sram_ctrl_executable.3024793743 |
|
|
Jul 18 07:11:42 PM PDT 24 |
Jul 18 07:23:56 PM PDT 24 |
29368631604 ps |
| T50 |
/workspace/coverage/default/42.sram_ctrl_stress_pipeline.303974775 |
|
|
Jul 18 07:19:04 PM PDT 24 |
Jul 18 07:25:14 PM PDT 24 |
22589615357 ps |
| T53 |
/workspace/coverage/default/15.sram_ctrl_multiple_keys.4055349252 |
|
|
Jul 18 07:12:56 PM PDT 24 |
Jul 18 07:35:26 PM PDT 24 |
6925979378 ps |
| T6 |
/workspace/coverage/default/45.sram_ctrl_lc_escalation.1625513696 |
|
|
Jul 18 07:20:00 PM PDT 24 |
Jul 18 07:21:07 PM PDT 24 |
20703870183 ps |
| T39 |
/workspace/coverage/default/13.sram_ctrl_partial_access.3389846048 |
|
|
Jul 18 07:12:14 PM PDT 24 |
Jul 18 07:12:28 PM PDT 24 |
2448231179 ps |
| T27 |
/workspace/coverage/default/4.sram_ctrl_ram_cfg.2530720430 |
|
|
Jul 18 07:11:05 PM PDT 24 |
Jul 18 07:11:11 PM PDT 24 |
1402731215 ps |
| T40 |
/workspace/coverage/default/32.sram_ctrl_access_during_key_req.2701401318 |
|
|
Jul 18 07:16:48 PM PDT 24 |
Jul 18 07:26:05 PM PDT 24 |
42040401799 ps |
| T81 |
/workspace/coverage/default/39.sram_ctrl_stress_pipeline.1350225731 |
|
|
Jul 18 07:18:10 PM PDT 24 |
Jul 18 07:23:30 PM PDT 24 |
19788866187 ps |
| T23 |
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.3496118349 |
|
|
Jul 18 07:19:19 PM PDT 24 |
Jul 18 07:20:39 PM PDT 24 |
1641500193 ps |
| T26 |
/workspace/coverage/default/17.sram_ctrl_executable.3543385178 |
|
|
Jul 18 07:12:55 PM PDT 24 |
Jul 18 07:23:18 PM PDT 24 |
14677166447 ps |
| T58 |
/workspace/coverage/default/2.sram_ctrl_stress_pipeline.2873649326 |
|
|
Jul 18 07:10:20 PM PDT 24 |
Jul 18 07:15:33 PM PDT 24 |
9047950024 ps |
| T7 |
/workspace/coverage/default/19.sram_ctrl_stress_all.1249992044 |
|
|
Jul 18 07:13:34 PM PDT 24 |
Jul 18 08:36:20 PM PDT 24 |
162169350980 ps |
| T59 |
/workspace/coverage/default/44.sram_ctrl_multiple_keys.834250261 |
|
|
Jul 18 07:19:45 PM PDT 24 |
Jul 18 07:33:32 PM PDT 24 |
6611000541 ps |
| T24 |
/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.2906986526 |
|
|
Jul 18 07:16:47 PM PDT 24 |
Jul 18 07:17:17 PM PDT 24 |
3846408803 ps |
| T41 |
/workspace/coverage/default/36.sram_ctrl_access_during_key_req.463412538 |
|
|
Jul 18 07:17:55 PM PDT 24 |
Jul 18 07:42:13 PM PDT 24 |
60437083261 ps |
| T60 |
/workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.3326598908 |
|
|
Jul 18 07:14:38 PM PDT 24 |
Jul 18 07:16:03 PM PDT 24 |
798378431 ps |
| T47 |
/workspace/coverage/default/15.sram_ctrl_mem_partial_access.3544470267 |
|
|
Jul 18 07:12:57 PM PDT 24 |
Jul 18 07:15:44 PM PDT 24 |
5620667096 ps |
| T61 |
/workspace/coverage/default/13.sram_ctrl_partial_access_b2b.671232588 |
|
|
Jul 18 07:12:13 PM PDT 24 |
Jul 18 07:17:21 PM PDT 24 |
5482700543 ps |
| T135 |
/workspace/coverage/default/4.sram_ctrl_smoke.3630585865 |
|
|
Jul 18 07:11:02 PM PDT 24 |
Jul 18 07:11:10 PM PDT 24 |
2856897615 ps |
| T136 |
/workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.3309620901 |
|
|
Jul 18 07:16:14 PM PDT 24 |
Jul 18 07:16:52 PM PDT 24 |
741004244 ps |
| T137 |
/workspace/coverage/default/15.sram_ctrl_partial_access.2443219669 |
|
|
Jul 18 07:12:55 PM PDT 24 |
Jul 18 07:13:09 PM PDT 24 |
1959259322 ps |
| T20 |
/workspace/coverage/default/9.sram_ctrl_stress_all.2279103735 |
|
|
Jul 18 07:11:49 PM PDT 24 |
Jul 18 07:25:28 PM PDT 24 |
112835215478 ps |
| T138 |
/workspace/coverage/default/47.sram_ctrl_partial_access.381236157 |
|
|
Jul 18 07:20:30 PM PDT 24 |
Jul 18 07:20:45 PM PDT 24 |
3148311267 ps |
| T139 |
/workspace/coverage/default/8.sram_ctrl_max_throughput.854887063 |
|
|
Jul 18 07:11:49 PM PDT 24 |
Jul 18 07:12:19 PM PDT 24 |
3199336536 ps |
| T140 |
/workspace/coverage/default/13.sram_ctrl_bijection.2082635726 |
|
|
Jul 18 07:12:12 PM PDT 24 |
Jul 18 07:57:42 PM PDT 24 |
526196206545 ps |
| T134 |
/workspace/coverage/default/1.sram_ctrl_multiple_keys.1772327035 |
|
|
Jul 18 07:10:15 PM PDT 24 |
Jul 18 07:12:05 PM PDT 24 |
19340327304 ps |
| T43 |
/workspace/coverage/default/31.sram_ctrl_executable.1586543148 |
|
|
Jul 18 07:16:28 PM PDT 24 |
Jul 18 07:19:37 PM PDT 24 |
8077421360 ps |
| T87 |
/workspace/coverage/default/39.sram_ctrl_mem_partial_access.5511473 |
|
|
Jul 18 07:18:27 PM PDT 24 |
Jul 18 07:19:41 PM PDT 24 |
4012531783 ps |
| T16 |
/workspace/coverage/default/0.sram_ctrl_sec_cm.2377070271 |
|
|
Jul 18 07:10:16 PM PDT 24 |
Jul 18 07:10:25 PM PDT 24 |
384496765 ps |
| T32 |
/workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.2274999937 |
|
|
Jul 18 07:17:29 PM PDT 24 |
Jul 18 07:19:52 PM PDT 24 |
6525106530 ps |
| T33 |
/workspace/coverage/default/28.sram_ctrl_partial_access_b2b.3306123703 |
|
|
Jul 18 07:15:46 PM PDT 24 |
Jul 18 07:22:21 PM PDT 24 |
17466043370 ps |
| T34 |
/workspace/coverage/default/27.sram_ctrl_partial_access_b2b.3811614640 |
|
|
Jul 18 07:15:21 PM PDT 24 |
Jul 18 07:17:32 PM PDT 24 |
34916082620 ps |
| T35 |
/workspace/coverage/default/18.sram_ctrl_partial_access_b2b.1680048846 |
|
|
Jul 18 07:13:34 PM PDT 24 |
Jul 18 07:19:37 PM PDT 24 |
15534177733 ps |
| T36 |
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.1404573212 |
|
|
Jul 18 07:11:48 PM PDT 24 |
Jul 18 07:13:17 PM PDT 24 |
6399597747 ps |
| T28 |
/workspace/coverage/default/48.sram_ctrl_ram_cfg.2092459871 |
|
|
Jul 18 07:20:45 PM PDT 24 |
Jul 18 07:20:52 PM PDT 24 |
1406469614 ps |
| T37 |
/workspace/coverage/default/35.sram_ctrl_bijection.1803270306 |
|
|
Jul 18 07:17:14 PM PDT 24 |
Jul 18 07:43:14 PM PDT 24 |
44904538962 ps |
| T38 |
/workspace/coverage/default/4.sram_ctrl_mem_walk.3720572584 |
|
|
Jul 18 07:11:03 PM PDT 24 |
Jul 18 07:17:19 PM PDT 24 |
42239089968 ps |
| T21 |
/workspace/coverage/default/6.sram_ctrl_lc_escalation.3522380964 |
|
|
Jul 18 07:11:07 PM PDT 24 |
Jul 18 07:12:32 PM PDT 24 |
70580143519 ps |
| T71 |
/workspace/coverage/default/24.sram_ctrl_lc_escalation.1804787480 |
|
|
Jul 18 07:14:52 PM PDT 24 |
Jul 18 07:15:46 PM PDT 24 |
24766909145 ps |
| T51 |
/workspace/coverage/default/30.sram_ctrl_mem_walk.649017779 |
|
|
Jul 18 07:16:14 PM PDT 24 |
Jul 18 07:18:53 PM PDT 24 |
2772501617 ps |
| T52 |
/workspace/coverage/default/31.sram_ctrl_mem_partial_access.365518900 |
|
|
Jul 18 07:16:28 PM PDT 24 |
Jul 18 07:18:53 PM PDT 24 |
4946821893 ps |
| T133 |
/workspace/coverage/default/39.sram_ctrl_partial_access_b2b.1007412655 |
|
|
Jul 18 07:18:11 PM PDT 24 |
Jul 18 07:24:31 PM PDT 24 |
33775226324 ps |
| T141 |
/workspace/coverage/default/24.sram_ctrl_partial_access_b2b.150487694 |
|
|
Jul 18 07:14:36 PM PDT 24 |
Jul 18 07:18:10 PM PDT 24 |
8308240201 ps |
| T65 |
/workspace/coverage/default/33.sram_ctrl_regwen.921650906 |
|
|
Jul 18 07:16:47 PM PDT 24 |
Jul 18 07:25:43 PM PDT 24 |
12505872203 ps |
| T142 |
/workspace/coverage/default/30.sram_ctrl_bijection.2747115923 |
|
|
Jul 18 07:15:59 PM PDT 24 |
Jul 18 07:42:40 PM PDT 24 |
46255240234 ps |
| T42 |
/workspace/coverage/default/17.sram_ctrl_access_during_key_req.2704694533 |
|
|
Jul 18 07:12:57 PM PDT 24 |
Jul 18 07:18:54 PM PDT 24 |
26379914667 ps |
| T143 |
/workspace/coverage/default/30.sram_ctrl_multiple_keys.2413485152 |
|
|
Jul 18 07:15:57 PM PDT 24 |
Jul 18 07:30:31 PM PDT 24 |
6600363029 ps |
| T144 |
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.300551386 |
|
|
Jul 18 07:20:30 PM PDT 24 |
Jul 18 07:20:49 PM PDT 24 |
1438582511 ps |
| T13 |
/workspace/coverage/default/11.sram_ctrl_alert_test.703612763 |
|
|
Jul 18 07:11:44 PM PDT 24 |
Jul 18 07:11:47 PM PDT 24 |
22275377 ps |
| T14 |
/workspace/coverage/default/9.sram_ctrl_alert_test.464745886 |
|
|
Jul 18 07:11:48 PM PDT 24 |
Jul 18 07:11:53 PM PDT 24 |
16081935 ps |
| T29 |
/workspace/coverage/default/26.sram_ctrl_ram_cfg.55902191 |
|
|
Jul 18 07:15:08 PM PDT 24 |
Jul 18 07:15:13 PM PDT 24 |
696418837 ps |
| T126 |
/workspace/coverage/default/6.sram_ctrl_executable.3211577548 |
|
|
Jul 18 07:11:09 PM PDT 24 |
Jul 18 07:28:17 PM PDT 24 |
14737941217 ps |
| T15 |
/workspace/coverage/default/23.sram_ctrl_alert_test.300219883 |
|
|
Jul 18 07:14:38 PM PDT 24 |
Jul 18 07:14:41 PM PDT 24 |
14062321 ps |
| T145 |
/workspace/coverage/default/2.sram_ctrl_ram_cfg.3785968201 |
|
|
Jul 18 07:10:16 PM PDT 24 |
Jul 18 07:10:25 PM PDT 24 |
738606044 ps |
| T146 |
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2370213097 |
|
|
Jul 18 07:10:17 PM PDT 24 |
Jul 18 07:22:35 PM PDT 24 |
117903871446 ps |
| T147 |
/workspace/coverage/default/28.sram_ctrl_max_throughput.1070118966 |
|
|
Jul 18 07:15:41 PM PDT 24 |
Jul 18 07:16:17 PM PDT 24 |
2168933892 ps |
| T48 |
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.3822370417 |
|
|
Jul 18 07:19:50 PM PDT 24 |
Jul 18 07:20:22 PM PDT 24 |
1100709847 ps |
| T148 |
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.3013557905 |
|
|
Jul 18 07:11:40 PM PDT 24 |
Jul 18 07:16:52 PM PDT 24 |
79256467986 ps |
| T149 |
/workspace/coverage/default/41.sram_ctrl_multiple_keys.1415835091 |
|
|
Jul 18 07:18:43 PM PDT 24 |
Jul 18 07:19:32 PM PDT 24 |
13967967637 ps |
| T150 |
/workspace/coverage/default/26.sram_ctrl_bijection.174148004 |
|
|
Jul 18 07:15:09 PM PDT 24 |
Jul 18 07:43:50 PM PDT 24 |
384368423055 ps |
| T151 |
/workspace/coverage/default/22.sram_ctrl_partial_access.2789948262 |
|
|
Jul 18 07:14:09 PM PDT 24 |
Jul 18 07:15:33 PM PDT 24 |
1136613731 ps |
| T49 |
/workspace/coverage/default/38.sram_ctrl_mem_partial_access.331070156 |
|
|
Jul 18 07:18:14 PM PDT 24 |
Jul 18 07:19:45 PM PDT 24 |
3070016639 ps |
| T68 |
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.3360318077 |
|
|
Jul 18 07:10:16 PM PDT 24 |
Jul 18 07:10:30 PM PDT 24 |
254650986 ps |
| T152 |
/workspace/coverage/default/13.sram_ctrl_ram_cfg.1789478481 |
|
|
Jul 18 07:12:14 PM PDT 24 |
Jul 18 07:12:20 PM PDT 24 |
831031041 ps |
| T72 |
/workspace/coverage/default/32.sram_ctrl_lc_escalation.2221036358 |
|
|
Jul 18 07:16:32 PM PDT 24 |
Jul 18 07:16:58 PM PDT 24 |
7357867950 ps |
| T128 |
/workspace/coverage/default/28.sram_ctrl_executable.1411121721 |
|
|
Jul 18 07:15:40 PM PDT 24 |
Jul 18 07:26:22 PM PDT 24 |
9246359794 ps |
| T127 |
/workspace/coverage/default/5.sram_ctrl_executable.290557252 |
|
|
Jul 18 07:11:03 PM PDT 24 |
Jul 18 07:24:01 PM PDT 24 |
11812880088 ps |
| T153 |
/workspace/coverage/default/35.sram_ctrl_smoke.1031290637 |
|
|
Jul 18 07:17:19 PM PDT 24 |
Jul 18 07:17:41 PM PDT 24 |
5309868163 ps |
| T154 |
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2654237036 |
|
|
Jul 18 07:11:52 PM PDT 24 |
Jul 18 07:13:57 PM PDT 24 |
1613894694 ps |
| T155 |
/workspace/coverage/default/42.sram_ctrl_bijection.1494733660 |
|
|
Jul 18 07:18:59 PM PDT 24 |
Jul 18 07:26:47 PM PDT 24 |
36295524537 ps |
| T88 |
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.2287761528 |
|
|
Jul 18 07:11:05 PM PDT 24 |
Jul 18 07:29:29 PM PDT 24 |
59989922910 ps |
| T156 |
/workspace/coverage/default/16.sram_ctrl_mem_walk.1399794940 |
|
|
Jul 18 07:12:56 PM PDT 24 |
Jul 18 07:15:47 PM PDT 24 |
10325713426 ps |
| T157 |
/workspace/coverage/default/31.sram_ctrl_stress_pipeline.3830221083 |
|
|
Jul 18 07:16:16 PM PDT 24 |
Jul 18 07:22:25 PM PDT 24 |
22471109920 ps |
| T158 |
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.3122257821 |
|
|
Jul 18 07:11:43 PM PDT 24 |
Jul 18 07:16:35 PM PDT 24 |
16103227379 ps |
| T159 |
/workspace/coverage/default/35.sram_ctrl_partial_access_b2b.1474196677 |
|
|
Jul 18 07:17:15 PM PDT 24 |
Jul 18 07:23:18 PM PDT 24 |
16411061835 ps |
| T19 |
/workspace/coverage/default/40.sram_ctrl_stress_all.3484606826 |
|
|
Jul 18 07:18:41 PM PDT 24 |
Jul 18 09:16:41 PM PDT 24 |
654910833596 ps |
| T160 |
/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.497523834 |
|
|
Jul 18 07:14:09 PM PDT 24 |
Jul 18 07:16:37 PM PDT 24 |
3217510176 ps |
| T161 |
/workspace/coverage/default/13.sram_ctrl_alert_test.3582740119 |
|
|
Jul 18 07:12:19 PM PDT 24 |
Jul 18 07:12:21 PM PDT 24 |
27664708 ps |
| T69 |
/workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.2463747938 |
|
|
Jul 18 07:11:03 PM PDT 24 |
Jul 18 07:11:12 PM PDT 24 |
410758133 ps |
| T162 |
/workspace/coverage/default/23.sram_ctrl_bijection.769876222 |
|
|
Jul 18 07:14:22 PM PDT 24 |
Jul 18 07:36:06 PM PDT 24 |
141102809761 ps |
| T54 |
/workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.13410056 |
|
|
Jul 18 07:18:29 PM PDT 24 |
Jul 18 07:20:30 PM PDT 24 |
2015447932 ps |
| T131 |
/workspace/coverage/default/24.sram_ctrl_regwen.2703508457 |
|
|
Jul 18 07:14:51 PM PDT 24 |
Jul 18 07:33:41 PM PDT 24 |
57687726630 ps |
| T163 |
/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.4228483268 |
|
|
Jul 18 07:15:58 PM PDT 24 |
Jul 18 07:16:47 PM PDT 24 |
3019575562 ps |
| T17 |
/workspace/coverage/default/1.sram_ctrl_sec_cm.2151412687 |
|
|
Jul 18 07:10:19 PM PDT 24 |
Jul 18 07:10:29 PM PDT 24 |
1294029107 ps |
| T164 |
/workspace/coverage/default/8.sram_ctrl_ram_cfg.3154885403 |
|
|
Jul 18 07:11:42 PM PDT 24 |
Jul 18 07:11:47 PM PDT 24 |
354040803 ps |
| T165 |
/workspace/coverage/default/11.sram_ctrl_multiple_keys.2658472367 |
|
|
Jul 18 07:11:53 PM PDT 24 |
Jul 18 07:22:35 PM PDT 24 |
38892700595 ps |
| T166 |
/workspace/coverage/default/32.sram_ctrl_bijection.3505084496 |
|
|
Jul 18 07:16:29 PM PDT 24 |
Jul 18 07:53:36 PM PDT 24 |
127874835333 ps |
| T167 |
/workspace/coverage/default/30.sram_ctrl_alert_test.1714325131 |
|
|
Jul 18 07:16:16 PM PDT 24 |
Jul 18 07:16:17 PM PDT 24 |
14136198 ps |
| T99 |
/workspace/coverage/default/41.sram_ctrl_access_during_key_req.1799813462 |
|
|
Jul 18 07:19:04 PM PDT 24 |
Jul 18 07:27:08 PM PDT 24 |
30452096042 ps |
| T132 |
/workspace/coverage/default/16.sram_ctrl_executable.4263080020 |
|
|
Jul 18 07:12:56 PM PDT 24 |
Jul 18 07:33:13 PM PDT 24 |
21392919239 ps |
| T100 |
/workspace/coverage/default/2.sram_ctrl_mem_partial_access.1869439794 |
|
|
Jul 18 07:10:20 PM PDT 24 |
Jul 18 07:11:32 PM PDT 24 |
3709160053 ps |
| T22 |
/workspace/coverage/default/13.sram_ctrl_stress_all.1664244118 |
|
|
Jul 18 07:12:19 PM PDT 24 |
Jul 18 08:57:07 PM PDT 24 |
319051893061 ps |
| T168 |
/workspace/coverage/default/23.sram_ctrl_partial_access.97252483 |
|
|
Jul 18 07:14:40 PM PDT 24 |
Jul 18 07:17:16 PM PDT 24 |
2581860038 ps |
| T169 |
/workspace/coverage/default/11.sram_ctrl_executable.2430493115 |
|
|
Jul 18 07:11:46 PM PDT 24 |
Jul 18 07:21:07 PM PDT 24 |
5381958171 ps |
| T170 |
/workspace/coverage/default/21.sram_ctrl_ram_cfg.1191938836 |
|
|
Jul 18 07:14:15 PM PDT 24 |
Jul 18 07:14:21 PM PDT 24 |
376589581 ps |
| T171 |
/workspace/coverage/default/5.sram_ctrl_ram_cfg.3412457167 |
|
|
Jul 18 07:11:03 PM PDT 24 |
Jul 18 07:11:09 PM PDT 24 |
696702513 ps |
| T172 |
/workspace/coverage/default/16.sram_ctrl_access_during_key_req.1109499730 |
|
|
Jul 18 07:12:56 PM PDT 24 |
Jul 18 07:36:28 PM PDT 24 |
98839244024 ps |
| T173 |
/workspace/coverage/default/9.sram_ctrl_partial_access.2666182007 |
|
|
Jul 18 07:11:49 PM PDT 24 |
Jul 18 07:12:11 PM PDT 24 |
3926240907 ps |
| T174 |
/workspace/coverage/default/32.sram_ctrl_max_throughput.1996410490 |
|
|
Jul 18 07:16:31 PM PDT 24 |
Jul 18 07:17:34 PM PDT 24 |
2971913896 ps |
| T175 |
/workspace/coverage/default/35.sram_ctrl_executable.675120646 |
|
|
Jul 18 07:17:15 PM PDT 24 |
Jul 18 07:32:33 PM PDT 24 |
10056846806 ps |
| T176 |
/workspace/coverage/default/12.sram_ctrl_regwen.1319265334 |
|
|
Jul 18 07:12:11 PM PDT 24 |
Jul 18 07:26:18 PM PDT 24 |
3527141034 ps |
| T55 |
/workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.2132344705 |
|
|
Jul 18 07:16:14 PM PDT 24 |
Jul 18 07:21:24 PM PDT 24 |
1695225471 ps |
| T177 |
/workspace/coverage/default/41.sram_ctrl_lc_escalation.2427459150 |
|
|
Jul 18 07:18:42 PM PDT 24 |
Jul 18 07:20:16 PM PDT 24 |
51047329684 ps |
| T178 |
/workspace/coverage/default/25.sram_ctrl_alert_test.2506221294 |
|
|
Jul 18 07:15:08 PM PDT 24 |
Jul 18 07:15:10 PM PDT 24 |
22680219 ps |
| T179 |
/workspace/coverage/default/38.sram_ctrl_bijection.1042311350 |
|
|
Jul 18 07:18:10 PM PDT 24 |
Jul 18 07:41:46 PM PDT 24 |
74858117697 ps |
| T180 |
/workspace/coverage/default/28.sram_ctrl_ram_cfg.2706085333 |
|
|
Jul 18 07:15:40 PM PDT 24 |
Jul 18 07:15:44 PM PDT 24 |
429709327 ps |
| T181 |
/workspace/coverage/default/12.sram_ctrl_smoke.697577340 |
|
|
Jul 18 07:11:49 PM PDT 24 |
Jul 18 07:12:08 PM PDT 24 |
3574774898 ps |
| T182 |
/workspace/coverage/default/43.sram_ctrl_smoke.519819636 |
|
|
Jul 18 07:19:18 PM PDT 24 |
Jul 18 07:19:24 PM PDT 24 |
389600744 ps |
| T183 |
/workspace/coverage/default/36.sram_ctrl_partial_access.1215115428 |
|
|
Jul 18 07:17:30 PM PDT 24 |
Jul 18 07:17:48 PM PDT 24 |
1707930967 ps |
| T184 |
/workspace/coverage/default/49.sram_ctrl_executable.439610675 |
|
|
Jul 18 07:21:02 PM PDT 24 |
Jul 18 07:43:28 PM PDT 24 |
52519853872 ps |
| T185 |
/workspace/coverage/default/5.sram_ctrl_alert_test.814965588 |
|
|
Jul 18 07:11:03 PM PDT 24 |
Jul 18 07:11:07 PM PDT 24 |
10918305 ps |
| T70 |
/workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.3159569923 |
|
|
Jul 18 07:18:43 PM PDT 24 |
Jul 18 07:19:13 PM PDT 24 |
3058483415 ps |
| T186 |
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.1916113436 |
|
|
Jul 18 07:11:42 PM PDT 24 |
Jul 18 07:14:14 PM PDT 24 |
4755660537 ps |
| T187 |
/workspace/coverage/default/49.sram_ctrl_max_throughput.1471500016 |
|
|
Jul 18 07:21:02 PM PDT 24 |
Jul 18 07:22:41 PM PDT 24 |
789634368 ps |
| T56 |
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.1336148952 |
|
|
Jul 18 07:20:13 PM PDT 24 |
Jul 18 07:22:30 PM PDT 24 |
2899998888 ps |
| T188 |
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.2752902737 |
|
|
Jul 18 07:11:08 PM PDT 24 |
Jul 18 07:12:28 PM PDT 24 |
9827383470 ps |
| T189 |
/workspace/coverage/default/20.sram_ctrl_smoke.1900272203 |
|
|
Jul 18 07:13:54 PM PDT 24 |
Jul 18 07:15:53 PM PDT 24 |
1277266365 ps |
| T190 |
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.1765292749 |
|
|
Jul 18 07:10:12 PM PDT 24 |
Jul 18 07:13:55 PM PDT 24 |
3634996141 ps |
| T191 |
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.3487410332 |
|
|
Jul 18 07:11:42 PM PDT 24 |
Jul 18 07:14:59 PM PDT 24 |
7718452481 ps |
| T130 |
/workspace/coverage/default/30.sram_ctrl_stress_all.3222265631 |
|
|
Jul 18 07:16:24 PM PDT 24 |
Jul 18 09:00:04 PM PDT 24 |
157397203531 ps |
| T192 |
/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.1132631488 |
|
|
Jul 18 07:12:56 PM PDT 24 |
Jul 18 07:23:34 PM PDT 24 |
443018208796 ps |
| T193 |
/workspace/coverage/default/33.sram_ctrl_alert_test.2562213463 |
|
|
Jul 18 07:17:01 PM PDT 24 |
Jul 18 07:17:03 PM PDT 24 |
12574227 ps |
| T194 |
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.3584547574 |
|
|
Jul 18 07:19:45 PM PDT 24 |
Jul 18 07:46:48 PM PDT 24 |
59420636730 ps |
| T195 |
/workspace/coverage/default/24.sram_ctrl_ram_cfg.3228721185 |
|
|
Jul 18 07:14:55 PM PDT 24 |
Jul 18 07:15:00 PM PDT 24 |
2581562074 ps |
| T196 |
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.3036325943 |
|
|
Jul 18 07:11:47 PM PDT 24 |
Jul 18 07:15:15 PM PDT 24 |
7660339106 ps |
| T197 |
/workspace/coverage/default/40.sram_ctrl_smoke.2306275691 |
|
|
Jul 18 07:18:28 PM PDT 24 |
Jul 18 07:18:43 PM PDT 24 |
2477012679 ps |
| T198 |
/workspace/coverage/default/17.sram_ctrl_mem_walk.286683418 |
|
|
Jul 18 07:13:37 PM PDT 24 |
Jul 18 07:19:09 PM PDT 24 |
14408314133 ps |
| T199 |
/workspace/coverage/default/41.sram_ctrl_regwen.1582525448 |
|
|
Jul 18 07:18:57 PM PDT 24 |
Jul 18 07:26:37 PM PDT 24 |
11802669996 ps |
| T200 |
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.3185632659 |
|
|
Jul 18 07:20:29 PM PDT 24 |
Jul 18 07:25:41 PM PDT 24 |
10455302039 ps |
| T201 |
/workspace/coverage/default/15.sram_ctrl_lc_escalation.522799926 |
|
|
Jul 18 07:13:06 PM PDT 24 |
Jul 18 07:14:13 PM PDT 24 |
19472662951 ps |
| T202 |
/workspace/coverage/default/3.sram_ctrl_smoke.2266462142 |
|
|
Jul 18 07:10:18 PM PDT 24 |
Jul 18 07:10:36 PM PDT 24 |
1707702620 ps |
| T203 |
/workspace/coverage/default/7.sram_ctrl_lc_escalation.256075786 |
|
|
Jul 18 07:11:46 PM PDT 24 |
Jul 18 07:12:52 PM PDT 24 |
18280159812 ps |
| T204 |
/workspace/coverage/default/48.sram_ctrl_smoke.3249875261 |
|
|
Jul 18 07:20:32 PM PDT 24 |
Jul 18 07:20:54 PM PDT 24 |
1781573260 ps |
| T45 |
/workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.1096069085 |
|
|
Jul 18 07:18:12 PM PDT 24 |
Jul 18 07:19:32 PM PDT 24 |
18283230709 ps |
| T205 |
/workspace/coverage/default/29.sram_ctrl_stress_pipeline.1754418586 |
|
|
Jul 18 07:15:58 PM PDT 24 |
Jul 18 07:19:40 PM PDT 24 |
14746817168 ps |
| T206 |
/workspace/coverage/default/39.sram_ctrl_ram_cfg.3879497687 |
|
|
Jul 18 07:18:25 PM PDT 24 |
Jul 18 07:18:30 PM PDT 24 |
352366872 ps |
| T207 |
/workspace/coverage/default/48.sram_ctrl_multiple_keys.3783431059 |
|
|
Jul 18 07:20:33 PM PDT 24 |
Jul 18 07:40:22 PM PDT 24 |
49536377866 ps |
| T208 |
/workspace/coverage/default/31.sram_ctrl_bijection.1782640924 |
|
|
Jul 18 07:16:20 PM PDT 24 |
Jul 18 07:51:18 PM PDT 24 |
518506633516 ps |
| T209 |
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.2516888412 |
|
|
Jul 18 07:11:44 PM PDT 24 |
Jul 18 07:34:03 PM PDT 24 |
14983922069 ps |
| T210 |
/workspace/coverage/default/12.sram_ctrl_lc_escalation.1355197135 |
|
|
Jul 18 07:12:11 PM PDT 24 |
Jul 18 07:13:07 PM PDT 24 |
8510271092 ps |
| T211 |
/workspace/coverage/default/30.sram_ctrl_regwen.3335753861 |
|
|
Jul 18 07:16:14 PM PDT 24 |
Jul 18 07:24:41 PM PDT 24 |
18286475124 ps |
| T212 |
/workspace/coverage/default/17.sram_ctrl_alert_test.4261502431 |
|
|
Jul 18 07:13:37 PM PDT 24 |
Jul 18 07:13:39 PM PDT 24 |
43063093 ps |
| T213 |
/workspace/coverage/default/46.sram_ctrl_max_throughput.1539749177 |
|
|
Jul 18 07:20:14 PM PDT 24 |
Jul 18 07:20:29 PM PDT 24 |
2712701676 ps |
| T214 |
/workspace/coverage/default/23.sram_ctrl_lc_escalation.3692207724 |
|
|
Jul 18 07:14:38 PM PDT 24 |
Jul 18 07:15:36 PM PDT 24 |
141695753455 ps |
| T129 |
/workspace/coverage/default/2.sram_ctrl_regwen.4287304525 |
|
|
Jul 18 07:10:18 PM PDT 24 |
Jul 18 07:22:25 PM PDT 24 |
11306096768 ps |
| T215 |
/workspace/coverage/default/28.sram_ctrl_smoke.2011985470 |
|
|
Jul 18 07:15:31 PM PDT 24 |
Jul 18 07:15:47 PM PDT 24 |
843353910 ps |
| T216 |
/workspace/coverage/default/34.sram_ctrl_executable.454294717 |
|
|
Jul 18 07:17:01 PM PDT 24 |
Jul 18 07:30:46 PM PDT 24 |
51292753957 ps |
| T217 |
/workspace/coverage/default/42.sram_ctrl_partial_access.2681936279 |
|
|
Jul 18 07:18:54 PM PDT 24 |
Jul 18 07:20:57 PM PDT 24 |
1633874928 ps |
| T218 |
/workspace/coverage/default/2.sram_ctrl_partial_access.3123063304 |
|
|
Jul 18 07:10:18 PM PDT 24 |
Jul 18 07:12:48 PM PDT 24 |
4085281187 ps |
| T219 |
/workspace/coverage/default/35.sram_ctrl_regwen.3377278341 |
|
|
Jul 18 07:17:14 PM PDT 24 |
Jul 18 07:28:52 PM PDT 24 |
22207476959 ps |
| T220 |
/workspace/coverage/default/46.sram_ctrl_lc_escalation.509892823 |
|
|
Jul 18 07:20:14 PM PDT 24 |
Jul 18 07:20:36 PM PDT 24 |
4929160971 ps |
| T221 |
/workspace/coverage/default/15.sram_ctrl_regwen.1254404036 |
|
|
Jul 18 07:12:55 PM PDT 24 |
Jul 18 07:22:53 PM PDT 24 |
3484009068 ps |
| T222 |
/workspace/coverage/default/40.sram_ctrl_bijection.3768263476 |
|
|
Jul 18 07:18:35 PM PDT 24 |
Jul 18 07:56:45 PM PDT 24 |
63691884098 ps |
| T223 |
/workspace/coverage/default/12.sram_ctrl_partial_access.3282749497 |
|
|
Jul 18 07:12:15 PM PDT 24 |
Jul 18 07:14:29 PM PDT 24 |
4319829105 ps |
| T224 |
/workspace/coverage/default/15.sram_ctrl_stress_pipeline.3011256208 |
|
|
Jul 18 07:12:55 PM PDT 24 |
Jul 18 07:17:45 PM PDT 24 |
17528133103 ps |
| T225 |
/workspace/coverage/default/13.sram_ctrl_regwen.1747403107 |
|
|
Jul 18 07:12:13 PM PDT 24 |
Jul 18 07:14:01 PM PDT 24 |
2144925915 ps |
| T226 |
/workspace/coverage/default/14.sram_ctrl_multiple_keys.2375535915 |
|
|
Jul 18 07:12:18 PM PDT 24 |
Jul 18 07:14:16 PM PDT 24 |
2517939043 ps |
| T227 |
/workspace/coverage/default/20.sram_ctrl_multiple_keys.2153096373 |
|
|
Jul 18 07:13:51 PM PDT 24 |
Jul 18 07:24:59 PM PDT 24 |
15670168549 ps |
| T228 |
/workspace/coverage/default/23.sram_ctrl_access_during_key_req.1456998296 |
|
|
Jul 18 07:14:38 PM PDT 24 |
Jul 18 07:41:21 PM PDT 24 |
13545676002 ps |
| T229 |
/workspace/coverage/default/32.sram_ctrl_smoke.4240425481 |
|
|
Jul 18 07:16:31 PM PDT 24 |
Jul 18 07:17:00 PM PDT 24 |
934862068 ps |
| T230 |
/workspace/coverage/default/36.sram_ctrl_mem_walk.1572475584 |
|
|
Jul 18 07:17:52 PM PDT 24 |
Jul 18 07:20:00 PM PDT 24 |
8223849899 ps |
| T231 |
/workspace/coverage/default/17.sram_ctrl_max_throughput.2826449535 |
|
|
Jul 18 07:12:57 PM PDT 24 |
Jul 18 07:14:02 PM PDT 24 |
758116507 ps |
| T57 |
/workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.2483060384 |
|
|
Jul 18 07:11:06 PM PDT 24 |
Jul 18 07:11:40 PM PDT 24 |
2657247865 ps |
| T232 |
/workspace/coverage/default/46.sram_ctrl_alert_test.2199932064 |
|
|
Jul 18 07:20:30 PM PDT 24 |
Jul 18 07:20:34 PM PDT 24 |
173563614 ps |
| T233 |
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.3569344501 |
|
|
Jul 18 07:21:01 PM PDT 24 |
Jul 18 07:26:58 PM PDT 24 |
26906870257 ps |
| T234 |
/workspace/coverage/default/3.sram_ctrl_max_throughput.1513000891 |
|
|
Jul 18 07:11:02 PM PDT 24 |
Jul 18 07:12:46 PM PDT 24 |
794634406 ps |
| T235 |
/workspace/coverage/default/29.sram_ctrl_ram_cfg.770839970 |
|
|
Jul 18 07:16:00 PM PDT 24 |
Jul 18 07:16:05 PM PDT 24 |
357553148 ps |
| T236 |
/workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.1350007895 |
|
|
Jul 18 07:10:19 PM PDT 24 |
Jul 18 07:11:46 PM PDT 24 |
4416200215 ps |
| T237 |
/workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.1863757830 |
|
|
Jul 18 07:13:07 PM PDT 24 |
Jul 18 07:14:11 PM PDT 24 |
1551088690 ps |
| T238 |
/workspace/coverage/default/4.sram_ctrl_stress_pipeline.3274454332 |
|
|
Jul 18 07:11:03 PM PDT 24 |
Jul 18 07:15:41 PM PDT 24 |
10132459474 ps |
| T239 |
/workspace/coverage/default/47.sram_ctrl_smoke.1501242211 |
|
|
Jul 18 07:20:31 PM PDT 24 |
Jul 18 07:21:26 PM PDT 24 |
3331477874 ps |
| T240 |
/workspace/coverage/default/21.sram_ctrl_alert_test.1048968499 |
|
|
Jul 18 07:14:09 PM PDT 24 |
Jul 18 07:14:14 PM PDT 24 |
34754988 ps |
| T241 |
/workspace/coverage/default/29.sram_ctrl_smoke.32387303 |
|
|
Jul 18 07:16:00 PM PDT 24 |
Jul 18 07:17:19 PM PDT 24 |
435916032 ps |
| T242 |
/workspace/coverage/default/3.sram_ctrl_ram_cfg.4085166041 |
|
|
Jul 18 07:11:01 PM PDT 24 |
Jul 18 07:11:05 PM PDT 24 |
1273391748 ps |
| T243 |
/workspace/coverage/default/27.sram_ctrl_multiple_keys.3627378404 |
|
|
Jul 18 07:15:16 PM PDT 24 |
Jul 18 07:29:47 PM PDT 24 |
30468890103 ps |
| T244 |
/workspace/coverage/default/34.sram_ctrl_smoke.1278824890 |
|
|
Jul 18 07:17:00 PM PDT 24 |
Jul 18 07:17:16 PM PDT 24 |
534410139 ps |
| T245 |
/workspace/coverage/default/32.sram_ctrl_mem_walk.3203182480 |
|
|
Jul 18 07:16:47 PM PDT 24 |
Jul 18 07:21:53 PM PDT 24 |
26247471401 ps |
| T246 |
/workspace/coverage/default/37.sram_ctrl_max_throughput.1557329646 |
|
|
Jul 18 07:17:54 PM PDT 24 |
Jul 18 07:18:35 PM PDT 24 |
739938881 ps |
| T247 |
/workspace/coverage/default/34.sram_ctrl_access_during_key_req.2762764400 |
|
|
Jul 18 07:17:00 PM PDT 24 |
Jul 18 07:39:12 PM PDT 24 |
25117564935 ps |
| T248 |
/workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.484455796 |
|
|
Jul 18 07:13:53 PM PDT 24 |
Jul 18 07:16:43 PM PDT 24 |
3132785746 ps |
| T249 |
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.1051687715 |
|
|
Jul 18 07:19:45 PM PDT 24 |
Jul 18 07:24:08 PM PDT 24 |
6735966839 ps |
| T250 |
/workspace/coverage/default/15.sram_ctrl_ram_cfg.3007192806 |
|
|
Jul 18 07:12:55 PM PDT 24 |
Jul 18 07:13:02 PM PDT 24 |
1297797877 ps |
| T251 |
/workspace/coverage/default/14.sram_ctrl_stress_all.2694382013 |
|
|
Jul 18 07:12:58 PM PDT 24 |
Jul 18 08:28:27 PM PDT 24 |
478727890272 ps |
| T252 |
/workspace/coverage/default/35.sram_ctrl_ram_cfg.2003151261 |
|
|
Jul 18 07:17:28 PM PDT 24 |
Jul 18 07:17:34 PM PDT 24 |
2130657948 ps |
| T253 |
/workspace/coverage/default/38.sram_ctrl_lc_escalation.1000997574 |
|
|
Jul 18 07:18:09 PM PDT 24 |
Jul 18 07:19:34 PM PDT 24 |
38901357582 ps |
| T254 |
/workspace/coverage/default/44.sram_ctrl_executable.3916162863 |
|
|
Jul 18 07:19:46 PM PDT 24 |
Jul 18 07:22:50 PM PDT 24 |
8333974296 ps |
| T255 |
/workspace/coverage/default/20.sram_ctrl_max_throughput.1557740809 |
|
|
Jul 18 07:13:50 PM PDT 24 |
Jul 18 07:14:29 PM PDT 24 |
741261652 ps |
| T256 |
/workspace/coverage/default/26.sram_ctrl_smoke.401346063 |
|
|
Jul 18 07:15:08 PM PDT 24 |
Jul 18 07:15:26 PM PDT 24 |
866584438 ps |
| T257 |
/workspace/coverage/default/22.sram_ctrl_multiple_keys.336260992 |
|
|
Jul 18 07:14:15 PM PDT 24 |
Jul 18 07:22:51 PM PDT 24 |
37577110534 ps |
| T258 |
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.644563544 |
|
|
Jul 18 07:20:15 PM PDT 24 |
Jul 18 07:22:26 PM PDT 24 |
811142727 ps |
| T259 |
/workspace/coverage/default/14.sram_ctrl_access_during_key_req.3732857703 |
|
|
Jul 18 07:12:55 PM PDT 24 |
Jul 18 07:28:56 PM PDT 24 |
12046871250 ps |
| T260 |
/workspace/coverage/default/1.sram_ctrl_stress_all.488188919 |
|
|
Jul 18 07:10:18 PM PDT 24 |
Jul 18 07:42:49 PM PDT 24 |
33021729584 ps |
| T261 |
/workspace/coverage/default/31.sram_ctrl_lc_escalation.2310011319 |
|
|
Jul 18 07:16:29 PM PDT 24 |
Jul 18 07:16:55 PM PDT 24 |
4482868964 ps |
| T262 |
/workspace/coverage/default/28.sram_ctrl_alert_test.4260372974 |
|
|
Jul 18 07:16:10 PM PDT 24 |
Jul 18 07:16:12 PM PDT 24 |
34642645 ps |
| T263 |
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.2497424037 |
|
|
Jul 18 07:20:46 PM PDT 24 |
Jul 18 07:43:58 PM PDT 24 |
16363738787 ps |
| T264 |
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.1171948222 |
|
|
Jul 18 07:11:41 PM PDT 24 |
Jul 18 07:12:50 PM PDT 24 |
7359172363 ps |
| T265 |
/workspace/coverage/default/22.sram_ctrl_alert_test.2706174270 |
|
|
Jul 18 07:14:21 PM PDT 24 |
Jul 18 07:14:25 PM PDT 24 |
15837776 ps |
| T266 |
/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.2966608034 |
|
|
Jul 18 07:12:57 PM PDT 24 |
Jul 18 07:15:38 PM PDT 24 |
3252176730 ps |
| T267 |
/workspace/coverage/default/3.sram_ctrl_multiple_keys.2814655715 |
|
|
Jul 18 07:10:18 PM PDT 24 |
Jul 18 07:24:59 PM PDT 24 |
27628732652 ps |
| T268 |
/workspace/coverage/default/16.sram_ctrl_mem_partial_access.2765289589 |
|
|
Jul 18 07:12:57 PM PDT 24 |
Jul 18 07:14:13 PM PDT 24 |
3816322483 ps |
| T269 |
/workspace/coverage/default/29.sram_ctrl_alert_test.1840078056 |
|
|
Jul 18 07:15:57 PM PDT 24 |
Jul 18 07:15:58 PM PDT 24 |
16066753 ps |
| T270 |
/workspace/coverage/default/47.sram_ctrl_alert_test.270377268 |
|
|
Jul 18 07:20:31 PM PDT 24 |
Jul 18 07:20:35 PM PDT 24 |
14050983 ps |
| T271 |
/workspace/coverage/default/27.sram_ctrl_ram_cfg.53809914 |
|
|
Jul 18 07:15:30 PM PDT 24 |
Jul 18 07:15:34 PM PDT 24 |
1410215706 ps |
| T272 |
/workspace/coverage/default/16.sram_ctrl_alert_test.3590001471 |
|
|
Jul 18 07:13:07 PM PDT 24 |
Jul 18 07:13:10 PM PDT 24 |
42167803 ps |
| T273 |
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.1147821965 |
|
|
Jul 18 07:19:48 PM PDT 24 |
Jul 18 07:19:57 PM PDT 24 |
676580239 ps |
| T274 |
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.3267056161 |
|
|
Jul 18 07:21:01 PM PDT 24 |
Jul 18 07:22:17 PM PDT 24 |
748191915 ps |
| T275 |
/workspace/coverage/default/30.sram_ctrl_lc_escalation.2223470117 |
|
|
Jul 18 07:16:13 PM PDT 24 |
Jul 18 07:17:29 PM PDT 24 |
54141351182 ps |
| T276 |
/workspace/coverage/default/3.sram_ctrl_alert_test.1035593881 |
|
|
Jul 18 07:11:03 PM PDT 24 |
Jul 18 07:11:06 PM PDT 24 |
32116247 ps |
| T277 |
/workspace/coverage/default/35.sram_ctrl_mem_partial_access.2703709457 |
|
|
Jul 18 07:17:28 PM PDT 24 |
Jul 18 07:20:44 PM PDT 24 |
44580229872 ps |
| T278 |
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.4270031328 |
|
|
Jul 18 07:11:08 PM PDT 24 |
Jul 18 07:20:51 PM PDT 24 |
23963170932 ps |
| T279 |
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.151872936 |
|
|
Jul 18 07:19:30 PM PDT 24 |
Jul 18 07:25:17 PM PDT 24 |
7572437993 ps |
| T280 |
/workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.2078272577 |
|
|
Jul 18 07:16:30 PM PDT 24 |
Jul 18 07:16:48 PM PDT 24 |
1699831254 ps |
| T281 |
/workspace/coverage/default/45.sram_ctrl_stress_all.1720842777 |
|
|
Jul 18 07:19:59 PM PDT 24 |
Jul 18 08:26:28 PM PDT 24 |
29949118152 ps |
| T282 |
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.1698240634 |
|
|
Jul 18 07:19:29 PM PDT 24 |
Jul 18 07:24:26 PM PDT 24 |
48912365179 ps |
| T283 |
/workspace/coverage/default/44.sram_ctrl_mem_walk.3533368186 |
|
|
Jul 18 07:19:47 PM PDT 24 |
Jul 18 07:22:37 PM PDT 24 |
5162239562 ps |
| T284 |
/workspace/coverage/default/6.sram_ctrl_regwen.433269868 |
|
|
Jul 18 07:11:07 PM PDT 24 |
Jul 18 07:21:39 PM PDT 24 |
24894915409 ps |
| T285 |
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.1764561448 |
|
|
Jul 18 07:11:42 PM PDT 24 |
Jul 18 07:13:23 PM PDT 24 |
812014097 ps |
| T286 |
/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.1855699403 |
|
|
Jul 18 07:12:54 PM PDT 24 |
Jul 18 07:18:51 PM PDT 24 |
108016529715 ps |
| T287 |
/workspace/coverage/default/45.sram_ctrl_mem_walk.279189683 |
|
|
Jul 18 07:19:59 PM PDT 24 |
Jul 18 07:25:39 PM PDT 24 |
25160871867 ps |
| T288 |
/workspace/coverage/default/28.sram_ctrl_partial_access.3974189940 |
|
|
Jul 18 07:15:39 PM PDT 24 |
Jul 18 07:15:59 PM PDT 24 |
1183867168 ps |
| T108 |
/workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.4030836414 |
|
|
Jul 18 07:10:20 PM PDT 24 |
Jul 18 07:11:30 PM PDT 24 |
2584995144 ps |
| T289 |
/workspace/coverage/default/17.sram_ctrl_regwen.909918668 |
|
|
Jul 18 07:12:55 PM PDT 24 |
Jul 18 07:31:39 PM PDT 24 |
117021046463 ps |
| T290 |
/workspace/coverage/default/20.sram_ctrl_mem_partial_access.2818614216 |
|
|
Jul 18 07:13:53 PM PDT 24 |
Jul 18 07:15:36 PM PDT 24 |
10453903782 ps |
| T291 |
/workspace/coverage/default/27.sram_ctrl_bijection.1923138653 |
|
|
Jul 18 07:15:15 PM PDT 24 |
Jul 18 07:53:39 PM PDT 24 |
38311224175 ps |
| T292 |
/workspace/coverage/default/24.sram_ctrl_mem_partial_access.3868635174 |
|
|
Jul 18 07:14:52 PM PDT 24 |
Jul 18 07:17:37 PM PDT 24 |
10396426945 ps |
| T293 |
/workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.3070394820 |
|
|
Jul 18 07:12:19 PM PDT 24 |
Jul 18 07:14:33 PM PDT 24 |
12802041325 ps |
| T294 |
/workspace/coverage/default/14.sram_ctrl_executable.3908766678 |
|
|
Jul 18 07:12:55 PM PDT 24 |
Jul 18 07:31:32 PM PDT 24 |
11805776713 ps |
| T295 |
/workspace/coverage/default/49.sram_ctrl_alert_test.2720715078 |
|
|
Jul 18 07:21:04 PM PDT 24 |
Jul 18 07:21:10 PM PDT 24 |
46340596 ps |
| T296 |
/workspace/coverage/default/25.sram_ctrl_lc_escalation.1167788769 |
|
|
Jul 18 07:14:54 PM PDT 24 |
Jul 18 07:15:06 PM PDT 24 |
1335254352 ps |
| T297 |
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.3994236360 |
|
|
Jul 18 07:11:45 PM PDT 24 |
Jul 18 07:14:17 PM PDT 24 |
20866096911 ps |
| T298 |
/workspace/coverage/default/48.sram_ctrl_alert_test.1953219115 |
|
|
Jul 18 07:20:46 PM PDT 24 |
Jul 18 07:20:51 PM PDT 24 |
13346467 ps |
| T299 |
/workspace/coverage/default/23.sram_ctrl_ram_cfg.161250248 |
|
|
Jul 18 07:14:39 PM PDT 24 |
Jul 18 07:14:44 PM PDT 24 |
1401134283 ps |
| T300 |
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.289271043 |
|
|
Jul 18 07:11:06 PM PDT 24 |
Jul 18 07:11:18 PM PDT 24 |
1370027710 ps |
| T301 |
/workspace/coverage/default/14.sram_ctrl_ram_cfg.2971042242 |
|
|
Jul 18 07:12:53 PM PDT 24 |
Jul 18 07:12:58 PM PDT 24 |
400057412 ps |
| T302 |
/workspace/coverage/default/37.sram_ctrl_smoke.2866247978 |
|
|
Jul 18 07:17:53 PM PDT 24 |
Jul 18 07:18:01 PM PDT 24 |
2866391478 ps |
| T303 |
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1617155818 |
|
|
Jul 18 07:11:51 PM PDT 24 |
Jul 18 07:12:24 PM PDT 24 |
2772717983 ps |
| T304 |
/workspace/coverage/default/42.sram_ctrl_alert_test.2224679282 |
|
|
Jul 18 07:19:19 PM PDT 24 |
Jul 18 07:19:21 PM PDT 24 |
22080402 ps |
| T305 |
/workspace/coverage/default/6.sram_ctrl_stress_all.208866125 |
|
|
Jul 18 07:11:04 PM PDT 24 |
Jul 18 08:31:58 PM PDT 24 |
116267215768 ps |
| T306 |
/workspace/coverage/default/10.sram_ctrl_regwen.2817625741 |
|
|
Jul 18 07:11:43 PM PDT 24 |
Jul 18 07:35:58 PM PDT 24 |
53931284808 ps |