Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	136714680	1			T1	18320		T2	1029		T3	14
triple_byte_access	2787856	1			T1	16547		T2	1006		T4	2452
halfword_access	4274588	1			T1	25023		T2	1431		T4	3790
byte_access	5970167	1			T1	32977		T2	1861		T4	4900
zero_access	1795100	1			T1	8337		T2	449		T4	1295

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

75464797

1

T1

50877

T2

2881

T3

7

auto[1]

76077594

1

T1

50327

T2

2895

T3

7

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	67916488	1			T1	9306		T2	518		T3	7
auto[0]	triple_byte_access	1332399	1			T1	8211		T2	487		T4	1222
auto[0]	halfword_access	2091789	1			T1	12544		T2	703		T4	1896
auto[0]	byte_access	3057302	1			T1	16589		T2	947		T4	2456
auto[0]	zero_access	1066819	1			T1	4227		T2	226		T4	655
auto[1]	word_access	68798192	1			T1	9014		T2	511		T3	7
auto[1]	triple_byte_access	1455457	1			T1	8336		T2	519		T4	1230
auto[1]	halfword_access	2182799	1			T1	12479		T2	728		T4	1894
auto[1]	byte_access	2912865	1			T1	16388		T2	914		T4	2444
auto[1]	zero_access	728281	1			T1	4110		T2	223		T4	640