| T798 |
/workspace/coverage/default/37.sram_ctrl_regwen.3614208991 |
|
|
Jul 18 07:18:10 PM PDT 24 |
Jul 18 07:35:00 PM PDT 24 |
13670291236 ps |
| T799 |
/workspace/coverage/default/0.sram_ctrl_ram_cfg.858976927 |
|
|
Jul 18 07:10:14 PM PDT 24 |
Jul 18 07:10:19 PM PDT 24 |
695211574 ps |
| T800 |
/workspace/coverage/default/42.sram_ctrl_mem_walk.2115872541 |
|
|
Jul 18 07:19:17 PM PDT 24 |
Jul 18 07:22:09 PM PDT 24 |
27767488950 ps |
| T801 |
/workspace/coverage/default/38.sram_ctrl_stress_pipeline.1591891287 |
|
|
Jul 18 07:18:11 PM PDT 24 |
Jul 18 07:22:44 PM PDT 24 |
46178645063 ps |
| T802 |
/workspace/coverage/default/32.sram_ctrl_regwen.456115422 |
|
|
Jul 18 07:16:47 PM PDT 24 |
Jul 18 07:19:31 PM PDT 24 |
11415831080 ps |
| T803 |
/workspace/coverage/default/42.sram_ctrl_max_throughput.3686322949 |
|
|
Jul 18 07:18:56 PM PDT 24 |
Jul 18 07:20:06 PM PDT 24 |
754589442 ps |
| T804 |
/workspace/coverage/default/33.sram_ctrl_ram_cfg.2650112450 |
|
|
Jul 18 07:16:48 PM PDT 24 |
Jul 18 07:16:53 PM PDT 24 |
362038557 ps |
| T805 |
/workspace/coverage/default/49.sram_ctrl_mem_walk.3395911224 |
|
|
Jul 18 07:21:00 PM PDT 24 |
Jul 18 07:24:28 PM PDT 24 |
103382085460 ps |
| T806 |
/workspace/coverage/default/47.sram_ctrl_regwen.35332494 |
|
|
Jul 18 07:20:31 PM PDT 24 |
Jul 18 07:23:55 PM PDT 24 |
1202249849 ps |
| T807 |
/workspace/coverage/default/21.sram_ctrl_smoke.925991293 |
|
|
Jul 18 07:13:55 PM PDT 24 |
Jul 18 07:14:17 PM PDT 24 |
11456597921 ps |
| T808 |
/workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.1775503928 |
|
|
Jul 18 07:13:35 PM PDT 24 |
Jul 18 07:13:50 PM PDT 24 |
425149556 ps |
| T809 |
/workspace/coverage/default/40.sram_ctrl_ram_cfg.3832531674 |
|
|
Jul 18 07:18:44 PM PDT 24 |
Jul 18 07:18:49 PM PDT 24 |
356552623 ps |
| T810 |
/workspace/coverage/default/27.sram_ctrl_smoke.3219348159 |
|
|
Jul 18 07:15:17 PM PDT 24 |
Jul 18 07:15:29 PM PDT 24 |
784209830 ps |
| T811 |
/workspace/coverage/default/16.sram_ctrl_partial_access.3356063139 |
|
|
Jul 18 07:12:55 PM PDT 24 |
Jul 18 07:13:17 PM PDT 24 |
4630422372 ps |
| T812 |
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.2149678468 |
|
|
Jul 18 07:10:15 PM PDT 24 |
Jul 18 07:16:47 PM PDT 24 |
6975564348 ps |
| T813 |
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.3265811895 |
|
|
Jul 18 07:11:47 PM PDT 24 |
Jul 18 07:13:22 PM PDT 24 |
767118245 ps |
| T814 |
/workspace/coverage/default/22.sram_ctrl_max_throughput.2764640837 |
|
|
Jul 18 07:14:07 PM PDT 24 |
Jul 18 07:15:25 PM PDT 24 |
1495992297 ps |
| T815 |
/workspace/coverage/default/8.sram_ctrl_executable.2638145953 |
|
|
Jul 18 07:11:45 PM PDT 24 |
Jul 18 07:26:52 PM PDT 24 |
50239129978 ps |
| T816 |
/workspace/coverage/default/27.sram_ctrl_access_during_key_req.816078895 |
|
|
Jul 18 07:15:30 PM PDT 24 |
Jul 18 07:22:05 PM PDT 24 |
5077277902 ps |
| T817 |
/workspace/coverage/default/30.sram_ctrl_executable.2388854677 |
|
|
Jul 18 07:16:13 PM PDT 24 |
Jul 18 07:27:32 PM PDT 24 |
4897571988 ps |
| T818 |
/workspace/coverage/default/7.sram_ctrl_mem_walk.2462476215 |
|
|
Jul 18 07:11:49 PM PDT 24 |
Jul 18 07:14:36 PM PDT 24 |
98921089355 ps |
| T819 |
/workspace/coverage/default/49.sram_ctrl_bijection.2037728142 |
|
|
Jul 18 07:20:48 PM PDT 24 |
Jul 18 07:57:30 PM PDT 24 |
350110367316 ps |
| T820 |
/workspace/coverage/default/27.sram_ctrl_max_throughput.1668336117 |
|
|
Jul 18 07:15:24 PM PDT 24 |
Jul 18 07:18:05 PM PDT 24 |
2670811432 ps |
| T821 |
/workspace/coverage/default/6.sram_ctrl_smoke.456470446 |
|
|
Jul 18 07:11:03 PM PDT 24 |
Jul 18 07:11:28 PM PDT 24 |
4126230673 ps |
| T822 |
/workspace/coverage/default/47.sram_ctrl_executable.3792395075 |
|
|
Jul 18 07:20:30 PM PDT 24 |
Jul 18 07:37:56 PM PDT 24 |
33596930860 ps |
| T823 |
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.191168088 |
|
|
Jul 18 07:20:02 PM PDT 24 |
Jul 18 07:22:54 PM PDT 24 |
880030237 ps |
| T824 |
/workspace/coverage/default/32.sram_ctrl_executable.2034385185 |
|
|
Jul 18 07:16:47 PM PDT 24 |
Jul 18 07:27:08 PM PDT 24 |
14237525469 ps |
| T825 |
/workspace/coverage/default/38.sram_ctrl_regwen.70533341 |
|
|
Jul 18 07:18:14 PM PDT 24 |
Jul 18 07:23:03 PM PDT 24 |
5376098361 ps |
| T826 |
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.3635709003 |
|
|
Jul 18 07:20:47 PM PDT 24 |
Jul 18 07:21:18 PM PDT 24 |
3374536367 ps |
| T827 |
/workspace/coverage/default/43.sram_ctrl_alert_test.1392871922 |
|
|
Jul 18 07:19:45 PM PDT 24 |
Jul 18 07:19:49 PM PDT 24 |
43216881 ps |
| T828 |
/workspace/coverage/default/7.sram_ctrl_alert_test.2366860741 |
|
|
Jul 18 07:11:44 PM PDT 24 |
Jul 18 07:11:48 PM PDT 24 |
16578417 ps |
| T829 |
/workspace/coverage/default/0.sram_ctrl_max_throughput.1859360923 |
|
|
Jul 18 07:10:15 PM PDT 24 |
Jul 18 07:10:25 PM PDT 24 |
678796847 ps |
| T830 |
/workspace/coverage/default/26.sram_ctrl_partial_access_b2b.2253186755 |
|
|
Jul 18 07:15:11 PM PDT 24 |
Jul 18 07:25:26 PM PDT 24 |
45288436867 ps |
| T831 |
/workspace/coverage/default/1.sram_ctrl_max_throughput.1001417580 |
|
|
Jul 18 07:10:16 PM PDT 24 |
Jul 18 07:11:06 PM PDT 24 |
1464062478 ps |
| T832 |
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.2256688583 |
|
|
Jul 18 07:20:00 PM PDT 24 |
Jul 18 07:30:36 PM PDT 24 |
85875698981 ps |
| T833 |
/workspace/coverage/default/30.sram_ctrl_max_throughput.1550817009 |
|
|
Jul 18 07:16:14 PM PDT 24 |
Jul 18 07:16:31 PM PDT 24 |
4326953652 ps |
| T834 |
/workspace/coverage/default/44.sram_ctrl_partial_access.2025862878 |
|
|
Jul 18 07:19:45 PM PDT 24 |
Jul 18 07:20:05 PM PDT 24 |
4493484904 ps |
| T835 |
/workspace/coverage/default/34.sram_ctrl_regwen.3420183901 |
|
|
Jul 18 07:17:00 PM PDT 24 |
Jul 18 07:18:51 PM PDT 24 |
2394338555 ps |
| T836 |
/workspace/coverage/default/33.sram_ctrl_stress_pipeline.3848152474 |
|
|
Jul 18 07:16:52 PM PDT 24 |
Jul 18 07:21:56 PM PDT 24 |
26353581403 ps |
| T837 |
/workspace/coverage/default/17.sram_ctrl_bijection.4238559518 |
|
|
Jul 18 07:12:57 PM PDT 24 |
Jul 18 07:23:37 PM PDT 24 |
115957495353 ps |
| T838 |
/workspace/coverage/default/38.sram_ctrl_smoke.4029017852 |
|
|
Jul 18 07:18:11 PM PDT 24 |
Jul 18 07:18:24 PM PDT 24 |
844222339 ps |
| T839 |
/workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.3261018588 |
|
|
Jul 18 07:12:55 PM PDT 24 |
Jul 18 07:13:47 PM PDT 24 |
7251249581 ps |
| T840 |
/workspace/coverage/default/15.sram_ctrl_alert_test.1891740859 |
|
|
Jul 18 07:12:55 PM PDT 24 |
Jul 18 07:12:59 PM PDT 24 |
13974901 ps |
| T841 |
/workspace/coverage/default/45.sram_ctrl_partial_access.3636991069 |
|
|
Jul 18 07:20:00 PM PDT 24 |
Jul 18 07:20:26 PM PDT 24 |
766494184 ps |
| T842 |
/workspace/coverage/default/21.sram_ctrl_max_throughput.1277505777 |
|
|
Jul 18 07:14:07 PM PDT 24 |
Jul 18 07:14:25 PM PDT 24 |
927303930 ps |
| T843 |
/workspace/coverage/default/24.sram_ctrl_stress_all.1521743381 |
|
|
Jul 18 07:14:53 PM PDT 24 |
Jul 18 08:56:47 PM PDT 24 |
352018927895 ps |
| T844 |
/workspace/coverage/default/24.sram_ctrl_stress_pipeline.1625583405 |
|
|
Jul 18 07:14:39 PM PDT 24 |
Jul 18 07:17:33 PM PDT 24 |
12927220061 ps |
| T845 |
/workspace/coverage/default/0.sram_ctrl_smoke.3297974650 |
|
|
Jul 18 07:10:16 PM PDT 24 |
Jul 18 07:10:27 PM PDT 24 |
372075027 ps |
| T846 |
/workspace/coverage/default/9.sram_ctrl_multiple_keys.668740219 |
|
|
Jul 18 07:11:41 PM PDT 24 |
Jul 18 07:17:48 PM PDT 24 |
23056278611 ps |
| T847 |
/workspace/coverage/default/16.sram_ctrl_lc_escalation.1514507851 |
|
|
Jul 18 07:12:57 PM PDT 24 |
Jul 18 07:13:44 PM PDT 24 |
26462815126 ps |
| T848 |
/workspace/coverage/default/5.sram_ctrl_stress_all.357825492 |
|
|
Jul 18 07:11:03 PM PDT 24 |
Jul 18 07:48:48 PM PDT 24 |
244431871038 ps |
| T849 |
/workspace/coverage/default/23.sram_ctrl_mem_partial_access.4014368145 |
|
|
Jul 18 07:14:36 PM PDT 24 |
Jul 18 07:15:46 PM PDT 24 |
5602646546 ps |
| T850 |
/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.151318353 |
|
|
Jul 18 07:18:28 PM PDT 24 |
Jul 18 07:20:36 PM PDT 24 |
3403311576 ps |
| T851 |
/workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.3379032503 |
|
|
Jul 18 07:13:42 PM PDT 24 |
Jul 18 07:13:54 PM PDT 24 |
1444324089 ps |
| T852 |
/workspace/coverage/default/5.sram_ctrl_regwen.2364520512 |
|
|
Jul 18 07:11:04 PM PDT 24 |
Jul 18 07:13:24 PM PDT 24 |
1912160390 ps |
| T853 |
/workspace/coverage/default/4.sram_ctrl_lc_escalation.591032409 |
|
|
Jul 18 07:11:03 PM PDT 24 |
Jul 18 07:11:35 PM PDT 24 |
4474119803 ps |
| T854 |
/workspace/coverage/default/17.sram_ctrl_multiple_keys.3580921896 |
|
|
Jul 18 07:12:57 PM PDT 24 |
Jul 18 07:34:06 PM PDT 24 |
20356334381 ps |
| T855 |
/workspace/coverage/default/32.sram_ctrl_mem_partial_access.1310466936 |
|
|
Jul 18 07:16:51 PM PDT 24 |
Jul 18 07:19:34 PM PDT 24 |
2535166363 ps |
| T856 |
/workspace/coverage/default/39.sram_ctrl_access_during_key_req.3956026711 |
|
|
Jul 18 07:18:27 PM PDT 24 |
Jul 18 07:42:53 PM PDT 24 |
168250995159 ps |
| T857 |
/workspace/coverage/default/38.sram_ctrl_multiple_keys.1286470154 |
|
|
Jul 18 07:18:09 PM PDT 24 |
Jul 18 07:31:40 PM PDT 24 |
13414256464 ps |
| T858 |
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.800389280 |
|
|
Jul 18 07:10:18 PM PDT 24 |
Jul 18 07:12:19 PM PDT 24 |
4118352707 ps |
| T859 |
/workspace/coverage/default/39.sram_ctrl_multiple_keys.1160520187 |
|
|
Jul 18 07:18:11 PM PDT 24 |
Jul 18 07:34:37 PM PDT 24 |
44641282885 ps |
| T860 |
/workspace/coverage/default/18.sram_ctrl_mem_partial_access.3647323623 |
|
|
Jul 18 07:13:34 PM PDT 24 |
Jul 18 07:15:04 PM PDT 24 |
10463843531 ps |
| T861 |
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.2965495357 |
|
|
Jul 18 07:11:02 PM PDT 24 |
Jul 18 07:17:50 PM PDT 24 |
10263766807 ps |
| T862 |
/workspace/coverage/default/48.sram_ctrl_bijection.2932028276 |
|
|
Jul 18 07:20:32 PM PDT 24 |
Jul 18 07:51:29 PM PDT 24 |
160376667343 ps |
| T863 |
/workspace/coverage/default/34.sram_ctrl_stress_pipeline.1005785821 |
|
|
Jul 18 07:17:00 PM PDT 24 |
Jul 18 07:22:39 PM PDT 24 |
16331642779 ps |
| T864 |
/workspace/coverage/default/21.sram_ctrl_partial_access_b2b.1446710568 |
|
|
Jul 18 07:13:55 PM PDT 24 |
Jul 18 07:19:30 PM PDT 24 |
9308003814 ps |
| T865 |
/workspace/coverage/default/9.sram_ctrl_ram_cfg.1372237672 |
|
|
Jul 18 07:11:40 PM PDT 24 |
Jul 18 07:11:45 PM PDT 24 |
365105949 ps |
| T866 |
/workspace/coverage/default/31.sram_ctrl_partial_access_b2b.1677903523 |
|
|
Jul 18 07:16:16 PM PDT 24 |
Jul 18 07:21:49 PM PDT 24 |
6143622051 ps |
| T867 |
/workspace/coverage/default/16.sram_ctrl_stress_pipeline.3842897148 |
|
|
Jul 18 07:12:56 PM PDT 24 |
Jul 18 07:18:49 PM PDT 24 |
10166879365 ps |
| T868 |
/workspace/coverage/default/22.sram_ctrl_stress_pipeline.297229177 |
|
|
Jul 18 07:14:07 PM PDT 24 |
Jul 18 07:19:34 PM PDT 24 |
7364439699 ps |
| T869 |
/workspace/coverage/default/23.sram_ctrl_mem_walk.2563448645 |
|
|
Jul 18 07:14:39 PM PDT 24 |
Jul 18 07:19:50 PM PDT 24 |
35000816474 ps |
| T870 |
/workspace/coverage/default/18.sram_ctrl_stress_pipeline.3902048040 |
|
|
Jul 18 07:13:34 PM PDT 24 |
Jul 18 07:18:42 PM PDT 24 |
4617594364 ps |
| T871 |
/workspace/coverage/default/25.sram_ctrl_multiple_keys.1557003483 |
|
|
Jul 18 07:14:54 PM PDT 24 |
Jul 18 07:36:28 PM PDT 24 |
19716483091 ps |
| T872 |
/workspace/coverage/default/19.sram_ctrl_stress_pipeline.3160171128 |
|
|
Jul 18 07:13:36 PM PDT 24 |
Jul 18 07:20:21 PM PDT 24 |
5403005855 ps |
| T873 |
/workspace/coverage/default/33.sram_ctrl_access_during_key_req.646351072 |
|
|
Jul 18 07:16:52 PM PDT 24 |
Jul 18 07:17:33 PM PDT 24 |
7765298826 ps |
| T874 |
/workspace/coverage/default/21.sram_ctrl_stress_pipeline.1408649900 |
|
|
Jul 18 07:13:59 PM PDT 24 |
Jul 18 07:17:33 PM PDT 24 |
49099250558 ps |
| T875 |
/workspace/coverage/default/4.sram_ctrl_multiple_keys.2085608384 |
|
|
Jul 18 07:11:07 PM PDT 24 |
Jul 18 07:35:58 PM PDT 24 |
22993867519 ps |
| T876 |
/workspace/coverage/default/41.sram_ctrl_bijection.164226926 |
|
|
Jul 18 07:18:43 PM PDT 24 |
Jul 18 07:36:42 PM PDT 24 |
28935536224 ps |
| T877 |
/workspace/coverage/default/16.sram_ctrl_smoke.4147551583 |
|
|
Jul 18 07:12:57 PM PDT 24 |
Jul 18 07:13:07 PM PDT 24 |
814704311 ps |
| T878 |
/workspace/coverage/default/5.sram_ctrl_max_throughput.2367856088 |
|
|
Jul 18 07:11:04 PM PDT 24 |
Jul 18 07:11:33 PM PDT 24 |
5895307528 ps |
| T879 |
/workspace/coverage/default/15.sram_ctrl_stress_all.4154774171 |
|
|
Jul 18 07:12:56 PM PDT 24 |
Jul 18 08:50:23 PM PDT 24 |
65565393814 ps |
| T880 |
/workspace/coverage/default/35.sram_ctrl_max_throughput.3501497977 |
|
|
Jul 18 07:17:14 PM PDT 24 |
Jul 18 07:17:50 PM PDT 24 |
741842338 ps |
| T881 |
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.224521188 |
|
|
Jul 18 07:11:41 PM PDT 24 |
Jul 18 07:12:22 PM PDT 24 |
1404992894 ps |
| T882 |
/workspace/coverage/default/16.sram_ctrl_partial_access_b2b.547448118 |
|
|
Jul 18 07:12:56 PM PDT 24 |
Jul 18 07:22:02 PM PDT 24 |
84509759428 ps |
| T883 |
/workspace/coverage/default/6.sram_ctrl_partial_access.3726711213 |
|
|
Jul 18 07:11:06 PM PDT 24 |
Jul 18 07:11:31 PM PDT 24 |
1466072092 ps |
| T884 |
/workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.3266280538 |
|
|
Jul 18 07:17:29 PM PDT 24 |
Jul 18 07:18:10 PM PDT 24 |
783885871 ps |
| T885 |
/workspace/coverage/default/42.sram_ctrl_ram_cfg.219530642 |
|
|
Jul 18 07:19:20 PM PDT 24 |
Jul 18 07:19:24 PM PDT 24 |
1602172510 ps |
| T886 |
/workspace/coverage/default/16.sram_ctrl_ram_cfg.1351779277 |
|
|
Jul 18 07:12:57 PM PDT 24 |
Jul 18 07:13:05 PM PDT 24 |
5595211682 ps |
| T887 |
/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.4038812536 |
|
|
Jul 18 07:16:32 PM PDT 24 |
Jul 18 07:23:03 PM PDT 24 |
35658831463 ps |
| T888 |
/workspace/coverage/default/12.sram_ctrl_ram_cfg.1260396875 |
|
|
Jul 18 07:12:12 PM PDT 24 |
Jul 18 07:12:18 PM PDT 24 |
1352807113 ps |
| T889 |
/workspace/coverage/default/46.sram_ctrl_ram_cfg.1617691814 |
|
|
Jul 18 07:20:19 PM PDT 24 |
Jul 18 07:20:26 PM PDT 24 |
618570479 ps |
| T890 |
/workspace/coverage/default/13.sram_ctrl_access_during_key_req.3289779609 |
|
|
Jul 18 07:12:13 PM PDT 24 |
Jul 18 07:22:56 PM PDT 24 |
27316296543 ps |
| T891 |
/workspace/coverage/default/0.sram_ctrl_lc_escalation.13101093 |
|
|
Jul 18 07:10:15 PM PDT 24 |
Jul 18 07:11:27 PM PDT 24 |
11741336267 ps |
| T892 |
/workspace/coverage/default/20.sram_ctrl_access_during_key_req.788369904 |
|
|
Jul 18 07:13:59 PM PDT 24 |
Jul 18 07:38:14 PM PDT 24 |
11229367510 ps |
| T893 |
/workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.1532674599 |
|
|
Jul 18 07:16:46 PM PDT 24 |
Jul 18 07:16:55 PM PDT 24 |
379154038 ps |
| T894 |
/workspace/coverage/default/7.sram_ctrl_partial_access.2787853637 |
|
|
Jul 18 07:11:45 PM PDT 24 |
Jul 18 07:12:53 PM PDT 24 |
5566554699 ps |
| T895 |
/workspace/coverage/default/44.sram_ctrl_max_throughput.1557086973 |
|
|
Jul 18 07:19:45 PM PDT 24 |
Jul 18 07:19:58 PM PDT 24 |
2842350808 ps |
| T896 |
/workspace/coverage/default/43.sram_ctrl_max_throughput.1058444829 |
|
|
Jul 18 07:19:30 PM PDT 24 |
Jul 18 07:22:12 PM PDT 24 |
767630077 ps |
| T897 |
/workspace/coverage/default/14.sram_ctrl_alert_test.2289391087 |
|
|
Jul 18 07:12:56 PM PDT 24 |
Jul 18 07:13:00 PM PDT 24 |
13256820 ps |
| T898 |
/workspace/coverage/default/35.sram_ctrl_mem_walk.270003090 |
|
|
Jul 18 07:17:31 PM PDT 24 |
Jul 18 07:22:34 PM PDT 24 |
10717242267 ps |
| T899 |
/workspace/coverage/default/19.sram_ctrl_alert_test.1452281502 |
|
|
Jul 18 07:13:53 PM PDT 24 |
Jul 18 07:13:59 PM PDT 24 |
17093678 ps |
| T900 |
/workspace/coverage/default/39.sram_ctrl_smoke.4132411648 |
|
|
Jul 18 07:18:14 PM PDT 24 |
Jul 18 07:19:23 PM PDT 24 |
1609744980 ps |
| T901 |
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.239871410 |
|
|
Jul 18 07:10:18 PM PDT 24 |
Jul 18 07:12:20 PM PDT 24 |
801983669 ps |
| T902 |
/workspace/coverage/default/46.sram_ctrl_mem_walk.3241371291 |
|
|
Jul 18 07:20:12 PM PDT 24 |
Jul 18 07:25:27 PM PDT 24 |
13978958979 ps |
| T903 |
/workspace/coverage/default/36.sram_ctrl_regwen.2174674144 |
|
|
Jul 18 07:17:52 PM PDT 24 |
Jul 18 07:44:48 PM PDT 24 |
37374614340 ps |
| T904 |
/workspace/coverage/default/43.sram_ctrl_multiple_keys.2745708361 |
|
|
Jul 18 07:19:30 PM PDT 24 |
Jul 18 07:34:19 PM PDT 24 |
16800335291 ps |
| T91 |
/workspace/coverage/default/17.sram_ctrl_mem_partial_access.3380271379 |
|
|
Jul 18 07:13:36 PM PDT 24 |
Jul 18 07:14:55 PM PDT 24 |
5341093548 ps |
| T905 |
/workspace/coverage/default/39.sram_ctrl_stress_all.2909084397 |
|
|
Jul 18 07:18:27 PM PDT 24 |
Jul 18 08:57:47 PM PDT 24 |
68207644101 ps |
| T906 |
/workspace/coverage/default/23.sram_ctrl_stress_all.3634467605 |
|
|
Jul 18 07:14:37 PM PDT 24 |
Jul 18 08:17:30 PM PDT 24 |
171705454800 ps |
| T907 |
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.4004039033 |
|
|
Jul 18 07:11:04 PM PDT 24 |
Jul 18 07:14:24 PM PDT 24 |
2245052734 ps |
| T908 |
/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.3354863333 |
|
|
Jul 18 07:17:03 PM PDT 24 |
Jul 18 07:26:01 PM PDT 24 |
23251549742 ps |
| T909 |
/workspace/coverage/default/27.sram_ctrl_stress_all.3864584972 |
|
|
Jul 18 07:15:31 PM PDT 24 |
Jul 18 10:04:42 PM PDT 24 |
698213631836 ps |
| T910 |
/workspace/coverage/default/6.sram_ctrl_multiple_keys.3603074297 |
|
|
Jul 18 07:11:03 PM PDT 24 |
Jul 18 07:29:43 PM PDT 24 |
17432412674 ps |
| T911 |
/workspace/coverage/default/2.sram_ctrl_alert_test.3378972609 |
|
|
Jul 18 07:10:18 PM PDT 24 |
Jul 18 07:10:26 PM PDT 24 |
31761164 ps |
| T912 |
/workspace/coverage/default/43.sram_ctrl_stress_all.3154508826 |
|
|
Jul 18 07:19:45 PM PDT 24 |
Jul 18 07:22:55 PM PDT 24 |
8217511430 ps |
| T913 |
/workspace/coverage/default/25.sram_ctrl_ram_cfg.2501002916 |
|
|
Jul 18 07:15:08 PM PDT 24 |
Jul 18 07:15:13 PM PDT 24 |
694121174 ps |
| T914 |
/workspace/coverage/default/38.sram_ctrl_partial_access_b2b.2280134816 |
|
|
Jul 18 07:18:10 PM PDT 24 |
Jul 18 07:22:29 PM PDT 24 |
22915288771 ps |
| T915 |
/workspace/coverage/default/44.sram_ctrl_regwen.3084313992 |
|
|
Jul 18 07:19:44 PM PDT 24 |
Jul 18 07:20:48 PM PDT 24 |
10323830887 ps |
| T916 |
/workspace/coverage/default/26.sram_ctrl_multiple_keys.1413686118 |
|
|
Jul 18 07:15:09 PM PDT 24 |
Jul 18 07:25:47 PM PDT 24 |
7878268467 ps |
| T917 |
/workspace/coverage/default/15.sram_ctrl_bijection.3844389451 |
|
|
Jul 18 07:12:56 PM PDT 24 |
Jul 18 07:58:49 PM PDT 24 |
317208281167 ps |
| T918 |
/workspace/coverage/default/18.sram_ctrl_executable.4105055692 |
|
|
Jul 18 07:13:34 PM PDT 24 |
Jul 18 07:29:52 PM PDT 24 |
8342113035 ps |
| T919 |
/workspace/coverage/default/35.sram_ctrl_access_during_key_req.1380845602 |
|
|
Jul 18 07:17:13 PM PDT 24 |
Jul 18 07:21:57 PM PDT 24 |
3815641218 ps |
| T920 |
/workspace/coverage/default/23.sram_ctrl_executable.3520859261 |
|
|
Jul 18 07:14:38 PM PDT 24 |
Jul 18 07:23:51 PM PDT 24 |
28968603342 ps |
| T921 |
/workspace/coverage/default/0.sram_ctrl_alert_test.2502303970 |
|
|
Jul 18 07:10:15 PM PDT 24 |
Jul 18 07:10:22 PM PDT 24 |
41901874 ps |
| T922 |
/workspace/coverage/default/30.sram_ctrl_stress_pipeline.3746113926 |
|
|
Jul 18 07:15:57 PM PDT 24 |
Jul 18 07:22:15 PM PDT 24 |
23723252551 ps |
| T923 |
/workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.317625097 |
|
|
Jul 18 07:18:11 PM PDT 24 |
Jul 18 07:19:05 PM PDT 24 |
1890613241 ps |
| T924 |
/workspace/coverage/default/17.sram_ctrl_partial_access.1787321951 |
|
|
Jul 18 07:13:07 PM PDT 24 |
Jul 18 07:13:32 PM PDT 24 |
3603725497 ps |
| T925 |
/workspace/coverage/default/35.sram_ctrl_stress_pipeline.3912730629 |
|
|
Jul 18 07:17:18 PM PDT 24 |
Jul 18 07:21:22 PM PDT 24 |
4178705145 ps |
| T926 |
/workspace/coverage/default/18.sram_ctrl_access_during_key_req.187623200 |
|
|
Jul 18 07:13:36 PM PDT 24 |
Jul 18 07:33:52 PM PDT 24 |
68057120974 ps |
| T927 |
/workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.3461167802 |
|
|
Jul 18 07:14:10 PM PDT 24 |
Jul 18 07:15:20 PM PDT 24 |
1877056513 ps |
| T928 |
/workspace/coverage/default/44.sram_ctrl_ram_cfg.3856942514 |
|
|
Jul 18 07:19:46 PM PDT 24 |
Jul 18 07:19:53 PM PDT 24 |
1464966292 ps |
| T929 |
/workspace/coverage/default/37.sram_ctrl_mem_partial_access.31548023 |
|
|
Jul 18 07:18:10 PM PDT 24 |
Jul 18 07:19:42 PM PDT 24 |
24528281988 ps |
| T930 |
/workspace/coverage/default/21.sram_ctrl_lc_escalation.3139159102 |
|
|
Jul 18 07:14:07 PM PDT 24 |
Jul 18 07:14:19 PM PDT 24 |
3058549525 ps |
| T931 |
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.2562387281 |
|
|
Jul 18 07:19:59 PM PDT 24 |
Jul 18 07:26:27 PM PDT 24 |
37916050813 ps |
| T932 |
/workspace/coverage/default/24.sram_ctrl_bijection.2414705565 |
|
|
Jul 18 07:14:38 PM PDT 24 |
Jul 18 07:48:42 PM PDT 24 |
441666336132 ps |
| T933 |
/workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.389589585 |
|
|
Jul 18 07:15:23 PM PDT 24 |
Jul 18 07:15:30 PM PDT 24 |
686058932 ps |
| T31 |
/workspace/coverage/default/3.sram_ctrl_sec_cm.1602234051 |
|
|
Jul 18 07:11:08 PM PDT 24 |
Jul 18 07:11:12 PM PDT 24 |
1102223346 ps |
| T934 |
/workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.2244368399 |
|
|
Jul 18 07:16:29 PM PDT 24 |
Jul 18 07:16:50 PM PDT 24 |
753185386 ps |
| T935 |
/workspace/coverage/default/11.sram_ctrl_ram_cfg.2818539427 |
|
|
Jul 18 07:11:44 PM PDT 24 |
Jul 18 07:11:49 PM PDT 24 |
363982671 ps |
| T936 |
/workspace/coverage/default/10.sram_ctrl_bijection.712301974 |
|
|
Jul 18 07:11:47 PM PDT 24 |
Jul 18 07:41:29 PM PDT 24 |
99743393397 ps |
| T937 |
/workspace/coverage/default/1.sram_ctrl_partial_access.1389776620 |
|
|
Jul 18 07:10:14 PM PDT 24 |
Jul 18 07:11:45 PM PDT 24 |
1679167323 ps |
| T938 |
/workspace/coverage/default/27.sram_ctrl_stress_pipeline.2181461126 |
|
|
Jul 18 07:15:23 PM PDT 24 |
Jul 18 07:21:02 PM PDT 24 |
11485962938 ps |
| T939 |
/workspace/coverage/default/3.sram_ctrl_stress_all.1858394097 |
|
|
Jul 18 07:11:04 PM PDT 24 |
Jul 18 07:59:32 PM PDT 24 |
177441316408 ps |
| T940 |
/workspace/coverage/default/16.sram_ctrl_regwen.319576491 |
|
|
Jul 18 07:12:57 PM PDT 24 |
Jul 18 07:27:49 PM PDT 24 |
18347143077 ps |
| T941 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1571090209 |
|
|
Jul 18 06:58:39 PM PDT 24 |
Jul 18 06:58:51 PM PDT 24 |
99922810 ps |
| T62 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.951584941 |
|
|
Jul 18 06:59:02 PM PDT 24 |
Jul 18 06:59:16 PM PDT 24 |
148874594 ps |
| T66 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2208493842 |
|
|
Jul 18 06:58:53 PM PDT 24 |
Jul 18 06:59:05 PM PDT 24 |
19403627 ps |
| T67 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.946536127 |
|
|
Jul 18 06:58:39 PM PDT 24 |
Jul 18 06:58:49 PM PDT 24 |
74782393 ps |
| T63 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.877846934 |
|
|
Jul 18 06:58:42 PM PDT 24 |
Jul 18 06:58:54 PM PDT 24 |
131717768 ps |
| T106 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2699703907 |
|
|
Jul 18 06:58:55 PM PDT 24 |
Jul 18 06:59:07 PM PDT 24 |
22435660 ps |
| T64 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2086680045 |
|
|
Jul 18 06:58:50 PM PDT 24 |
Jul 18 06:59:03 PM PDT 24 |
1365073942 ps |
| T942 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1749208609 |
|
|
Jul 18 06:58:49 PM PDT 24 |
Jul 18 06:59:01 PM PDT 24 |
71682004 ps |
| T101 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2134656891 |
|
|
Jul 18 06:58:54 PM PDT 24 |
Jul 18 06:59:05 PM PDT 24 |
66015172 ps |
| T73 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3683710598 |
|
|
Jul 18 06:58:41 PM PDT 24 |
Jul 18 06:58:52 PM PDT 24 |
13196223 ps |
| T102 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1619164166 |
|
|
Jul 18 06:58:51 PM PDT 24 |
Jul 18 06:59:02 PM PDT 24 |
77068679 ps |
| T107 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2355167950 |
|
|
Jul 18 06:58:40 PM PDT 24 |
Jul 18 06:58:53 PM PDT 24 |
178291577 ps |
| T943 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.282386246 |
|
|
Jul 18 06:58:38 PM PDT 24 |
Jul 18 06:58:50 PM PDT 24 |
389680616 ps |
| T116 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1712091076 |
|
|
Jul 18 06:58:42 PM PDT 24 |
Jul 18 06:58:54 PM PDT 24 |
142895556 ps |
| T103 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3995435342 |
|
|
Jul 18 06:59:02 PM PDT 24 |
Jul 18 06:59:43 PM PDT 24 |
15425919337 ps |
| T944 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.271670345 |
|
|
Jul 18 06:58:51 PM PDT 24 |
Jul 18 06:59:05 PM PDT 24 |
679398426 ps |
| T945 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.4139271273 |
|
|
Jul 18 06:58:40 PM PDT 24 |
Jul 18 06:58:53 PM PDT 24 |
3756844040 ps |
| T74 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.4146014613 |
|
|
Jul 18 06:58:45 PM PDT 24 |
Jul 18 06:58:58 PM PDT 24 |
14714084 ps |
| T946 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2576025851 |
|
|
Jul 18 06:58:50 PM PDT 24 |
Jul 18 06:59:04 PM PDT 24 |
421942403 ps |
| T947 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1849217216 |
|
|
Jul 18 06:58:51 PM PDT 24 |
Jul 18 06:59:05 PM PDT 24 |
517846863 ps |
| T120 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3132974552 |
|
|
Jul 18 06:58:51 PM PDT 24 |
Jul 18 06:59:03 PM PDT 24 |
498063280 ps |
| T113 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.914467860 |
|
|
Jul 18 06:58:57 PM PDT 24 |
Jul 18 06:59:11 PM PDT 24 |
185222142 ps |
| T948 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3209724482 |
|
|
Jul 18 06:58:54 PM PDT 24 |
Jul 18 06:59:09 PM PDT 24 |
710307105 ps |
| T104 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3412531922 |
|
|
Jul 18 06:58:43 PM PDT 24 |
Jul 18 06:58:54 PM PDT 24 |
41764722 ps |
| T125 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3749965270 |
|
|
Jul 18 06:59:01 PM PDT 24 |
Jul 18 06:59:16 PM PDT 24 |
320389577 ps |
| T75 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2188575980 |
|
|
Jul 18 06:58:53 PM PDT 24 |
Jul 18 06:59:05 PM PDT 24 |
19872990 ps |
| T949 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1872591315 |
|
|
Jul 18 06:58:39 PM PDT 24 |
Jul 18 06:58:50 PM PDT 24 |
65149193 ps |
| T76 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2727973721 |
|
|
Jul 18 06:58:38 PM PDT 24 |
Jul 18 06:58:47 PM PDT 24 |
306222018 ps |
| T77 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2018376753 |
|
|
Jul 18 06:58:38 PM PDT 24 |
Jul 18 06:58:47 PM PDT 24 |
33255713 ps |
| T950 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3449950763 |
|
|
Jul 18 06:58:37 PM PDT 24 |
Jul 18 06:58:48 PM PDT 24 |
712362496 ps |
| T951 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.233036158 |
|
|
Jul 18 06:58:41 PM PDT 24 |
Jul 18 06:58:56 PM PDT 24 |
1441305726 ps |
| T952 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.4188322892 |
|
|
Jul 18 06:59:01 PM PDT 24 |
Jul 18 06:59:18 PM PDT 24 |
126379834 ps |
| T78 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2797386207 |
|
|
Jul 18 06:58:40 PM PDT 24 |
Jul 18 06:58:51 PM PDT 24 |
118160402 ps |
| T118 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2886158373 |
|
|
Jul 18 06:58:54 PM PDT 24 |
Jul 18 06:59:07 PM PDT 24 |
949056220 ps |
| T123 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.940627438 |
|
|
Jul 18 06:58:54 PM PDT 24 |
Jul 18 06:59:08 PM PDT 24 |
931265136 ps |
| T105 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1126862017 |
|
|
Jul 18 06:58:58 PM PDT 24 |
Jul 18 06:59:11 PM PDT 24 |
171059422 ps |
| T79 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2328459126 |
|
|
Jul 18 06:58:45 PM PDT 24 |
Jul 18 06:59:23 PM PDT 24 |
3766726467 ps |
| T80 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1459826187 |
|
|
Jul 18 06:59:01 PM PDT 24 |
Jul 18 06:59:15 PM PDT 24 |
16123651 ps |
| T117 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1689117202 |
|
|
Jul 18 06:58:55 PM PDT 24 |
Jul 18 06:59:08 PM PDT 24 |
858230018 ps |
| T953 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2860355109 |
|
|
Jul 18 06:58:54 PM PDT 24 |
Jul 18 06:59:08 PM PDT 24 |
160776261 ps |
| T954 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1473007595 |
|
|
Jul 18 06:58:50 PM PDT 24 |
Jul 18 06:59:04 PM PDT 24 |
349494408 ps |
| T955 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1016492013 |
|
|
Jul 18 06:58:54 PM PDT 24 |
Jul 18 06:59:05 PM PDT 24 |
19775587 ps |
| T82 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2967165524 |
|
|
Jul 18 06:58:51 PM PDT 24 |
Jul 18 06:59:55 PM PDT 24 |
7447986132 ps |
| T956 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2528250565 |
|
|
Jul 18 06:58:54 PM PDT 24 |
Jul 18 06:59:07 PM PDT 24 |
16028961 ps |
| T957 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2929963627 |
|
|
Jul 18 06:58:55 PM PDT 24 |
Jul 18 06:59:09 PM PDT 24 |
1549329016 ps |
| T83 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.749695360 |
|
|
Jul 18 06:58:55 PM PDT 24 |
Jul 18 06:59:36 PM PDT 24 |
14749319881 ps |
| T84 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3856755288 |
|
|
Jul 18 06:58:54 PM PDT 24 |
Jul 18 06:59:31 PM PDT 24 |
33741937146 ps |
| T114 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3200915603 |
|
|
Jul 18 06:58:39 PM PDT 24 |
Jul 18 06:58:50 PM PDT 24 |
477428011 ps |
| T958 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.85674890 |
|
|
Jul 18 06:58:39 PM PDT 24 |
Jul 18 06:58:49 PM PDT 24 |
10961154 ps |
| T959 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.86991303 |
|
|
Jul 18 06:58:39 PM PDT 24 |
Jul 18 06:58:49 PM PDT 24 |
18054658 ps |
| T85 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.881307337 |
|
|
Jul 18 06:58:43 PM PDT 24 |
Jul 18 06:59:25 PM PDT 24 |
12716691760 ps |
| T960 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3429521340 |
|
|
Jul 18 06:58:42 PM PDT 24 |
Jul 18 06:59:46 PM PDT 24 |
10069964464 ps |
| T961 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.507134483 |
|
|
Jul 18 06:59:02 PM PDT 24 |
Jul 18 06:59:19 PM PDT 24 |
6986279112 ps |
| T962 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3038405798 |
|
|
Jul 18 06:58:39 PM PDT 24 |
Jul 18 06:58:52 PM PDT 24 |
36679053 ps |
| T963 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1211913361 |
|
|
Jul 18 06:58:52 PM PDT 24 |
Jul 18 06:59:05 PM PDT 24 |
26228651 ps |
| T964 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.254289377 |
|
|
Jul 18 06:59:01 PM PDT 24 |
Jul 18 06:59:15 PM PDT 24 |
23455583 ps |
| T965 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2170257769 |
|
|
Jul 18 06:58:51 PM PDT 24 |
Jul 18 06:59:02 PM PDT 24 |
162023066 ps |
| T966 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3220608784 |
|
|
Jul 18 06:58:38 PM PDT 24 |
Jul 18 06:58:47 PM PDT 24 |
46211824 ps |
| T967 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.464128160 |
|
|
Jul 18 06:58:57 PM PDT 24 |
Jul 18 06:59:13 PM PDT 24 |
371784329 ps |
| T119 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3265675498 |
|
|
Jul 18 06:58:52 PM PDT 24 |
Jul 18 06:59:04 PM PDT 24 |
288929613 ps |
| T968 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3111965282 |
|
|
Jul 18 06:58:54 PM PDT 24 |
Jul 18 06:59:07 PM PDT 24 |
83615159 ps |
| T969 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3635564837 |
|
|
Jul 18 06:58:40 PM PDT 24 |
Jul 18 06:58:54 PM PDT 24 |
681215881 ps |
| T970 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.90940149 |
|
|
Jul 18 06:58:57 PM PDT 24 |
Jul 18 06:59:14 PM PDT 24 |
135131181 ps |
| T971 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3291573160 |
|
|
Jul 18 06:58:51 PM PDT 24 |
Jul 18 06:59:05 PM PDT 24 |
1503898965 ps |
| T86 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3407965646 |
|
|
Jul 18 06:58:52 PM PDT 24 |
Jul 18 06:59:31 PM PDT 24 |
18484597329 ps |
| T972 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1357304805 |
|
|
Jul 18 06:58:39 PM PDT 24 |
Jul 18 06:58:49 PM PDT 24 |
12278931 ps |
| T973 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1765458800 |
|
|
Jul 18 06:58:38 PM PDT 24 |
Jul 18 06:58:46 PM PDT 24 |
14276747 ps |
| T124 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3926491641 |
|
|
Jul 18 06:58:40 PM PDT 24 |
Jul 18 06:58:52 PM PDT 24 |
227399256 ps |
| T974 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.454340834 |
|
|
Jul 18 06:58:50 PM PDT 24 |
Jul 18 06:59:04 PM PDT 24 |
295432870 ps |
| T975 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2078309947 |
|
|
Jul 18 06:58:58 PM PDT 24 |
Jul 18 06:59:11 PM PDT 24 |
19529003 ps |
| T976 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.846280342 |
|
|
Jul 18 06:58:38 PM PDT 24 |
Jul 18 06:58:49 PM PDT 24 |
287954897 ps |
| T977 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3883938545 |
|
|
Jul 18 06:58:50 PM PDT 24 |
Jul 18 06:59:01 PM PDT 24 |
26582478 ps |
| T978 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.293540699 |
|
|
Jul 18 06:58:53 PM PDT 24 |
Jul 18 06:59:07 PM PDT 24 |
5030143710 ps |
| T979 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3559350829 |
|
|
Jul 18 06:58:57 PM PDT 24 |
Jul 18 06:59:11 PM PDT 24 |
68654945 ps |
| T98 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2478360935 |
|
|
Jul 18 06:58:54 PM PDT 24 |
Jul 18 07:00:07 PM PDT 24 |
37141000097 ps |
| T980 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2892300288 |
|
|
Jul 18 06:58:49 PM PDT 24 |
Jul 18 06:59:04 PM PDT 24 |
80067240 ps |
| T981 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2161230557 |
|
|
Jul 18 06:58:50 PM PDT 24 |
Jul 18 06:59:03 PM PDT 24 |
203137866 ps |
| T92 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.616141625 |
|
|
Jul 18 06:58:56 PM PDT 24 |
Jul 18 06:59:35 PM PDT 24 |
3926602408 ps |
| T93 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3649880079 |
|
|
Jul 18 06:58:41 PM PDT 24 |
Jul 18 06:59:45 PM PDT 24 |
14855511918 ps |
| T982 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.648110743 |
|
|
Jul 18 06:58:41 PM PDT 24 |
Jul 18 06:58:52 PM PDT 24 |
20131709 ps |
| T983 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3720518964 |
|
|
Jul 18 06:59:02 PM PDT 24 |
Jul 18 06:59:16 PM PDT 24 |
361631571 ps |
| T121 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.4250490423 |
|
|
Jul 18 06:58:50 PM PDT 24 |
Jul 18 06:59:03 PM PDT 24 |
321236048 ps |
| T122 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1754881810 |
|
|
Jul 18 06:58:53 PM PDT 24 |
Jul 18 06:59:05 PM PDT 24 |
103653623 ps |
| T984 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2760372689 |
|
|
Jul 18 06:58:40 PM PDT 24 |
Jul 18 06:58:53 PM PDT 24 |
114396082 ps |
| T985 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1036513886 |
|
|
Jul 18 06:58:40 PM PDT 24 |
Jul 18 06:58:54 PM PDT 24 |
135669643 ps |
| T94 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3557928361 |
|
|
Jul 18 06:58:52 PM PDT 24 |
Jul 18 06:59:30 PM PDT 24 |
7461032610 ps |
| T986 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.662265861 |
|
|
Jul 18 06:58:47 PM PDT 24 |
Jul 18 06:58:59 PM PDT 24 |
28569298 ps |
| T987 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2268047301 |
|
|
Jul 18 06:58:39 PM PDT 24 |
Jul 18 06:58:49 PM PDT 24 |
28731908 ps |
| T95 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3365628251 |
|
|
Jul 18 06:58:51 PM PDT 24 |
Jul 18 06:59:29 PM PDT 24 |
7543564381 ps |
| T96 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2270089289 |
|
|
Jul 18 06:58:51 PM PDT 24 |
Jul 18 06:59:03 PM PDT 24 |
15377220 ps |
| T97 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1087453697 |
|
|
Jul 18 06:58:46 PM PDT 24 |
Jul 18 06:58:59 PM PDT 24 |
106296414 ps |
| T988 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1657601811 |
|
|
Jul 18 06:58:38 PM PDT 24 |
Jul 18 06:58:49 PM PDT 24 |
75577875 ps |
| T989 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.937138079 |
|
|
Jul 18 06:58:50 PM PDT 24 |
Jul 18 06:59:01 PM PDT 24 |
15243809 ps |
| T990 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2192249120 |
|
|
Jul 18 06:58:40 PM PDT 24 |
Jul 18 06:59:21 PM PDT 24 |
14213807970 ps |
| T991 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.117622433 |
|
|
Jul 18 06:58:50 PM PDT 24 |
Jul 18 06:59:01 PM PDT 24 |
80873284 ps |
| T992 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1093020363 |
|
|
Jul 18 06:58:57 PM PDT 24 |
Jul 18 06:59:10 PM PDT 24 |
12224203 ps |
| T993 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1738840803 |
|
|
Jul 18 06:58:56 PM PDT 24 |
Jul 18 06:59:12 PM PDT 24 |
1510242399 ps |
| T994 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1535019185 |
|
|
Jul 18 06:58:49 PM PDT 24 |
Jul 18 06:59:03 PM PDT 24 |
134291786 ps |
| T115 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1311054960 |
|
|
Jul 18 06:58:37 PM PDT 24 |
Jul 18 06:58:47 PM PDT 24 |
182113313 ps |
| T995 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1900779296 |
|
|
Jul 18 06:58:57 PM PDT 24 |
Jul 18 06:59:10 PM PDT 24 |
98320148 ps |
| T996 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2752097647 |
|
|
Jul 18 06:58:54 PM PDT 24 |
Jul 18 06:59:06 PM PDT 24 |
13473607 ps |
| T997 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2820476091 |
|
|
Jul 18 06:58:51 PM PDT 24 |
Jul 18 06:59:02 PM PDT 24 |
36553798 ps |
| T998 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2092684287 |
|
|
Jul 18 06:59:02 PM PDT 24 |
Jul 18 07:00:09 PM PDT 24 |
14376376678 ps |
| T999 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.194478689 |
|
|
Jul 18 06:58:43 PM PDT 24 |
Jul 18 06:58:55 PM PDT 24 |
123965075 ps |
| T1000 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2965693486 |
|
|
Jul 18 06:58:39 PM PDT 24 |
Jul 18 06:58:49 PM PDT 24 |
91553051 ps |