Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16383340	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

165920650

1

T1

893

T2

1281

T3

1107

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	89811159	1			T1	2351		T2	3529		T3	2956
values[0x0]	44607380	1			T1	792		T2	1219		T3	930
values[0x1]	47885451	1			T1	1581		T2	2307		T3	1962

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8327275	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

173976715

1

T1

2870

T2

4111

T3

3504

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	562304	1			T2	45		T3	21		T6	621
valid_sources[0x01]	554241	1			T2	33		T3	30		T6	604
valid_sources[0x02]	1414631	1			T2	40		T3	24		T6	668
valid_sources[0x03]	779231	1			T2	111		T3	24		T6	694
valid_sources[0x04]	585896	1			T3	22		T6	668		T11	7
valid_sources[0x05]	594018	1			T3	23		T6	628		T11	7
valid_sources[0x06]	1464093	1			T3	23		T6	622		T11	14
valid_sources[0x07]	618566	1			T3	14		T6	655		T11	17
valid_sources[0x08]	627796	1			T2	4		T3	18		T6	676
valid_sources[0x09]	574632	1			T2	11		T3	28		T6	636
valid_sources[0x0a]	1631276	1			T3	24		T6	674		T11	1
valid_sources[0x0b]	788332	1			T2	108		T3	20		T6	665
valid_sources[0x0c]	645271	1			T2	85		T3	26		T6	697
valid_sources[0x0d]	600816	1			T2	17		T3	29		T6	693
valid_sources[0x0e]	572634	1			T2	11		T3	18		T6	652
valid_sources[0x0f]	609136	1			T3	21		T6	675		T11	5
valid_sources[0x10]	568416	1			T2	65		T3	21		T6	711
valid_sources[0x11]	580485	1			T3	23		T6	728		T11	6
valid_sources[0x12]	637207	1			T3	15		T6	643		T11	8
valid_sources[0x13]	649265	1			T2	18		T3	27		T6	703
valid_sources[0x14]	2474023	1			T2	5		T3	18		T6	662
valid_sources[0x15]	573103	1			T3	13		T6	700		T11	2
valid_sources[0x16]	561314	1			T2	89		T3	29		T6	661
valid_sources[0x17]	3827580	1			T2	174		T3	32		T6	637
valid_sources[0x18]	714747	1			T2	24		T3	22		T6	669
valid_sources[0x19]	785150	1			T2	61		T3	15		T6	615
valid_sources[0x1a]	1101820	1			T3	23		T6	640		T11	7
valid_sources[0x1b]	563587	1			T2	18		T3	19		T6	656
valid_sources[0x1c]	602509	1			T3	19		T6	660		T11	8
valid_sources[0x1d]	552450	1			T2	58		T3	18		T6	651
valid_sources[0x1e]	624917	1			T3	21		T6	716		T11	6
valid_sources[0x1f]	570280	1			T2	11		T3	25		T6	715
valid_sources[0x20]	1130437	1			T2	28		T3	19		T6	690
valid_sources[0x21]	575337	1			T2	10		T3	24		T6	656
valid_sources[0x22]	600390	1			T2	49		T3	19		T6	686
valid_sources[0x23]	597712	1			T2	12		T3	29		T6	608
valid_sources[0x24]	556450	1			T1	2344		T2	53		T3	27
valid_sources[0x25]	588344	1			T3	15		T6	641		T11	3
valid_sources[0x26]	588208	1			T3	24		T6	637		T11	5
valid_sources[0x27]	567872	1			T2	102		T3	33		T6	678
valid_sources[0x28]	562384	1			T2	55		T3	13		T6	680
valid_sources[0x29]	630265	1			T2	9		T3	18		T6	717
valid_sources[0x2a]	640488	1			T3	27		T6	605		T11	9
valid_sources[0x2b]	593877	1			T2	65		T3	23		T6	729
valid_sources[0x2c]	615266	1			T2	15		T3	39		T6	703
valid_sources[0x2d]	624174	1			T2	40		T3	21		T6	709
valid_sources[0x2e]	581922	1			T3	24		T6	670		T11	3
valid_sources[0x2f]	589405	1			T3	20		T6	667		T11	15
valid_sources[0x30]	637182	1			T2	110		T3	24		T6	638
valid_sources[0x31]	570312	1			T2	71		T3	24		T6	689
valid_sources[0x32]	579754	1			T3	24		T6	663		T11	5
valid_sources[0x33]	631855	1			T2	58		T3	35		T6	688
valid_sources[0x34]	585231	1			T2	6		T3	22		T6	712
valid_sources[0x35]	568638	1			T2	53		T3	27		T6	607
valid_sources[0x36]	556277	1			T3	19		T6	670		T11	3
valid_sources[0x37]	613822	1			T2	7		T3	17		T6	684
valid_sources[0x38]	575283	1			T2	3		T3	25		T6	662
valid_sources[0x39]	565589	1			T2	19		T3	26		T6	654
valid_sources[0x3a]	567303	1			T3	25		T6	649		T11	6
valid_sources[0x3b]	605715	1			T2	11		T3	25		T6	706
valid_sources[0x3c]	552860	1			T3	28		T6	684		T11	7
valid_sources[0x3d]	565488	1			T2	36		T3	32		T6	665
valid_sources[0x3e]	622441	1			T2	158		T3	21		T6	717
valid_sources[0x3f]	602614	1			T2	223		T3	21		T6	678
valid_sources[0x40]	563540	1			T2	45		T3	32		T6	618
valid_sources[0x41]	680519	1			T3	21		T6	649		T11	16
valid_sources[0x42]	600482	1			T3	19		T6	672		T11	5
valid_sources[0x43]	604712	1			T3	27		T6	701		T11	3
valid_sources[0x44]	577958	1			T2	14		T3	21		T6	663
valid_sources[0x45]	560380	1			T2	34		T3	24		T6	685
valid_sources[0x46]	687919	1			T2	96		T3	26		T6	690
valid_sources[0x47]	604525	1			T3	28		T6	689		T11	7
valid_sources[0x48]	562238	1			T3	28		T6	677		T11	9
valid_sources[0x49]	570402	1			T2	53		T3	14		T6	714
valid_sources[0x4a]	577689	1			T2	13		T3	23		T6	650
valid_sources[0x4b]	614107	1			T2	4		T3	23		T6	657
valid_sources[0x4c]	578675	1			T3	22		T6	659		T11	18
valid_sources[0x4d]	787837	1			T2	147		T3	33		T6	737
valid_sources[0x4e]	562118	1			T2	66		T3	19		T6	714
valid_sources[0x4f]	592532	1			T3	32		T6	640		T11	4
valid_sources[0x50]	581645	1			T2	32		T3	15		T6	674
valid_sources[0x51]	599254	1			T1	2362		T2	14		T3	16
valid_sources[0x52]	571023	1			T3	23		T6	667		T11	13
valid_sources[0x53]	575596	1			T3	26		T6	591		T11	3
valid_sources[0x54]	623922	1			T2	27		T3	16		T6	662
valid_sources[0x55]	557823	1			T2	59		T3	22		T6	671
valid_sources[0x56]	576072	1			T3	23		T6	653		T11	19
valid_sources[0x57]	630145	1			T2	17		T3	25		T6	665
valid_sources[0x58]	580623	1			T2	11		T3	18		T6	677
valid_sources[0x59]	608808	1			T3	17		T6	716		T11	4
valid_sources[0x5a]	674086	1			T3	35		T6	645		T11	14
valid_sources[0x5b]	594817	1			T2	50		T3	27		T6	716
valid_sources[0x5c]	569291	1			T2	103		T3	21		T6	678
valid_sources[0x5d]	1589272	1			T3	25		T6	691		T11	12
valid_sources[0x5e]	624939	1			T2	45		T3	18		T6	725
valid_sources[0x5f]	555817	1			T2	105		T3	22		T6	657
valid_sources[0x60]	608633	1			T2	27		T3	20		T6	639
valid_sources[0x61]	1425708	1			T2	4		T3	15		T6	688
valid_sources[0x62]	583543	1			T2	44		T3	25		T6	700
valid_sources[0x63]	555609	1			T2	51		T3	33		T6	692
valid_sources[0x64]	563399	1			T3	16		T6	698		T11	5
valid_sources[0x65]	567714	1			T2	34		T3	26		T6	644
valid_sources[0x66]	557488	1			T3	30		T6	685		T11	4
valid_sources[0x67]	585500	1			T2	3		T3	25		T6	626
valid_sources[0x68]	595704	1			T2	11		T3	14		T6	648
valid_sources[0x69]	585369	1			T3	32		T6	642		T11	3
valid_sources[0x6a]	648234	1			T2	30		T3	22		T6	693
valid_sources[0x6b]	579393	1			T2	25		T3	26		T6	682
valid_sources[0x6c]	576929	1			T2	79		T3	18		T6	706
valid_sources[0x6d]	633657	1			T3	21		T6	658		T11	1
valid_sources[0x6e]	560527	1			T3	12		T6	675		T11	17
valid_sources[0x6f]	570919	1			T3	21		T6	674		T11	20
valid_sources[0x70]	562095	1			T2	4		T3	21		T6	669
valid_sources[0x71]	602772	1			T2	1		T3	20		T6	674
valid_sources[0x72]	1390046	1			T2	56		T3	17		T6	673
valid_sources[0x73]	640255	1			T2	77		T3	25		T6	720
valid_sources[0x74]	569815	1			T3	27		T6	666		T11	15
valid_sources[0x75]	599150	1			T2	48		T3	20		T6	649
valid_sources[0x76]	562450	1			T2	41		T3	15		T6	694
valid_sources[0x77]	566476	1			T2	17		T3	23		T6	674
valid_sources[0x78]	641933	1			T2	27		T3	14		T6	679
valid_sources[0x79]	593741	1			T2	19		T3	23		T6	669
valid_sources[0x7a]	607832	1			T2	11		T3	20		T6	648
valid_sources[0x7b]	602954	1			T2	135		T3	27		T6	670
valid_sources[0x7c]	1811862	1			T2	31		T3	21		T6	699
valid_sources[0x7d]	571067	1			T3	25		T6	681		T11	20
valid_sources[0x7e]	623080	1			T2	49		T3	10		T6	744
valid_sources[0x7f]	579526	1			T2	30		T3	28		T6	655
valid_sources[0x80]	627949	1			T2	23		T3	21		T6	720

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

81574179

1

T1

436

T2

649

T3

590

values[0x0]

all_enables

biggest_size

42164652

1

T1

215

T2

294

T3

248

values[0x1]

all_enables

biggest_size

42181819

1

T1

242

T2

338

T3

269

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	45074	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

152549

1

T2

1

T3

1

T6

19

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	54228	1			T6	14		T23	732		T7	37
values[0x0]	69047	1			T2	2		T6	28		T11	1
values[0x1]	74348	1			T1	1		T3	2		T6	27

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34916	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

162707

1

T1

1

T2

1

T3

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	950	1			T6	2		T156	2		T29	11
valid_sources[0x01]	942	1			T157	2		T148	3		T29	7
valid_sources[0x02]	699	1			T23	4		T55	1		T56	107
valid_sources[0x03]	1030	1			T55	1		T147	1		T148	1
valid_sources[0x04]	722	1			T70	1		T29	9		T62	1
valid_sources[0x05]	604	1			T25	3		T55	1		T21	2
valid_sources[0x06]	648	1			T7	1		T59	5		T148	3
valid_sources[0x07]	993	1			T6	1		T30	1		T23	1
valid_sources[0x08]	1316	1			T55	4		T147	1		T157	7
valid_sources[0x09]	610	1			T6	1		T14	6		T8	24
valid_sources[0x0a]	722	1			T6	1		T94	1		T28	3
valid_sources[0x0b]	896	1			T23	1		T114	1		T21	2
valid_sources[0x0c]	725	1			T30	2		T55	1		T21	1
valid_sources[0x0d]	872	1			T6	1		T23	2		T157	2
valid_sources[0x0e]	789	1			T94	1		T28	2		T29	6
valid_sources[0x0f]	685	1			T25	1		T55	1		T145	3
valid_sources[0x10]	708	1			T25	2		T23	7		T28	3
valid_sources[0x11]	521	1			T6	2		T25	1		T47	1
valid_sources[0x12]	508	1			T54	1		T147	1		T21	2
valid_sources[0x13]	983	1			T59	1		T157	2		T148	1
valid_sources[0x14]	826	1			T23	281		T55	1		T94	1
valid_sources[0x15]	737	1			T23	11		T55	1		T59	1
valid_sources[0x16]	849	1			T30	1		T55	2		T21	1
valid_sources[0x17]	877	1			T4	1		T55	2		T158	2
valid_sources[0x18]	805	1			T6	1		T26	1		T55	2
valid_sources[0x19]	502	1			T157	3		T29	6		T73	30
valid_sources[0x1a]	513	1			T25	3		T55	1		T29	10
valid_sources[0x1b]	941	1			T23	267		T55	1		T21	1
valid_sources[0x1c]	736	1			T3	1		T55	1		T56	15
valid_sources[0x1d]	537	1			T54	2		T55	1		T29	6
valid_sources[0x1e]	1001	1			T23	77		T7	1		T82	1
valid_sources[0x1f]	692	1			T6	1		T21	2		T159	16
valid_sources[0x20]	545	1			T7	2		T9	40		T21	4
valid_sources[0x21]	932	1			T6	2		T23	31		T55	1
valid_sources[0x22]	784	1			T11	2		T55	1		T59	1
valid_sources[0x23]	646	1			T23	1		T55	1		T147	1
valid_sources[0x24]	557	1			T23	1		T7	1		T55	1
valid_sources[0x25]	857	1			T7	1		T21	2		T50	1
valid_sources[0x26]	596	1			T23	16		T146	26		T21	1
valid_sources[0x27]	1093	1			T147	1		T160	1		T28	1
valid_sources[0x28]	796	1			T23	3		T7	2		T55	2
valid_sources[0x29]	871	1			T29	8		T161	1		T162	3
valid_sources[0x2a]	827	1			T6	1		T45	1		T163	12
valid_sources[0x2b]	787	1			T28	2		T29	6		T62	1
valid_sources[0x2c]	627	1			T23	1		T147	3		T21	1
valid_sources[0x2d]	536	1			T157	2		T164	6		T29	11
valid_sources[0x2e]	656	1			T145	4		T94	1		T28	11
valid_sources[0x2f]	598	1			T1	1		T6	3		T23	9
valid_sources[0x30]	563	1			T25	3		T14	1		T21	1
valid_sources[0x31]	811	1			T55	1		T20	1		T28	1
valid_sources[0x32]	565	1			T55	2		T144	1		T59	1
valid_sources[0x33]	914	1			T26	3		T23	4		T58	1
valid_sources[0x34]	639	1			T7	1		T21	1		T28	1
valid_sources[0x35]	698	1			T6	1		T30	2		T58	1
valid_sources[0x36]	849	1			T30	1		T58	1		T29	5
valid_sources[0x37]	506	1			T23	1		T7	1		T15	14
valid_sources[0x38]	1052	1			T27	1		T147	1		T58	1
valid_sources[0x39]	1025	1			T30	1		T25	1		T7	2
valid_sources[0x3a]	777	1			T24	40		T157	2		T82	2
valid_sources[0x3b]	659	1			T7	1		T82	1		T29	17
valid_sources[0x3c]	923	1			T13	5		T7	1		T144	1
valid_sources[0x3d]	568	1			T6	2		T30	1		T25	2
valid_sources[0x3e]	499	1			T55	1		T59	6		T165	1
valid_sources[0x3f]	1406	1			T10	1		T23	122		T7	2
valid_sources[0x40]	756	1			T6	1		T23	1		T55	1
valid_sources[0x41]	647	1			T7	1		T147	1		T21	1
valid_sources[0x42]	583	1			T7	1		T55	1		T70	2
valid_sources[0x43]	823	1			T6	1		T7	1		T21	4
valid_sources[0x44]	605	1			T55	2		T147	2		T21	1
valid_sources[0x45]	594	1			T23	3		T60	1		T55	1
valid_sources[0x46]	732	1			T13	15		T25	1		T23	2
valid_sources[0x47]	777	1			T59	2		T157	2		T29	18
valid_sources[0x48]	620	1			T6	1		T21	2		T29	11
valid_sources[0x49]	879	1			T6	1		T23	25		T55	2
valid_sources[0x4a]	968	1			T30	1		T23	1		T21	1
valid_sources[0x4b]	616	1			T2	2		T148	2		T29	8
valid_sources[0x4c]	468	1			T7	1		T147	1		T21	1
valid_sources[0x4d]	818	1			T6	1		T145	1		T147	1
valid_sources[0x4e]	966	1			T30	1		T55	1		T20	3
valid_sources[0x4f]	1217	1			T23	349		T55	1		T21	1
valid_sources[0x50]	689	1			T7	2		T16	1		T21	1
valid_sources[0x51]	780	1			T6	1		T16	2		T58	1
valid_sources[0x52]	544	1			T55	1		T29	3		T73	7
valid_sources[0x53]	643	1			T147	1		T59	1		T156	3
valid_sources[0x54]	850	1			T21	1		T28	161		T157	1
valid_sources[0x55]	728	1			T155	21		T21	1		T157	3
valid_sources[0x56]	538	1			T55	1		T28	2		T29	12
valid_sources[0x57]	733	1			T23	2		T55	2		T166	1
valid_sources[0x58]	558	1			T7	1		T55	1		T147	1
valid_sources[0x59]	826	1			T7	1		T147	1		T21	1
valid_sources[0x5a]	825	1			T6	1		T25	3		T61	2
valid_sources[0x5b]	1186	1			T55	3		T165	1		T29	16
valid_sources[0x5c]	1025	1			T7	2		T144	1		T70	1
valid_sources[0x5d]	1058	1			T6	1		T145	1		T144	1
valid_sources[0x5e]	1025	1			T13	1		T7	1		T55	2
valid_sources[0x5f]	852	1			T6	1		T30	1		T55	3
valid_sources[0x60]	981	1			T23	1		T147	1		T82	2
valid_sources[0x61]	776	1			T31	2		T30	1		T55	2
valid_sources[0x62]	749	1			T30	1		T7	1		T114	1
valid_sources[0x63]	792	1			T28	6		T157	3		T29	5
valid_sources[0x64]	659	1			T23	2		T21	2		T29	7
valid_sources[0x65]	780	1			T23	2		T7	1		T21	3
valid_sources[0x66]	680	1			T6	1		T23	1		T7	1
valid_sources[0x67]	706	1			T30	1		T147	1		T22	105
valid_sources[0x68]	495	1			T23	2		T29	7		T162	3
valid_sources[0x69]	884	1			T70	1		T58	1		T28	1
valid_sources[0x6a]	929	1			T55	2		T70	1		T58	1
valid_sources[0x6b]	815	1			T114	1		T55	1		T28	1
valid_sources[0x6c]	964	1			T55	1		T144	1		T21	3
valid_sources[0x6d]	686	1			T23	3		T55	2		T56	5
valid_sources[0x6e]	730	1			T51	2		T82	1		T29	12
valid_sources[0x6f]	601	1			T55	1		T28	1		T157	3
valid_sources[0x70]	640	1			T26	1		T144	1		T8	17
valid_sources[0x71]	1019	1			T28	1		T167	1		T148	1
valid_sources[0x72]	1032	1			T23	1		T28	19		T29	9
valid_sources[0x73]	800	1			T30	1		T25	1		T7	1
valid_sources[0x74]	738	1			T6	1		T25	2		T147	1
valid_sources[0x75]	550	1			T94	1		T82	1		T29	8
valid_sources[0x76]	932	1			T7	1		T147	1		T21	1
valid_sources[0x77]	813	1			T23	6		T7	2		T55	1
valid_sources[0x78]	799	1			T28	34		T82	1		T29	5
valid_sources[0x79]	930	1			T51	1		T23	4		T21	1
valid_sources[0x7a]	558	1			T7	1		T21	1		T165	2
valid_sources[0x7b]	620	1			T23	2		T55	4		T157	2
valid_sources[0x7c]	708	1			T6	1		T23	4		T168	2
valid_sources[0x7d]	525	1			T59	2		T82	1		T29	4
valid_sources[0x7e]	1029	1			T7	1		T58	2		T157	1
valid_sources[0x7f]	1135	1			T26	1		T55	1		T147	1
valid_sources[0x80]	548	1			T50	1		T28	3		T29	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

41081

1

T6

7

T23

701

T7

20

values[0x0]

all_enables

biggest_size

57050

1

T2

1

T6

9

T5

4

values[0x1]

all_enables

biggest_size

54418

1

T3

1

T6

3

T4

1