Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
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Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block] 100.00 1 100 1 64 64




Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
partial 16288604 1 T1 3831 T2 5774 T3 4741
full_word 162824442 1 T1 893 T2 1281 T3 1107



Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 179112746 1 T1 4724 T2 7055 T3 5848
auto[TlIntgErrCmd] 101 1 T67 9 T68 2 T69 4
auto[TlIntgErrData] 100 1 T67 5 T68 4 T69 1
auto[TlIntgErrBoth] 99 1 T67 6 T68 4 T69 5



Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 86530435 1 T1 2351 T2 3529 T3 2956
auto[1] 92582611 1 T1 2373 T2 3526 T3 2892



Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 7977947 1 T1 1915 T2 2880 T3 2366
auto[TlIntgErrNone] partial auto[1] 8310376 1 T1 1916 T2 2894 T3 2375
auto[TlIntgErrNone] full_word auto[0] 78552363 1 T1 436 T2 649 T3 590
auto[TlIntgErrNone] full_word auto[1] 84272060 1 T1 457 T2 632 T3 517
auto[TlIntgErrCmd] partial auto[0] 37 1 T67 4 T68 1 T69 1
auto[TlIntgErrCmd] partial auto[1] 58 1 T67 4 T68 1 T69 3
auto[TlIntgErrCmd] full_word auto[0] 3 1 T67 1 T137 1 T138 1
auto[TlIntgErrCmd] full_word auto[1] 3 1 T139 1 T137 1 T140 1
auto[TlIntgErrData] partial auto[0] 44 1 T67 2 T69 1 T134 2
auto[TlIntgErrData] partial auto[1] 50 1 T67 2 T68 4 T134 5
auto[TlIntgErrData] full_word auto[0] 3 1 T139 1 T141 1 T133 1
auto[TlIntgErrData] full_word auto[1] 3 1 T67 1 T134 1 T142 1
auto[TlIntgErrBoth] partial auto[0] 37 1 T67 2 T68 2 T69 1
auto[TlIntgErrBoth] partial auto[1] 55 1 T67 4 T68 2 T69 4
auto[TlIntgErrBoth] full_word auto[0] 1 1 T143 1 - - - -
auto[TlIntgErrBoth] full_word auto[1] 6 1 T134 1 T131 1 T139 1

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