Group : dv_base_reg_pkg::mubi_cov#(8,32'h00000096,32'h00000069)::mubi_cg
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Group : dv_base_reg_pkg::mubi_cov#(8,32'h00000096,32'h00000069)::mubi_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_dv_base_reg_0/dv_base_mubi_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
mubi8_cov_of_mubi8_cov_of_tb.dut.u_otp_en_sram_ifetch_mubi_cov_if 100.00 1 100 1 64 64




Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.u_otp_en_sram_ifetch_mubi_cov_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.u_otp_en_sram_ifetch_mubi_cov_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00


Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.u_otp_en_sram_ifetch_mubi_cov_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 10 0 10 100.00 100 1 1 0


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 65 1 T6 1 T146 1 T147 1
others[1] 49 1 T26 1 T147 1 T21 2
others[2] 60 1 T13 1 T26 1 T145 2
others[3] 55 1 T21 2 T148 1 T149 1
others[4] 58 1 T147 1 T22 1 T81 1
others[5] 51 1 T145 1 T147 1 T21 2
others[6] 58 1 T6 1 T21 3 T22 1
others[7] 75 1 T13 2 T24 1 T147 1
false 5774 1 T1 1 T2 1 T3 1
true 643 1 T6 5 T13 5 T24 5

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%