Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	717165	1			T13	33		T24	14		T26	1886
auto[1]	11221517	1			T1	2160		T3	2927		T6	9285
auto[2]	541242	1			T13	14		T24	21		T26	962
auto[3]	10951501	1			T1	2175		T3	2871		T6	4712

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14536031	1			T1	172		T3	181		T6	11656
auto[1]	2223120	1			T1	681		T3	910		T6	1129
auto[2]	2270213	1			T1	690		T3	823		T6	1110
auto[3]	4402061	1			T1	2792		T3	3884		T6	102

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9292965

1

T1

4335

T3

5798

T6

13997

auto[1]

14138460

1

T4

1

T30

4

T60

92112

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	305956	1			T13	30		T24	11		T26	1546
auto[0]	auto[0]	auto[1]	31571	1			T13	1		T24	3		T26	167
auto[0]	auto[0]	auto[2]	31658	1			T13	2		T26	167		T79	116
auto[0]	auto[0]	auto[3]	29523	1			T26	6		T79	503		T145	33
auto[0]	auto[1]	auto[0]	3354305	1			T1	81		T3	89		T6	7715
auto[0]	auto[1]	auto[1]	344549	1			T1	315		T3	493		T6	738
auto[0]	auto[1]	auto[2]	365885	1			T1	370		T3	405		T6	763
auto[0]	auto[1]	auto[3]	343552	1			T1	1394		T3	1940		T6	69
auto[0]	auto[2]	auto[0]	213240	1			T26	780		T79	12		T145	2298
auto[0]	auto[2]	auto[1]	23191	1			T26	99		T79	95		T145	232
auto[0]	auto[2]	auto[2]	26043	1			T13	14		T24	20		T26	76
auto[0]	auto[2]	auto[3]	22435	1			T24	1		T26	7		T79	312
auto[0]	auto[3]	auto[0]	3185271	1			T1	91		T3	92		T6	3941
auto[0]	auto[3]	auto[1]	344134	1			T1	366		T3	417		T6	391
auto[0]	auto[3]	auto[2]	354464	1			T1	320		T3	418		T6	347
auto[0]	auto[3]	auto[3]	317188	1			T1	1398		T3	1944		T6	33
auto[1]	auto[0]	auto[0]	10513	1			T153	1		T150	542		T151	171
auto[1]	auto[0]	auto[1]	47241	1			T150	2416		T151	680		T154	1
auto[1]	auto[0]	auto[2]	47583	1			T150	2523		T151	738		T152	3990
auto[1]	auto[0]	auto[3]	213120	1			T150	11292		T151	3334		T152	18040
auto[1]	auto[1]	auto[0]	3731569	1			T60	38477		T114	77996		T155	4
auto[1]	auto[1]	auto[1]	710779	1			T60	3575		T114	7202		T115	15257
auto[1]	auto[1]	auto[2]	703701	1			T30	1		T60	3911		T114	7840
auto[1]	auto[1]	auto[3]	1667177	1			T60	342		T114	742		T115	67773
auto[1]	auto[2]	auto[0]	7420	1			T150	477		T151	110		T154	3
auto[1]	auto[2]	auto[1]	32955	1			T150	2261		T151	462		T152	3733
auto[1]	auto[2]	auto[2]	39417	1			T150	2078		T151	652		T152	2696
auto[1]	auto[2]	auto[3]	176541	1			T150	9262		T151	2989		T152	11974
auto[1]	auto[3]	auto[0]	3727757	1			T30	3		T60	38126		T114	78101
auto[1]	auto[3]	auto[1]	688700	1			T4	1		T60	3809		T114	7863
auto[1]	auto[3]	auto[2]	701462	1			T60	3518		T114	6974		T155	1
auto[1]	auto[3]	auto[3]	1632525	1			T60	354		T114	746		T115	67826