Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1256141395	222571	0	0
ctrl_regwen_rd_A	1256141395	5015	0	0
exec_rd_A	1256141395	4545	0	0
exec_regwen_rd_A	1256141395	4776	0	0
readback_rd_A	1256141395	3607	0	0
readback_regwen_rd_A	1256141395	2756	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1256141395	222571	0	0
T7	132366	0	0	0
T14	744	0	0	0
T23	83338	3540	0	0
T28	0	4610	0	0
T29	0	4111	0	0
T32	34542	0	0	0
T46	206913	0	0	0
T47	295572	0	0	0
T54	295085	0	0	0
T60	163185	0	0	0
T61	111108	0	0	0
T62	0	6047	0	0
T73	0	1819	0	0
T74	0	4713	0	0
T75	0	5054	0	0
T76	0	1196	0	0
T77	0	1397	0	0
T78	0	1160	0	0
T79	109119	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1256141395	5015	0	0
T7	132366	0	0	0
T14	744	0	0	0
T23	83338	307	0	0
T32	34542	0	0	0
T46	206913	0	0	0
T47	295572	0	0	0
T54	295085	0	0	0
T60	163185	0	0	0
T61	111108	0	0	0
T62	0	612	0	0
T73	0	173	0	0
T75	0	351	0	0
T76	0	162	0	0
T79	109119	0	0	0
T124	0	63	0	0
T125	0	195	0	0
T126	0	197	0	0
T127	0	164	0	0
T128	0	189	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1256141395	4545	0	0
T7	132366	0	0	0
T14	744	0	0	0
T23	83338	284	0	0
T32	34542	0	0	0
T46	206913	0	0	0
T47	295572	0	0	0
T54	295085	0	0	0
T60	163185	0	0	0
T61	111108	0	0	0
T62	0	492	0	0
T73	0	146	0	0
T75	0	313	0	0
T76	0	120	0	0
T79	109119	0	0	0
T124	0	125	0	0
T125	0	180	0	0
T126	0	217	0	0
T127	0	187	0	0
T128	0	202	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1256141395	4776	0	0
T7	132366	0	0	0
T14	744	0	0	0
T23	83338	310	0	0
T32	34542	0	0	0
T46	206913	0	0	0
T47	295572	0	0	0
T54	295085	0	0	0
T60	163185	0	0	0
T61	111108	0	0	0
T62	0	560	0	0
T73	0	146	0	0
T75	0	343	0	0
T76	0	123	0	0
T79	109119	0	0	0
T124	0	63	0	0
T125	0	233	0	0
T126	0	168	0	0
T127	0	145	0	0
T128	0	168	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1256141395	3607	0	0
T7	132366	0	0	0
T14	744	0	0	0
T23	83338	349	0	0
T32	34542	0	0	0
T46	206913	0	0	0
T47	295572	0	0	0
T54	295085	0	0	0
T60	163185	0	0	0
T61	111108	0	0	0
T62	0	485	0	0
T73	0	129	0	0
T75	0	298	0	0
T76	0	96	0	0
T79	109119	0	0	0
T124	0	41	0	0
T125	0	199	0	0
T126	0	193	0	0
T127	0	133	0	0
T128	0	195	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1256141395	2756	0	0
T7	132366	0	0	0
T14	744	0	0	0
T23	83338	223	0	0
T32	34542	0	0	0
T46	206913	0	0	0
T47	295572	0	0	0
T54	295085	0	0	0
T60	163185	0	0	0
T61	111108	0	0	0
T62	0	372	0	0
T73	0	105	0	0
T75	0	318	0	0
T76	0	101	0	0
T79	109119	0	0	0
T124	0	22	0	0
T125	0	126	0	0
T126	0	134	0	0
T127	0	129	0	0
T128	0	103	0	0