| T799 |
/workspace/coverage/default/24.sram_ctrl_regwen.2691797610 |
|
|
Jul 19 06:08:08 PM PDT 24 |
Jul 19 06:19:18 PM PDT 24 |
5214940442 ps |
| T800 |
/workspace/coverage/default/8.sram_ctrl_alert_test.926504714 |
|
|
Jul 19 06:05:07 PM PDT 24 |
Jul 19 06:05:11 PM PDT 24 |
23291498 ps |
| T801 |
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1869318771 |
|
|
Jul 19 06:13:07 PM PDT 24 |
Jul 19 06:16:07 PM PDT 24 |
3339566361 ps |
| T802 |
/workspace/coverage/default/31.sram_ctrl_partial_access_b2b.3409429464 |
|
|
Jul 19 06:09:56 PM PDT 24 |
Jul 19 06:19:32 PM PDT 24 |
24183516820 ps |
| T803 |
/workspace/coverage/default/20.sram_ctrl_regwen.180359354 |
|
|
Jul 19 06:07:21 PM PDT 24 |
Jul 19 06:27:08 PM PDT 24 |
3803946749 ps |
| T804 |
/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.1626429871 |
|
|
Jul 19 06:12:22 PM PDT 24 |
Jul 19 06:14:58 PM PDT 24 |
2707241289 ps |
| T805 |
/workspace/coverage/default/35.sram_ctrl_stress_pipeline.2469119384 |
|
|
Jul 19 06:10:46 PM PDT 24 |
Jul 19 06:12:45 PM PDT 24 |
2502909466 ps |
| T806 |
/workspace/coverage/default/32.sram_ctrl_stress_pipeline.652113507 |
|
|
Jul 19 06:10:06 PM PDT 24 |
Jul 19 06:13:02 PM PDT 24 |
2036682223 ps |
| T807 |
/workspace/coverage/default/31.sram_ctrl_access_during_key_req.532285243 |
|
|
Jul 19 06:09:56 PM PDT 24 |
Jul 19 06:26:22 PM PDT 24 |
21662910268 ps |
| T808 |
/workspace/coverage/default/42.sram_ctrl_stress_all.1020120034 |
|
|
Jul 19 06:12:43 PM PDT 24 |
Jul 19 07:53:53 PM PDT 24 |
150406794156 ps |
| T809 |
/workspace/coverage/default/5.sram_ctrl_max_throughput.465893008 |
|
|
Jul 19 06:04:29 PM PDT 24 |
Jul 19 06:07:01 PM PDT 24 |
849915177 ps |
| T810 |
/workspace/coverage/default/42.sram_ctrl_access_during_key_req.3779808040 |
|
|
Jul 19 06:12:35 PM PDT 24 |
Jul 19 06:14:53 PM PDT 24 |
6520269267 ps |
| T811 |
/workspace/coverage/default/34.sram_ctrl_regwen.3465985394 |
|
|
Jul 19 06:10:38 PM PDT 24 |
Jul 19 06:24:40 PM PDT 24 |
283320578937 ps |
| T812 |
/workspace/coverage/default/26.sram_ctrl_multiple_keys.3360783575 |
|
|
Jul 19 06:08:25 PM PDT 24 |
Jul 19 06:23:15 PM PDT 24 |
40311610374 ps |
| T813 |
/workspace/coverage/default/4.sram_ctrl_max_throughput.3002353184 |
|
|
Jul 19 06:04:22 PM PDT 24 |
Jul 19 06:05:34 PM PDT 24 |
779732967 ps |
| T814 |
/workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.3111529588 |
|
|
Jul 19 06:11:23 PM PDT 24 |
Jul 19 06:13:54 PM PDT 24 |
1786550706 ps |
| T35 |
/workspace/coverage/default/3.sram_ctrl_sec_cm.48264853 |
|
|
Jul 19 06:04:16 PM PDT 24 |
Jul 19 06:04:20 PM PDT 24 |
269466898 ps |
| T815 |
/workspace/coverage/default/48.sram_ctrl_smoke.3149979948 |
|
|
Jul 19 06:14:13 PM PDT 24 |
Jul 19 06:16:36 PM PDT 24 |
808468279 ps |
| T816 |
/workspace/coverage/default/1.sram_ctrl_smoke.1523329755 |
|
|
Jul 19 06:03:55 PM PDT 24 |
Jul 19 06:04:10 PM PDT 24 |
1543691862 ps |
| T817 |
/workspace/coverage/default/31.sram_ctrl_regwen.960188324 |
|
|
Jul 19 06:10:10 PM PDT 24 |
Jul 19 06:13:00 PM PDT 24 |
1325166834 ps |
| T818 |
/workspace/coverage/default/34.sram_ctrl_stress_pipeline.3020654354 |
|
|
Jul 19 06:10:30 PM PDT 24 |
Jul 19 06:13:32 PM PDT 24 |
2707854456 ps |
| T99 |
/workspace/coverage/default/31.sram_ctrl_mem_partial_access.2785559004 |
|
|
Jul 19 06:10:08 PM PDT 24 |
Jul 19 06:11:28 PM PDT 24 |
1469940700 ps |
| T819 |
/workspace/coverage/default/41.sram_ctrl_access_during_key_req.3176863981 |
|
|
Jul 19 06:12:20 PM PDT 24 |
Jul 19 06:31:05 PM PDT 24 |
15344444546 ps |
| T820 |
/workspace/coverage/default/20.sram_ctrl_mem_partial_access.27935852 |
|
|
Jul 19 06:07:29 PM PDT 24 |
Jul 19 06:08:59 PM PDT 24 |
10737929095 ps |
| T821 |
/workspace/coverage/default/16.sram_ctrl_access_during_key_req.1879189934 |
|
|
Jul 19 06:06:31 PM PDT 24 |
Jul 19 06:24:01 PM PDT 24 |
14892486949 ps |
| T822 |
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.3851914167 |
|
|
Jul 19 06:13:48 PM PDT 24 |
Jul 19 06:20:49 PM PDT 24 |
36445351489 ps |
| T823 |
/workspace/coverage/default/38.sram_ctrl_lc_escalation.3012316349 |
|
|
Jul 19 06:11:32 PM PDT 24 |
Jul 19 06:12:27 PM PDT 24 |
32633289004 ps |
| T824 |
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.1833730989 |
|
|
Jul 19 06:12:43 PM PDT 24 |
Jul 19 06:13:04 PM PDT 24 |
737359898 ps |
| T825 |
/workspace/coverage/default/5.sram_ctrl_bijection.1288776147 |
|
|
Jul 19 06:04:31 PM PDT 24 |
Jul 19 06:53:35 PM PDT 24 |
522845570782 ps |
| T826 |
/workspace/coverage/default/40.sram_ctrl_executable.1973184508 |
|
|
Jul 19 06:12:10 PM PDT 24 |
Jul 19 06:17:53 PM PDT 24 |
3693729986 ps |
| T827 |
/workspace/coverage/default/25.sram_ctrl_partial_access.3545352955 |
|
|
Jul 19 06:08:17 PM PDT 24 |
Jul 19 06:08:58 PM PDT 24 |
676563082 ps |
| T828 |
/workspace/coverage/default/49.sram_ctrl_ram_cfg.1344916541 |
|
|
Jul 19 06:14:37 PM PDT 24 |
Jul 19 06:14:41 PM PDT 24 |
695182602 ps |
| T829 |
/workspace/coverage/default/8.sram_ctrl_max_throughput.3018168844 |
|
|
Jul 19 06:05:07 PM PDT 24 |
Jul 19 06:05:46 PM PDT 24 |
4442065313 ps |
| T830 |
/workspace/coverage/default/14.sram_ctrl_stress_all.208863391 |
|
|
Jul 19 06:06:08 PM PDT 24 |
Jul 19 07:53:13 PM PDT 24 |
81742498984 ps |
| T831 |
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3615256505 |
|
|
Jul 19 06:13:50 PM PDT 24 |
Jul 19 06:14:15 PM PDT 24 |
4259656028 ps |
| T832 |
/workspace/coverage/default/37.sram_ctrl_alert_test.1547310641 |
|
|
Jul 19 06:11:34 PM PDT 24 |
Jul 19 06:11:35 PM PDT 24 |
31517993 ps |
| T833 |
/workspace/coverage/default/30.sram_ctrl_bijection.3519590367 |
|
|
Jul 19 06:09:39 PM PDT 24 |
Jul 19 06:36:17 PM PDT 24 |
203978046463 ps |
| T834 |
/workspace/coverage/default/40.sram_ctrl_max_throughput.958040351 |
|
|
Jul 19 06:12:06 PM PDT 24 |
Jul 19 06:12:31 PM PDT 24 |
1476363489 ps |
| T835 |
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.3235071797 |
|
|
Jul 19 06:05:47 PM PDT 24 |
Jul 19 06:13:16 PM PDT 24 |
8668679864 ps |
| T836 |
/workspace/coverage/default/1.sram_ctrl_stress_all.1243020775 |
|
|
Jul 19 06:04:00 PM PDT 24 |
Jul 19 06:35:26 PM PDT 24 |
161257934484 ps |
| T837 |
/workspace/coverage/default/38.sram_ctrl_mem_walk.3020839665 |
|
|
Jul 19 06:11:41 PM PDT 24 |
Jul 19 06:16:45 PM PDT 24 |
21874047739 ps |
| T838 |
/workspace/coverage/default/0.sram_ctrl_bijection.613170612 |
|
|
Jul 19 06:03:44 PM PDT 24 |
Jul 19 06:47:04 PM PDT 24 |
138078502625 ps |
| T839 |
/workspace/coverage/default/47.sram_ctrl_stress_all.525696214 |
|
|
Jul 19 06:14:04 PM PDT 24 |
Jul 19 07:39:14 PM PDT 24 |
40348448224 ps |
| T840 |
/workspace/coverage/default/43.sram_ctrl_ram_cfg.983529365 |
|
|
Jul 19 06:12:50 PM PDT 24 |
Jul 19 06:12:54 PM PDT 24 |
352015558 ps |
| T841 |
/workspace/coverage/default/39.sram_ctrl_stress_pipeline.1985275004 |
|
|
Jul 19 06:11:48 PM PDT 24 |
Jul 19 06:17:26 PM PDT 24 |
5655320069 ps |
| T842 |
/workspace/coverage/default/9.sram_ctrl_max_throughput.570451561 |
|
|
Jul 19 06:05:14 PM PDT 24 |
Jul 19 06:05:24 PM PDT 24 |
1364244346 ps |
| T843 |
/workspace/coverage/default/3.sram_ctrl_stress_pipeline.872675793 |
|
|
Jul 19 06:04:08 PM PDT 24 |
Jul 19 06:10:52 PM PDT 24 |
6031469931 ps |
| T844 |
/workspace/coverage/default/0.sram_ctrl_multiple_keys.3037087071 |
|
|
Jul 19 06:03:44 PM PDT 24 |
Jul 19 06:25:10 PM PDT 24 |
17769563073 ps |
| T845 |
/workspace/coverage/default/30.sram_ctrl_lc_escalation.2662872297 |
|
|
Jul 19 06:09:40 PM PDT 24 |
Jul 19 06:11:19 PM PDT 24 |
68942824126 ps |
| T846 |
/workspace/coverage/default/18.sram_ctrl_multiple_keys.135588862 |
|
|
Jul 19 06:06:49 PM PDT 24 |
Jul 19 06:12:27 PM PDT 24 |
42924165098 ps |
| T847 |
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.1205373820 |
|
|
Jul 19 06:03:56 PM PDT 24 |
Jul 19 06:07:25 PM PDT 24 |
3071520731 ps |
| T848 |
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.3973329652 |
|
|
Jul 19 06:14:12 PM PDT 24 |
Jul 19 06:16:39 PM PDT 24 |
820286092 ps |
| T849 |
/workspace/coverage/default/45.sram_ctrl_regwen.524926893 |
|
|
Jul 19 06:13:32 PM PDT 24 |
Jul 19 06:25:30 PM PDT 24 |
104469278941 ps |
| T850 |
/workspace/coverage/default/5.sram_ctrl_regwen.3297043458 |
|
|
Jul 19 06:04:31 PM PDT 24 |
Jul 19 06:20:44 PM PDT 24 |
3505796013 ps |
| T851 |
/workspace/coverage/default/17.sram_ctrl_partial_access.3199362940 |
|
|
Jul 19 06:06:39 PM PDT 24 |
Jul 19 06:06:46 PM PDT 24 |
795213794 ps |
| T852 |
/workspace/coverage/default/13.sram_ctrl_regwen.3395971049 |
|
|
Jul 19 06:05:58 PM PDT 24 |
Jul 19 06:21:07 PM PDT 24 |
14980291963 ps |
| T853 |
/workspace/coverage/default/0.sram_ctrl_stress_all.3853212459 |
|
|
Jul 19 06:03:55 PM PDT 24 |
Jul 19 07:08:55 PM PDT 24 |
61600023181 ps |
| T854 |
/workspace/coverage/default/21.sram_ctrl_lc_escalation.2622787544 |
|
|
Jul 19 06:07:39 PM PDT 24 |
Jul 19 06:08:25 PM PDT 24 |
12165366423 ps |
| T855 |
/workspace/coverage/default/40.sram_ctrl_mem_partial_access.2882486620 |
|
|
Jul 19 06:12:11 PM PDT 24 |
Jul 19 06:13:33 PM PDT 24 |
12532296095 ps |
| T856 |
/workspace/coverage/default/7.sram_ctrl_smoke.723353110 |
|
|
Jul 19 06:04:45 PM PDT 24 |
Jul 19 06:05:36 PM PDT 24 |
827984427 ps |
| T857 |
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.3639972972 |
|
|
Jul 19 06:14:12 PM PDT 24 |
Jul 19 06:19:34 PM PDT 24 |
23252153202 ps |
| T858 |
/workspace/coverage/default/29.sram_ctrl_multiple_keys.349311773 |
|
|
Jul 19 06:09:19 PM PDT 24 |
Jul 19 06:32:43 PM PDT 24 |
335253797771 ps |
| T859 |
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.1174047721 |
|
|
Jul 19 06:04:54 PM PDT 24 |
Jul 19 06:06:51 PM PDT 24 |
8427572764 ps |
| T860 |
/workspace/coverage/default/31.sram_ctrl_max_throughput.3379167761 |
|
|
Jul 19 06:09:56 PM PDT 24 |
Jul 19 06:10:16 PM PDT 24 |
2578922274 ps |
| T861 |
/workspace/coverage/default/0.sram_ctrl_regwen.2850085029 |
|
|
Jul 19 06:03:52 PM PDT 24 |
Jul 19 06:15:52 PM PDT 24 |
10273271329 ps |
| T862 |
/workspace/coverage/default/2.sram_ctrl_executable.2687777693 |
|
|
Jul 19 06:04:12 PM PDT 24 |
Jul 19 06:18:02 PM PDT 24 |
45930189056 ps |
| T863 |
/workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.2278861392 |
|
|
Jul 19 06:11:33 PM PDT 24 |
Jul 19 06:12:10 PM PDT 24 |
2887053880 ps |
| T864 |
/workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.222773768 |
|
|
Jul 19 06:11:48 PM PDT 24 |
Jul 19 06:11:56 PM PDT 24 |
2800953586 ps |
| T865 |
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.3089091145 |
|
|
Jul 19 06:05:15 PM PDT 24 |
Jul 19 06:09:16 PM PDT 24 |
3754509651 ps |
| T866 |
/workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.390793193 |
|
|
Jul 19 06:08:25 PM PDT 24 |
Jul 19 06:11:52 PM PDT 24 |
3549180157 ps |
| T867 |
/workspace/coverage/default/19.sram_ctrl_partial_access.254797550 |
|
|
Jul 19 06:07:07 PM PDT 24 |
Jul 19 06:09:59 PM PDT 24 |
3131607474 ps |
| T868 |
/workspace/coverage/default/43.sram_ctrl_lc_escalation.451951230 |
|
|
Jul 19 06:12:52 PM PDT 24 |
Jul 19 06:14:20 PM PDT 24 |
54766108154 ps |
| T869 |
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.3372065899 |
|
|
Jul 19 06:14:29 PM PDT 24 |
Jul 19 06:19:04 PM PDT 24 |
32823811562 ps |
| T870 |
/workspace/coverage/default/26.sram_ctrl_partial_access.3458108752 |
|
|
Jul 19 06:08:35 PM PDT 24 |
Jul 19 06:09:19 PM PDT 24 |
720761595 ps |
| T871 |
/workspace/coverage/default/4.sram_ctrl_smoke.2921224718 |
|
|
Jul 19 06:04:20 PM PDT 24 |
Jul 19 06:04:30 PM PDT 24 |
1911860657 ps |
| T872 |
/workspace/coverage/default/30.sram_ctrl_alert_test.3967797926 |
|
|
Jul 19 06:09:57 PM PDT 24 |
Jul 19 06:09:58 PM PDT 24 |
46055432 ps |
| T873 |
/workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.4063278942 |
|
|
Jul 19 06:04:24 PM PDT 24 |
Jul 19 06:05:03 PM PDT 24 |
771908001 ps |
| T874 |
/workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.2407511723 |
|
|
Jul 19 06:10:07 PM PDT 24 |
Jul 19 06:10:23 PM PDT 24 |
703505165 ps |
| T875 |
/workspace/coverage/default/3.sram_ctrl_stress_all.3257203191 |
|
|
Jul 19 06:04:13 PM PDT 24 |
Jul 19 07:18:58 PM PDT 24 |
191307959269 ps |
| T876 |
/workspace/coverage/default/24.sram_ctrl_max_throughput.376145848 |
|
|
Jul 19 06:08:07 PM PDT 24 |
Jul 19 06:09:17 PM PDT 24 |
4818127625 ps |
| T877 |
/workspace/coverage/default/29.sram_ctrl_lc_escalation.777229115 |
|
|
Jul 19 06:09:26 PM PDT 24 |
Jul 19 06:10:05 PM PDT 24 |
30018416772 ps |
| T878 |
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2614107097 |
|
|
Jul 19 06:05:16 PM PDT 24 |
Jul 19 06:05:30 PM PDT 24 |
13359156989 ps |
| T879 |
/workspace/coverage/default/40.sram_ctrl_multiple_keys.3483394651 |
|
|
Jul 19 06:12:02 PM PDT 24 |
Jul 19 06:36:03 PM PDT 24 |
77996897742 ps |
| T880 |
/workspace/coverage/default/32.sram_ctrl_executable.382581453 |
|
|
Jul 19 06:10:19 PM PDT 24 |
Jul 19 06:24:08 PM PDT 24 |
22540619570 ps |
| T881 |
/workspace/coverage/default/38.sram_ctrl_multiple_keys.202932569 |
|
|
Jul 19 06:11:33 PM PDT 24 |
Jul 19 06:35:02 PM PDT 24 |
35826797626 ps |
| T882 |
/workspace/coverage/default/22.sram_ctrl_stress_all.707469362 |
|
|
Jul 19 06:07:52 PM PDT 24 |
Jul 19 07:18:00 PM PDT 24 |
74248860495 ps |
| T883 |
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.2070957202 |
|
|
Jul 19 06:13:42 PM PDT 24 |
Jul 19 06:13:50 PM PDT 24 |
688354496 ps |
| T884 |
/workspace/coverage/default/42.sram_ctrl_bijection.1917112249 |
|
|
Jul 19 06:12:36 PM PDT 24 |
Jul 19 06:46:33 PM PDT 24 |
441930306095 ps |
| T885 |
/workspace/coverage/default/22.sram_ctrl_partial_access.4075377746 |
|
|
Jul 19 06:07:45 PM PDT 24 |
Jul 19 06:08:49 PM PDT 24 |
830402270 ps |
| T886 |
/workspace/coverage/default/28.sram_ctrl_bijection.2768313829 |
|
|
Jul 19 06:09:01 PM PDT 24 |
Jul 19 06:20:37 PM PDT 24 |
84395385080 ps |
| T887 |
/workspace/coverage/default/27.sram_ctrl_max_throughput.3512932240 |
|
|
Jul 19 06:08:46 PM PDT 24 |
Jul 19 06:09:36 PM PDT 24 |
2878790447 ps |
| T888 |
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.2877026236 |
|
|
Jul 19 06:04:31 PM PDT 24 |
Jul 19 06:08:24 PM PDT 24 |
8152881619 ps |
| T889 |
/workspace/coverage/default/8.sram_ctrl_mem_walk.362401691 |
|
|
Jul 19 06:05:09 PM PDT 24 |
Jul 19 06:09:29 PM PDT 24 |
206659644053 ps |
| T890 |
/workspace/coverage/default/14.sram_ctrl_mem_partial_access.3485617082 |
|
|
Jul 19 06:06:06 PM PDT 24 |
Jul 19 06:07:26 PM PDT 24 |
1400427385 ps |
| T891 |
/workspace/coverage/default/38.sram_ctrl_alert_test.1568225813 |
|
|
Jul 19 06:11:40 PM PDT 24 |
Jul 19 06:11:42 PM PDT 24 |
41058670 ps |
| T892 |
/workspace/coverage/default/13.sram_ctrl_smoke.3841936944 |
|
|
Jul 19 06:05:46 PM PDT 24 |
Jul 19 06:06:04 PM PDT 24 |
3026511681 ps |
| T893 |
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.3984030934 |
|
|
Jul 19 06:14:22 PM PDT 24 |
Jul 19 06:15:06 PM PDT 24 |
1695960821 ps |
| T894 |
/workspace/coverage/default/6.sram_ctrl_mem_walk.2441134168 |
|
|
Jul 19 06:04:54 PM PDT 24 |
Jul 19 06:07:44 PM PDT 24 |
28863343484 ps |
| T895 |
/workspace/coverage/default/14.sram_ctrl_ram_cfg.2530642967 |
|
|
Jul 19 06:06:08 PM PDT 24 |
Jul 19 06:06:15 PM PDT 24 |
1770896848 ps |
| T896 |
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.626458130 |
|
|
Jul 19 06:13:06 PM PDT 24 |
Jul 19 06:36:18 PM PDT 24 |
14312964106 ps |
| T897 |
/workspace/coverage/default/14.sram_ctrl_partial_access.2915996689 |
|
|
Jul 19 06:06:07 PM PDT 24 |
Jul 19 06:06:17 PM PDT 24 |
845964232 ps |
| T898 |
/workspace/coverage/default/26.sram_ctrl_stress_pipeline.116381033 |
|
|
Jul 19 06:08:24 PM PDT 24 |
Jul 19 06:13:10 PM PDT 24 |
3278383885 ps |
| T899 |
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.4049950531 |
|
|
Jul 19 06:12:35 PM PDT 24 |
Jul 19 06:13:14 PM PDT 24 |
726611177 ps |
| T900 |
/workspace/coverage/default/42.sram_ctrl_multiple_keys.3434072461 |
|
|
Jul 19 06:12:36 PM PDT 24 |
Jul 19 06:14:48 PM PDT 24 |
39759509940 ps |
| T901 |
/workspace/coverage/default/3.sram_ctrl_partial_access_b2b.3761441240 |
|
|
Jul 19 06:04:15 PM PDT 24 |
Jul 19 06:07:48 PM PDT 24 |
71039535835 ps |
| T902 |
/workspace/coverage/default/12.sram_ctrl_max_throughput.3885174220 |
|
|
Jul 19 06:05:44 PM PDT 24 |
Jul 19 06:05:55 PM PDT 24 |
1468662515 ps |
| T903 |
/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.1752419752 |
|
|
Jul 19 06:07:46 PM PDT 24 |
Jul 19 06:16:56 PM PDT 24 |
17781698061 ps |
| T904 |
/workspace/coverage/default/34.sram_ctrl_bijection.2317351586 |
|
|
Jul 19 06:10:29 PM PDT 24 |
Jul 19 06:24:54 PM PDT 24 |
24320922599 ps |
| T905 |
/workspace/coverage/default/46.sram_ctrl_alert_test.2408747098 |
|
|
Jul 19 06:13:50 PM PDT 24 |
Jul 19 06:13:51 PM PDT 24 |
17869101 ps |
| T906 |
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.2826591876 |
|
|
Jul 19 06:13:33 PM PDT 24 |
Jul 19 06:13:40 PM PDT 24 |
1105196576 ps |
| T907 |
/workspace/coverage/default/23.sram_ctrl_ram_cfg.2518625209 |
|
|
Jul 19 06:07:59 PM PDT 24 |
Jul 19 06:08:09 PM PDT 24 |
1406017732 ps |
| T908 |
/workspace/coverage/default/17.sram_ctrl_ram_cfg.2911271147 |
|
|
Jul 19 06:06:50 PM PDT 24 |
Jul 19 06:06:54 PM PDT 24 |
352967146 ps |
| T909 |
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.111996097 |
|
|
Jul 19 06:04:36 PM PDT 24 |
Jul 19 06:07:07 PM PDT 24 |
9701055409 ps |
| T910 |
/workspace/coverage/default/20.sram_ctrl_lc_escalation.3720885821 |
|
|
Jul 19 06:07:23 PM PDT 24 |
Jul 19 06:08:14 PM PDT 24 |
16290838088 ps |
| T911 |
/workspace/coverage/default/9.sram_ctrl_ram_cfg.2236878332 |
|
|
Jul 19 06:05:09 PM PDT 24 |
Jul 19 06:05:17 PM PDT 24 |
2239655871 ps |
| T912 |
/workspace/coverage/default/43.sram_ctrl_partial_access.1181071739 |
|
|
Jul 19 06:12:51 PM PDT 24 |
Jul 19 06:13:11 PM PDT 24 |
2034451455 ps |
| T913 |
/workspace/coverage/default/27.sram_ctrl_stress_all.3771105281 |
|
|
Jul 19 06:09:05 PM PDT 24 |
Jul 19 08:47:19 PM PDT 24 |
309837404595 ps |
| T914 |
/workspace/coverage/default/10.sram_ctrl_max_throughput.802608930 |
|
|
Jul 19 06:05:19 PM PDT 24 |
Jul 19 06:06:09 PM PDT 24 |
1499687757 ps |
| T915 |
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.972892227 |
|
|
Jul 19 06:05:38 PM PDT 24 |
Jul 19 06:05:50 PM PDT 24 |
2744340735 ps |
| T916 |
/workspace/coverage/default/10.sram_ctrl_bijection.3251822244 |
|
|
Jul 19 06:05:18 PM PDT 24 |
Jul 19 06:30:22 PM PDT 24 |
355125725683 ps |
| T917 |
/workspace/coverage/default/32.sram_ctrl_regwen.1471274451 |
|
|
Jul 19 06:10:13 PM PDT 24 |
Jul 19 06:16:56 PM PDT 24 |
18680035643 ps |
| T918 |
/workspace/coverage/default/4.sram_ctrl_mem_partial_access.1300076131 |
|
|
Jul 19 06:04:23 PM PDT 24 |
Jul 19 06:05:38 PM PDT 24 |
2557586263 ps |
| T919 |
/workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.3397712421 |
|
|
Jul 19 06:07:07 PM PDT 24 |
Jul 19 06:07:15 PM PDT 24 |
1385502452 ps |
| T920 |
/workspace/coverage/default/12.sram_ctrl_smoke.2950395257 |
|
|
Jul 19 06:05:45 PM PDT 24 |
Jul 19 06:05:59 PM PDT 24 |
1007635484 ps |
| T921 |
/workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.3426344683 |
|
|
Jul 19 06:07:22 PM PDT 24 |
Jul 19 06:08:03 PM PDT 24 |
733434770 ps |
| T922 |
/workspace/coverage/default/33.sram_ctrl_lc_escalation.2431476422 |
|
|
Jul 19 06:10:23 PM PDT 24 |
Jul 19 06:11:19 PM PDT 24 |
9349984672 ps |
| T923 |
/workspace/coverage/default/14.sram_ctrl_access_during_key_req.3120654661 |
|
|
Jul 19 06:06:09 PM PDT 24 |
Jul 19 06:30:35 PM PDT 24 |
56924938862 ps |
| T924 |
/workspace/coverage/default/37.sram_ctrl_multiple_keys.3203029534 |
|
|
Jul 19 06:11:18 PM PDT 24 |
Jul 19 06:26:59 PM PDT 24 |
26773211356 ps |
| T925 |
/workspace/coverage/default/34.sram_ctrl_stress_all.1304150558 |
|
|
Jul 19 06:10:45 PM PDT 24 |
Jul 19 07:06:49 PM PDT 24 |
668303528960 ps |
| T926 |
/workspace/coverage/default/22.sram_ctrl_access_during_key_req.3120838985 |
|
|
Jul 19 06:07:53 PM PDT 24 |
Jul 19 06:27:31 PM PDT 24 |
9203001518 ps |
| T927 |
/workspace/coverage/default/45.sram_ctrl_bijection.2328036832 |
|
|
Jul 19 06:13:25 PM PDT 24 |
Jul 19 06:32:05 PM PDT 24 |
257245054107 ps |
| T928 |
/workspace/coverage/default/44.sram_ctrl_stress_all.355637247 |
|
|
Jul 19 06:13:13 PM PDT 24 |
Jul 19 07:33:59 PM PDT 24 |
126789213969 ps |
| T929 |
/workspace/coverage/default/35.sram_ctrl_mem_walk.1341089062 |
|
|
Jul 19 06:10:52 PM PDT 24 |
Jul 19 06:13:39 PM PDT 24 |
9884914023 ps |
| T930 |
/workspace/coverage/default/26.sram_ctrl_ram_cfg.1738595836 |
|
|
Jul 19 06:08:42 PM PDT 24 |
Jul 19 06:09:24 PM PDT 24 |
354825764 ps |
| T931 |
/workspace/coverage/default/10.sram_ctrl_alert_test.3709546657 |
|
|
Jul 19 06:05:24 PM PDT 24 |
Jul 19 06:05:26 PM PDT 24 |
26568436 ps |
| T932 |
/workspace/coverage/default/18.sram_ctrl_mem_walk.1381242203 |
|
|
Jul 19 06:06:55 PM PDT 24 |
Jul 19 06:11:56 PM PDT 24 |
5477881275 ps |
| T933 |
/workspace/coverage/default/35.sram_ctrl_access_during_key_req.109169904 |
|
|
Jul 19 06:10:52 PM PDT 24 |
Jul 19 06:31:08 PM PDT 24 |
34255161937 ps |
| T934 |
/workspace/coverage/default/7.sram_ctrl_regwen.3555987238 |
|
|
Jul 19 06:04:54 PM PDT 24 |
Jul 19 06:19:17 PM PDT 24 |
26780202690 ps |
| T935 |
/workspace/coverage/default/47.sram_ctrl_regwen.191198056 |
|
|
Jul 19 06:14:05 PM PDT 24 |
Jul 19 06:20:54 PM PDT 24 |
6840525790 ps |
| T936 |
/workspace/coverage/default/7.sram_ctrl_ram_cfg.4187721986 |
|
|
Jul 19 06:04:55 PM PDT 24 |
Jul 19 06:04:59 PM PDT 24 |
344555809 ps |
| T937 |
/workspace/coverage/default/20.sram_ctrl_mem_walk.1593368002 |
|
|
Jul 19 06:07:21 PM PDT 24 |
Jul 19 06:12:45 PM PDT 24 |
14106500696 ps |
| T938 |
/workspace/coverage/default/15.sram_ctrl_multiple_keys.3881149297 |
|
|
Jul 19 06:06:13 PM PDT 24 |
Jul 19 06:26:15 PM PDT 24 |
56097120426 ps |
| T939 |
/workspace/coverage/default/7.sram_ctrl_alert_test.3374455322 |
|
|
Jul 19 06:04:55 PM PDT 24 |
Jul 19 06:04:59 PM PDT 24 |
91121283 ps |
| T940 |
/workspace/coverage/default/42.sram_ctrl_max_throughput.24291268 |
|
|
Jul 19 06:12:38 PM PDT 24 |
Jul 19 06:13:02 PM PDT 24 |
908755231 ps |
| T941 |
/workspace/coverage/default/32.sram_ctrl_lc_escalation.3233798142 |
|
|
Jul 19 06:10:10 PM PDT 24 |
Jul 19 06:11:59 PM PDT 24 |
16291368992 ps |
| T942 |
/workspace/coverage/default/19.sram_ctrl_regwen.3820403774 |
|
|
Jul 19 06:07:17 PM PDT 24 |
Jul 19 06:20:51 PM PDT 24 |
21942998880 ps |
| T943 |
/workspace/coverage/default/49.sram_ctrl_lc_escalation.1698491050 |
|
|
Jul 19 06:14:31 PM PDT 24 |
Jul 19 06:15:35 PM PDT 24 |
44168334339 ps |
| T944 |
/workspace/coverage/default/15.sram_ctrl_mem_walk.1868815303 |
|
|
Jul 19 06:06:25 PM PDT 24 |
Jul 19 06:09:24 PM PDT 24 |
57659851220 ps |
| T945 |
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.2418798490 |
|
|
Jul 19 06:14:35 PM PDT 24 |
Jul 19 06:14:55 PM PDT 24 |
487790920 ps |
| T71 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.845635161 |
|
|
Jul 19 04:52:07 PM PDT 24 |
Jul 19 04:52:57 PM PDT 24 |
7309603114 ps |
| T946 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3255879305 |
|
|
Jul 19 04:52:15 PM PDT 24 |
Jul 19 04:52:19 PM PDT 24 |
97879916 ps |
| T67 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2053886403 |
|
|
Jul 19 04:52:22 PM PDT 24 |
Jul 19 04:52:26 PM PDT 24 |
212338073 ps |
| T72 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1611634654 |
|
|
Jul 19 04:52:23 PM PDT 24 |
Jul 19 04:52:27 PM PDT 24 |
20857359 ps |
| T947 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2174443498 |
|
|
Jul 19 04:51:53 PM PDT 24 |
Jul 19 04:51:56 PM PDT 24 |
42700770 ps |
| T68 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1371537717 |
|
|
Jul 19 04:51:34 PM PDT 24 |
Jul 19 04:51:41 PM PDT 24 |
466708618 ps |
| T120 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.805645263 |
|
|
Jul 19 04:52:25 PM PDT 24 |
Jul 19 04:52:29 PM PDT 24 |
14803676 ps |
| T83 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.581022382 |
|
|
Jul 19 04:52:14 PM PDT 24 |
Jul 19 04:52:16 PM PDT 24 |
128229233 ps |
| T109 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.405516295 |
|
|
Jul 19 04:52:02 PM PDT 24 |
Jul 19 04:52:56 PM PDT 24 |
64107316605 ps |
| T110 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.824646901 |
|
|
Jul 19 04:52:21 PM PDT 24 |
Jul 19 04:52:23 PM PDT 24 |
45114510 ps |
| T121 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.394517246 |
|
|
Jul 19 04:51:34 PM PDT 24 |
Jul 19 04:51:40 PM PDT 24 |
32485795 ps |
| T948 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3992127937 |
|
|
Jul 19 04:52:23 PM PDT 24 |
Jul 19 04:52:27 PM PDT 24 |
15345513 ps |
| T949 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2880983373 |
|
|
Jul 19 04:52:05 PM PDT 24 |
Jul 19 04:52:10 PM PDT 24 |
127028613 ps |
| T950 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3100883041 |
|
|
Jul 19 04:52:07 PM PDT 24 |
Jul 19 04:52:14 PM PDT 24 |
733691585 ps |
| T111 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3691721753 |
|
|
Jul 19 04:51:53 PM PDT 24 |
Jul 19 04:52:22 PM PDT 24 |
3868432181 ps |
| T951 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2915947428 |
|
|
Jul 19 04:51:55 PM PDT 24 |
Jul 19 04:51:59 PM PDT 24 |
37097125 ps |
| T69 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.4140065197 |
|
|
Jul 19 04:51:33 PM PDT 24 |
Jul 19 04:51:39 PM PDT 24 |
175873805 ps |
| T134 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.888047081 |
|
|
Jul 19 04:52:14 PM PDT 24 |
Jul 19 04:52:18 PM PDT 24 |
330785208 ps |
| T122 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2416601468 |
|
|
Jul 19 04:51:45 PM PDT 24 |
Jul 19 04:51:48 PM PDT 24 |
18088014 ps |
| T123 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2104946714 |
|
|
Jul 19 04:51:33 PM PDT 24 |
Jul 19 04:51:38 PM PDT 24 |
18934082 ps |
| T112 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.2182659178 |
|
|
Jul 19 04:51:53 PM PDT 24 |
Jul 19 04:51:54 PM PDT 24 |
39356683 ps |
| T952 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2672895084 |
|
|
Jul 19 04:52:25 PM PDT 24 |
Jul 19 04:52:32 PM PDT 24 |
712316401 ps |
| T131 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.557677852 |
|
|
Jul 19 04:51:56 PM PDT 24 |
Jul 19 04:52:00 PM PDT 24 |
346617149 ps |
| T113 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.523345228 |
|
|
Jul 19 04:51:48 PM PDT 24 |
Jul 19 04:51:51 PM PDT 24 |
52617327 ps |
| T953 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1119628230 |
|
|
Jul 19 04:52:03 PM PDT 24 |
Jul 19 04:52:08 PM PDT 24 |
1577976054 ps |
| T954 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1343035319 |
|
|
Jul 19 04:52:24 PM PDT 24 |
Jul 19 04:52:29 PM PDT 24 |
86442596 ps |
| T84 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1876863892 |
|
|
Jul 19 04:51:53 PM PDT 24 |
Jul 19 04:51:55 PM PDT 24 |
13495641 ps |
| T955 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.301761928 |
|
|
Jul 19 04:51:52 PM PDT 24 |
Jul 19 04:51:55 PM PDT 24 |
375107479 ps |
| T956 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1190122683 |
|
|
Jul 19 04:52:22 PM PDT 24 |
Jul 19 04:52:26 PM PDT 24 |
100201863 ps |
| T957 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.180075149 |
|
|
Jul 19 04:51:45 PM PDT 24 |
Jul 19 04:51:50 PM PDT 24 |
66799644 ps |
| T85 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2340959282 |
|
|
Jul 19 04:51:46 PM PDT 24 |
Jul 19 04:52:19 PM PDT 24 |
15368891568 ps |
| T86 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3770834757 |
|
|
Jul 19 04:51:44 PM PDT 24 |
Jul 19 04:52:41 PM PDT 24 |
29405146570 ps |
| T958 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.407330785 |
|
|
Jul 19 04:51:44 PM PDT 24 |
Jul 19 04:51:47 PM PDT 24 |
341575121 ps |
| T959 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3451885899 |
|
|
Jul 19 04:51:44 PM PDT 24 |
Jul 19 04:51:47 PM PDT 24 |
461574683 ps |
| T87 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1577828236 |
|
|
Jul 19 04:51:45 PM PDT 24 |
Jul 19 04:51:48 PM PDT 24 |
49051345 ps |
| T960 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3981786499 |
|
|
Jul 19 04:51:46 PM PDT 24 |
Jul 19 04:51:49 PM PDT 24 |
24316023 ps |
| T961 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1417301121 |
|
|
Jul 19 04:52:14 PM PDT 24 |
Jul 19 04:52:18 PM PDT 24 |
371959210 ps |
| T88 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2062201791 |
|
|
Jul 19 04:52:06 PM PDT 24 |
Jul 19 04:52:36 PM PDT 24 |
10278641267 ps |
| T135 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.74446214 |
|
|
Jul 19 04:51:54 PM PDT 24 |
Jul 19 04:51:58 PM PDT 24 |
556988396 ps |
| T89 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3246572361 |
|
|
Jul 19 04:51:53 PM PDT 24 |
Jul 19 04:52:23 PM PDT 24 |
3710621748 ps |
| T962 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3210593411 |
|
|
Jul 19 04:51:56 PM PDT 24 |
Jul 19 04:51:58 PM PDT 24 |
68227128 ps |
| T963 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3179038610 |
|
|
Jul 19 04:51:44 PM PDT 24 |
Jul 19 04:51:49 PM PDT 24 |
709020673 ps |
| T964 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.89187937 |
|
|
Jul 19 04:51:35 PM PDT 24 |
Jul 19 04:51:44 PM PDT 24 |
1409067018 ps |
| T90 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.558926110 |
|
|
Jul 19 04:52:06 PM PDT 24 |
Jul 19 04:52:09 PM PDT 24 |
111855428 ps |
| T965 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3213256625 |
|
|
Jul 19 04:52:51 PM PDT 24 |
Jul 19 04:52:57 PM PDT 24 |
591323672 ps |
| T91 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.635032745 |
|
|
Jul 19 04:52:08 PM PDT 24 |
Jul 19 04:52:38 PM PDT 24 |
7863467320 ps |
| T966 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1788529421 |
|
|
Jul 19 04:52:23 PM PDT 24 |
Jul 19 04:52:27 PM PDT 24 |
16223528 ps |
| T967 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3108133364 |
|
|
Jul 19 04:51:44 PM PDT 24 |
Jul 19 04:51:46 PM PDT 24 |
24108230 ps |
| T968 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.214846107 |
|
|
Jul 19 04:52:15 PM PDT 24 |
Jul 19 04:52:17 PM PDT 24 |
22845007 ps |
| T969 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1157953119 |
|
|
Jul 19 04:51:54 PM PDT 24 |
Jul 19 04:51:59 PM PDT 24 |
38291844 ps |
| T970 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.4082844374 |
|
|
Jul 19 04:51:53 PM PDT 24 |
Jul 19 04:51:59 PM PDT 24 |
352238006 ps |
| T971 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2616814273 |
|
|
Jul 19 04:51:33 PM PDT 24 |
Jul 19 04:51:43 PM PDT 24 |
263359512 ps |
| T972 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1220526672 |
|
|
Jul 19 04:51:45 PM PDT 24 |
Jul 19 04:51:48 PM PDT 24 |
15103408 ps |
| T973 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.4281983179 |
|
|
Jul 19 04:51:44 PM PDT 24 |
Jul 19 04:51:48 PM PDT 24 |
48668172 ps |
| T92 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1600308027 |
|
|
Jul 19 04:51:47 PM PDT 24 |
Jul 19 04:51:50 PM PDT 24 |
62647247 ps |
| T974 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3108448351 |
|
|
Jul 19 04:51:54 PM PDT 24 |
Jul 19 04:51:57 PM PDT 24 |
83059965 ps |
| T975 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2581143912 |
|
|
Jul 19 04:51:32 PM PDT 24 |
Jul 19 04:51:38 PM PDT 24 |
47938070 ps |
| T136 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2648181908 |
|
|
Jul 19 04:51:42 PM PDT 24 |
Jul 19 04:51:46 PM PDT 24 |
1130324003 ps |
| T976 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2365894540 |
|
|
Jul 19 04:52:14 PM PDT 24 |
Jul 19 04:52:16 PM PDT 24 |
24444970 ps |
| T977 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1019115201 |
|
|
Jul 19 04:51:58 PM PDT 24 |
Jul 19 04:52:02 PM PDT 24 |
476077860 ps |
| T93 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2488401054 |
|
|
Jul 19 04:51:42 PM PDT 24 |
Jul 19 04:52:34 PM PDT 24 |
14672976395 ps |
| T978 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2119529599 |
|
|
Jul 19 04:51:46 PM PDT 24 |
Jul 19 04:51:50 PM PDT 24 |
25768630 ps |
| T139 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.568309155 |
|
|
Jul 19 04:52:14 PM PDT 24 |
Jul 19 04:52:16 PM PDT 24 |
761443380 ps |
| T142 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.4061933488 |
|
|
Jul 19 04:52:22 PM PDT 24 |
Jul 19 04:52:27 PM PDT 24 |
1278816268 ps |
| T979 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3594205485 |
|
|
Jul 19 04:52:07 PM PDT 24 |
Jul 19 04:52:11 PM PDT 24 |
44450842 ps |
| T980 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1802337316 |
|
|
Jul 19 04:51:45 PM PDT 24 |
Jul 19 04:51:49 PM PDT 24 |
43420037 ps |
| T981 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.118080357 |
|
|
Jul 19 04:51:33 PM PDT 24 |
Jul 19 04:51:41 PM PDT 24 |
249791048 ps |
| T982 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3406646782 |
|
|
Jul 19 04:52:23 PM PDT 24 |
Jul 19 04:52:26 PM PDT 24 |
111442746 ps |
| T137 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3869217456 |
|
|
Jul 19 04:52:18 PM PDT 24 |
Jul 19 04:52:21 PM PDT 24 |
291794942 ps |
| T140 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1556153162 |
|
|
Jul 19 04:51:58 PM PDT 24 |
Jul 19 04:52:01 PM PDT 24 |
154819304 ps |
| T141 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1957083196 |
|
|
Jul 19 04:51:43 PM PDT 24 |
Jul 19 04:51:47 PM PDT 24 |
899317154 ps |
| T983 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1619040369 |
|
|
Jul 19 04:52:22 PM PDT 24 |
Jul 19 04:52:26 PM PDT 24 |
47234014 ps |
| T984 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1601673965 |
|
|
Jul 19 04:51:44 PM PDT 24 |
Jul 19 04:51:51 PM PDT 24 |
1187377118 ps |
| T985 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.565975777 |
|
|
Jul 19 04:51:34 PM PDT 24 |
Jul 19 04:52:33 PM PDT 24 |
29417575828 ps |
| T986 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.442352635 |
|
|
Jul 19 04:51:52 PM PDT 24 |
Jul 19 04:52:21 PM PDT 24 |
3873690244 ps |
| T987 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.67772813 |
|
|
Jul 19 04:52:21 PM PDT 24 |
Jul 19 04:52:26 PM PDT 24 |
354533655 ps |
| T988 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1754492405 |
|
|
Jul 19 04:51:54 PM PDT 24 |
Jul 19 04:51:57 PM PDT 24 |
19950240 ps |
| T989 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2296712172 |
|
|
Jul 19 04:52:18 PM PDT 24 |
Jul 19 04:53:12 PM PDT 24 |
9111875574 ps |
| T990 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1728586356 |
|
|
Jul 19 04:52:24 PM PDT 24 |
Jul 19 04:52:31 PM PDT 24 |
441037308 ps |
| T991 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1547912926 |
|
|
Jul 19 04:52:09 PM PDT 24 |
Jul 19 04:52:11 PM PDT 24 |
44523946 ps |
| T992 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2216812369 |
|
|
Jul 19 04:51:44 PM PDT 24 |
Jul 19 04:51:46 PM PDT 24 |
37233269 ps |
| T993 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1537458716 |
|
|
Jul 19 04:52:24 PM PDT 24 |
Jul 19 04:53:27 PM PDT 24 |
29413487089 ps |
| T994 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.4248646057 |
|
|
Jul 19 04:52:18 PM PDT 24 |
Jul 19 04:52:48 PM PDT 24 |
14778279300 ps |
| T995 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2845538906 |
|
|
Jul 19 04:51:44 PM PDT 24 |
Jul 19 04:51:50 PM PDT 24 |
43900700 ps |
| T996 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1677867423 |
|
|
Jul 19 04:51:55 PM PDT 24 |
Jul 19 04:52:00 PM PDT 24 |
363710503 ps |
| T997 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3376823769 |
|
|
Jul 19 04:51:46 PM PDT 24 |
Jul 19 04:51:51 PM PDT 24 |
162914415 ps |
| T100 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2970361555 |
|
|
Jul 19 04:52:22 PM PDT 24 |
Jul 19 04:53:12 PM PDT 24 |
14434321403 ps |
| T998 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1059580363 |
|
|
Jul 19 04:52:01 PM PDT 24 |
Jul 19 04:52:03 PM PDT 24 |
73149216 ps |
| T143 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.4269056047 |
|
|
Jul 19 04:51:56 PM PDT 24 |
Jul 19 04:52:01 PM PDT 24 |
942988143 ps |
| T999 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1275105383 |
|
|
Jul 19 04:51:56 PM PDT 24 |
Jul 19 04:51:59 PM PDT 24 |
12967157 ps |
| T105 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3599876667 |
|
|
Jul 19 04:51:32 PM PDT 24 |
Jul 19 04:51:38 PM PDT 24 |
98683107 ps |
| T132 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1277307495 |
|
|
Jul 19 04:52:07 PM PDT 24 |
Jul 19 04:52:12 PM PDT 24 |
662139796 ps |
| T1000 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1582119243 |
|
|
Jul 19 04:51:58 PM PDT 24 |
Jul 19 04:52:00 PM PDT 24 |
59761875 ps |
| T1001 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3245540976 |
|
|
Jul 19 04:52:06 PM PDT 24 |
Jul 19 04:52:08 PM PDT 24 |
88577282 ps |
| T106 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3747600840 |
|
|
Jul 19 04:51:45 PM PDT 24 |
Jul 19 04:51:48 PM PDT 24 |
41497843 ps |
| T101 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3355784484 |
|
|
Jul 19 04:51:30 PM PDT 24 |
Jul 19 04:52:25 PM PDT 24 |
7334942661 ps |
| T1002 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.266403138 |
|
|
Jul 19 04:51:45 PM PDT 24 |
Jul 19 04:51:48 PM PDT 24 |
41151847 ps |
| T1003 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.900099245 |
|
|
Jul 19 04:51:56 PM PDT 24 |
Jul 19 04:52:00 PM PDT 24 |
102034998 ps |
| T1004 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3468269976 |
|
|
Jul 19 04:52:25 PM PDT 24 |
Jul 19 04:52:29 PM PDT 24 |
20600775 ps |
| T1005 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1337697719 |
|
|
Jul 19 04:52:22 PM PDT 24 |
Jul 19 04:52:24 PM PDT 24 |
23664663 ps |
| T1006 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1197266271 |
|
|
Jul 19 04:52:02 PM PDT 24 |
Jul 19 04:52:07 PM PDT 24 |
71522762 ps |